{ "schemaVersion": 1, "project": { "name": "AMS Signals", "scope": "Public factual signals in RNM and mixed-signal verification.", "notes": [ "Each Event states only what its representative public sources directly support; source modality limits what the record establishes.", "The absence of a public Event is not evidence that a company or person lacks related internal activity.", "An employer move or acquisition alone does not establish methodology transfer.", "Standards participation alone does not establish internal deployment." ] }, "companies": [ { "id": "advantest", "name": "Advantest", "lastReviewed": "2026-09-02" }, { "id": "allegro-microsystems", "name": "Allegro MicroSystems", "lastReviewed": "2026-10-05" }, { "id": "amd", "name": "AMD", "lastReviewed": "2026-09-09" }, { "id": "ams-osram", "name": "ams OSRAM", "lastReviewed": "2026-10-05" }, { "id": "analog-devices", "name": "Analog Devices", "lastReviewed": "2026-10-15" }, { "id": "analog-port", "name": "Analog Port", "lastReviewed": "2026-09-25" }, { "id": "apple", "name": "Apple", "lastReviewed": "2026-10-15" }, { "id": "arago", "name": "Arago", "lastReviewed": "2026-09-09" }, { "id": "asfigo", "name": "AsFigo", "lastReviewed": "2026-10-25" }, { "id": "astera-labs", "name": "Astera Labs", "lastReviewed": "2026-10-05" }, { "id": "atrisa", "name": "Atrisa", "lastReviewed": "2026-10-25" }, { "id": "ayar-labs", "name": "Ayar Labs", "lastReviewed": "2026-09-09" }, { "id": "betasoft", "name": "Betasoft Consulting", "lastReviewed": "2026-10-19" }, { "id": "blue-origin", "name": "Blue Origin", "lastReviewed": "2026-10-25" }, { "id": "bosch", "name": "Bosch", "lastReviewed": "2026-10-05" }, { "id": "bosch-sensortec", "name": "Bosch Sensortec", "lastReviewed": "2026-08-30" }, { "id": "broadcom", "name": "Broadcom", "lastReviewed": "2026-09-21" }, { "id": "cadence", "name": "Cadence", "lastReviewed": "2026-09-09" }, { "id": "celera-semiconductor", "name": "Celera Semiconductor", "lastReviewed": "2026-10-19" }, { "id": "chipagents", "name": "ChipAgents", "lastReviewed": "2026-09-02" }, { "id": "cirrus-logic", "name": "Cirrus Logic", "lastReviewed": "2026-10-06" }, { "id": "coseda-technologies", "name": "COSEDA", "lastReviewed": "2026-08-31" }, { "id": "credo", "name": "Credo", "lastReviewed": "2026-09-21" }, { "id": "designers-guide-consulting", "name": "Designer's Guide", "lastReviewed": "2026-08-31" }, { "id": "ekepower", "name": "EKEPOWER", "lastReviewed": "2026-09-07" }, { "id": "eliyan", "name": "Eliyan", "lastReviewed": "2026-08-31" }, { "id": "encore-semi", "name": "Encore Semi", "lastReviewed": "2026-10-05" }, { "id": "enphase", "name": "Enphase Energy", "lastReviewed": "2026-09-25" }, { "id": "ensilica", "name": "EnSilica", "lastReviewed": "2026-10-19" }, { "id": "google", "name": "Google", "lastReviewed": "2026-09-14" }, { "id": "hitachi", "name": "Hitachi", "lastReviewed": "2026-08-30" }, { "id": "hmt-microelectronic", "name": "HMT Microelectronic", "lastReviewed": "2026-10-09" }, { "id": "hewlett-packard", "name": "HP", "lastReviewed": "2026-08-30" }, { "id": "ibm", "name": "IBM", "lastReviewed": "2026-08-30" }, { "id": "imms", "name": "IMMS", "lastReviewed": "2026-10-05" }, { "id": "infineon", "name": "Infineon", "lastReviewed": "2026-10-15" }, { "id": "innophase", "name": "InnoPhase", "lastReviewed": "2026-08-31" }, { "id": "intel", "name": "Intel", "lastReviewed": "2026-09-02" }, { "id": "keysight", "name": "Keysight", "lastReviewed": "2026-10-15" }, { "id": "kioxia", "name": "KIOXIA", "lastReviewed": "2026-08-30" }, { "id": "maieutic-semiconductors", "name": "Maieutic Semiconductors", "lastReviewed": "2026-10-19" }, { "id": "marvell", "name": "Marvell", "lastReviewed": "2026-10-05" }, { "id": "mathworks", "name": "MathWorks", "lastReviewed": "2026-08-30" }, { "id": "mediatek", "name": "MediaTek", "lastReviewed": "2026-10-06" }, { "id": "medtronic", "name": "Medtronic", "lastReviewed": "2026-08-30" }, { "id": "melexis", "name": "Melexis", "lastReviewed": "2026-10-15" }, { "id": "meta", "name": "Meta", "lastReviewed": "2026-08-30" }, { "id": "microchip", "name": "Microchip", "lastReviewed": "2026-09-25" }, { "id": "micron", "name": "Micron", "lastReviewed": "2026-10-15" }, { "id": "microsoft", "name": "Microsoft", "lastReviewed": "2026-10-25" }, { "id": "monolithic-power-systems", "name": "Monolithic Power Systems", "lastReviewed": "2026-10-06" }, { "id": "mythic", "name": "Mythic", "lastReviewed": "2026-08-31" }, { "id": "neurophos", "name": "Neurophos", "lastReviewed": "2026-08-31" }, { "id": "nvidia", "name": "NVIDIA", "lastReviewed": "2026-09-02" }, { "id": "nxp", "name": "NXP", "lastReviewed": "2026-10-15" }, { "id": "olix", "name": "OLIX", "lastReviewed": "2026-08-31" }, { "id": "onsemi", "name": "onsemi", "lastReviewed": "2026-10-15" }, { "id": "qualcomm", "name": "Qualcomm", "lastReviewed": "2026-09-28" }, { "id": "renesas", "name": "Renesas", "lastReviewed": "2026-10-15" }, { "id": "roche-sequencing-solutions", "name": "Roche Sequencing", "lastReviewed": "2026-08-30" }, { "id": "rohm", "name": "ROHM", "lastReviewed": "2026-08-30" }, { "id": "samsung", "name": "Samsung", "lastReviewed": "2026-08-31" }, { "id": "scientific-analog", "name": "Scientific Analog", "lastReviewed": "2026-10-25" }, { "id": "semtech", "name": "Semtech", "lastReviewed": "2026-08-31" }, { "id": "siemens-eda", "name": "Siemens EDA", "lastReviewed": "2026-09-25" }, { "id": "silicon-labs", "name": "Silicon Labs", "lastReviewed": "2026-08-31" }, { "id": "sitime", "name": "SiTime", "lastReviewed": "2026-10-05" }, { "id": "sk-hynix", "name": "SK hynix", "lastReviewed": "2026-10-25" }, { "id": "skyworks", "name": "Skyworks", "lastReviewed": "2026-10-09" }, { "id": "solidvue", "name": "SolidVue", "lastReviewed": "2026-10-09" }, { "id": "sony-ai", "name": "Sony AI", "lastReviewed": "2026-10-19" }, { "id": "sony-semiconductor-solutions", "name": "Sony Semiconductor", "lastReviewed": "2026-08-31" }, { "id": "stmicroelectronics", "name": "STMicroelectronics", "lastReviewed": "2026-10-06" }, { "id": "synopsys", "name": "Synopsys", "lastReviewed": "2026-10-05" }, { "id": "texas-instruments", "name": "Texas Instruments", "lastReviewed": "2026-10-15" }, { "id": "toppan", "name": "TOPPAN", "lastReviewed": "2026-08-30" }, { "id": "toshiba-electronic-devices-storage", "name": "Toshiba", "lastReviewed": "2026-08-30" }, { "id": "tylsemi", "name": "TYLsemi", "lastReviewed": "2026-10-25" }, { "id": "ubitium", "name": "Ubitium", "lastReviewed": "2026-09-09" }, { "id": "ulkasemi", "name": "Ulkasemi", "lastReviewed": "2026-08-31" } ], "people": [ { "id": "aadhar-sharma", "name": "Aadhar Sharma" }, { "id": "alexandra-kuester", "name": "Alexandra Küster" }, { "id": "augusto-mafra", "name": "Augusto Mafra" }, { "id": "awani-khodkumbhe", "name": "Awani Khodkumbhe" }, { "id": "bahaa-osman", "name": "Bahaa Osman" }, { "id": "carna-zivkovic", "name": "Carna Zivkovic" }, { "id": "carsten-wegener", "name": "Carsten Wegener" }, { "id": "charles-dancak", "name": "Charles Dančak" }, { "id": "chia-tung-ho", "name": "Chia-Tung Ho" }, { "id": "ching-san-wu", "name": "Ching San Wu" }, { "id": "chuck-mcclish", "name": "Chuck McClish" }, { "id": "evgeny-vlasov", "name": "Evgeny Vlasov" }, { "id": "felix-assmann", "name": "Felix Aßmann" }, { "id": "gabriel-rutsch", "name": "Gabriel Rutsch" }, { "id": "gautham-sathyan", "name": "Gautham Sathyan" }, { "id": "guha-lakshmanan", "name": "Guha Lakshmanan" }, { "id": "guillermo-conde", "name": "Guillermo Conde" }, { "id": "helen-song", "name": "Helen Song" }, { "id": "henry-chang", "name": "Henry Chang" }, { "id": "jaeha-kim", "name": "Jaeha Kim" }, { "id": "jakub-dudek", "name": "Jakub Dudek" }, { "id": "jeevan-ramaswamy", "name": "Jeevan Ramaswamy" }, { "id": "joachim-glas", "name": "Joachim Glas" }, { "id": "jun-yan", "name": "Jun Yan" }, { "id": "keiichi-kajino", "name": "Keiichi Kajino" }, { "id": "konstantinos-glaros", "name": "Konstantinos Glaros" }, { "id": "lorenzo-servadei", "name": "Lorenzo Servadei" }, { "id": "marcel-oosterhuis", "name": "Marcel Oosterhuis" }, { "id": "mariam-maurice", "name": "Mariam Maurice" }, { "id": "martin-barnasconi", "name": "Martin Barnasconi" }, { "id": "neel-natekar", "name": "Neel Natekar" }, { "id": "neha-chavan", "name": "Neha Chavan" }, { "id": "neyaz-khan", "name": "Neyaz Khan" }, { "id": "patrick-lynch", "name": "Patrick Lynch" }, { "id": "paul-graykowski", "name": "Paul Graykowski" }, { "id": "peter-grove", "name": "Peter Grove" }, { "id": "prabal-bhattacharya", "name": "Prabal K. Bhattacharya" }, { "id": "rakesh-kumar", "name": "Rakesh Kumar" }, { "id": "scott-little", "name": "Scott Little" }, { "id": "sebastian-simon", "name": "Sebastian Simon" }, { "id": "selcuk-talay", "name": "Selcuk Talay" }, { "id": "sidharth-kannan", "name": "Sidharth Kannan" }, { "id": "simul-barua", "name": "Simul Barua" }, { "id": "souradip-poddar", "name": "Souradip Poddar" }, { "id": "srinivasan-venkataramanan", "name": "Srinivasan Venkataramanan" }, { "id": "stefan-uhlich", "name": "Stefan Uhlich" }, { "id": "steven-holloway", "name": "Steven Holloway" }, { "id": "suhas-belgal", "name": "Suhas Belgal" }, { "id": "takaomi-nakabe", "name": "Takaomi Nakabe" }, { "id": "thilo-voertler", "name": "Thilo Vörtler" }, { "id": "tomokatsu-mizukusa", "name": "Tomokatsu Mizukusa" }, { "id": "toshi-kawashima", "name": "Toshi Kawashima" }, { "id": "venkateswaran-padmanabhan", "name": "Venkateswaran Padmanabhan" }, { "id": "vijay-kumar", "name": "Vijay Kumar" }, { "id": "xin-zhang", "name": "Xin Zhang" }, { "id": "zhipeng-ye", "name": "Zhipeng Ye" }, { "id": "tadokoro-haruko", "name": "田所 晴子" } ], "events": [ { "id": "qualcomm-2026-toronto-analog-modeling-internship", "when": { "start": "2026-11-07", "precision": "day" }, "kind": "organizational", "companies": [ "qualcomm" ], "people": [], "headline": "Observed Qualcomm Toronto internship offers possible SV modeling and AMS validation assignments", "fact": "As observed November 7, Qualcomm advertised a Toronto Analog Design internship for 12 or 16 months beginning in May or June 2027. Possible assignments include SystemVerilog analog behavioral models, AMS co-simulation to validate them, simulation-data peer review and testbench-performance metrics, with analog, digital, firmware and system teams. The application feeds multiple project-specific roles, so these are possible duties rather than completed work or a promise that every intern receives the same assignment. The Event uses the observation date because a reliable first-publication date is unconfirmed; 2027 is the planned placement year.", "sources": [ { "title": "Qualcomm employer LinkedIn: FY27 Analog Design Internship, Canada", "url": "https://ca.linkedin.com/jobs/view/fy27-intern-analog-design-internship-canada-12-or-16-months-at-qualcomm-4467871176", "checkedAt": "2026-11-07", "summary": "Employer-attributed full text identifies the Toronto Analog Design team, possible SV/AMS validation and review duties, candidate-pool model and May/June 2027 start. Only mutable relative posting age was available; this check is not evidence of a new November posting.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/qualcomm-2026-toronto-analog-modeling-internship/" }, { "id": "tylsemi-2026-10-ivr-rnm-verilog-a-verification-hiring", "when": { "start": "2026-10-25", "precision": "day" }, "kind": "organizational", "companies": [ "tylsemi" ], "people": [], "headline": "TYLsemi's retained IVR role links Verilog-A/RNM models, co-simulation and power-control checks", "fact": "An employer-attributed TYLsemi LinkedIn role observed October 25, 2026 describes high-current integrated-voltage-regulator verification. It assigns Verilog-A and SystemVerilog RNM models for power stages, integrated inductors, the power-delivery network and analog blocks; analog/digital co-simulation; and testbenches for load transients, loop stability, ripple, protection and startup/shutdown. Duties also include PVT/Monte Carlo regressions and simulation-to-lab correlation. The first publication date is unconfirmed, so this Event uses the observation date of the retained advertisement, not a claimed October hiring launch.", "sources": [ { "title": "TYLsemi employer LinkedIn: Senior Mixed-Signal Verification Engineer - Power Management ICs", "url": "https://www.linkedin.com/jobs/view/senior-mixed-signal-verification-engineer-power-management-ics-at-tylsemi-4446565851", "checkedAt": "2026-10-25", "summary": "Retained full employer description was checked October 25, 2026. It names high-current IVRs, Verilog-A/SystemVerilog RNM models, simulator combinations, control-loop checks and lab correlation. No reliable original datePosted was exposed; relative ages are not used.", "status": "available", "archiveUrl": null }, { "title": "TYLsemi employer LinkedIn: related retained IVR verification listing", "url": "https://www.linkedin.com/jobs/view/senior-mixed-signal-verification-engineer-power-management-ics-at-tylsemi-4447043899", "checkedAt": "2026-10-25", "summary": "Related retained copy repeats the IVR modeling and verification duties and is marked no longer accepting applications. Grouped with the same mandate; this does not establish a separate recruitment event or current vacancy.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/tylsemi-2026-10-ivr-rnm-verilog-a-verification-hiring/" }, { "id": "analog-devices-2026-10-milan-power-ams-training", "when": { "start": "2026-10-21", "precision": "day" }, "kind": "organizational", "companies": [ "analog-devices" ], "people": [], "headline": "ADI Milan internship describes power-IC modeling and metric-driven DMS/AMS verification training", "fact": "ADI posted AMS Design Verification Intern R267539 for its High-Performance Power Group in Milan, with a possible master’s thesis. The group designs display, lighting and cloud-power ICs. Advertised training covers verification planning, Verilog-AMS and SystemVerilog analog-block models, AMS simulations, state-machine checks, analog assertions and metric-driven SystemVerilog/UVM environments combining DMS and AMS at IP and top level. This records the current internship posting, not the launch of a new training program or completed student work.", "sources": [ { "title": "ADI Careers: AMS Design Verification Intern (R267539)", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/Italy-Milan-Assago/AMS-Design-Verification-Intern_R267539", "checkedAt": "2026-11-07", "summary": "Official public Workday startDate is October 21, 2026. The full description names the Milan High-Performance Power Group, application areas and proposed training; applications remained enabled at this check. It does not assign AI-assisted modeling.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2026-10-milan-power-ams-training/" }, { "id": "apple-2026-10-ams-ip-formal-verification-internship", "when": { "start": "2026-10-14", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple advertises an AMS IP formal-verification internship in London", "fact": "Apple posted London internship 200688723 for its AMS IP team. The project develops property sets for hardware-model functional coverage, formalizes SVA properties, executes formal proofs and studies model-accuracy versus proof-convergence tradeoffs. It also extends the framework to integrate properties at higher levels for system verification. The posting describes proposed intern work within an AMS IP organization; it does not report completed proofs or a deployed formal flow.", "sources": [ { "title": "Apple Careers: Formal Verification Framework for Hardware IPs Validation (200688723)", "url": "https://jobs.apple.com/en-us/details/200688723/formal-verification-framework-for-hardware-ips-validation", "checkedAt": "2026-10-25", "summary": "Official page hydration data gives October 14, 2026 and the London AMS IP team. Full duties specify SVA, model accuracy, proof convergence and higher-level property integration. No particular analog model language or completed result is disclosed.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-10-ams-ip-formal-verification-internship/" }, { "id": "skyworks-2026-10-agentic-analog-rf-design-coop", "when": { "start": "2026-10-14", "precision": "day" }, "kind": "organizational", "companies": [ "skyworks" ], "people": [], "headline": "Skyworks advertises circuit-simulator agents and RAG evaluation for analog/RF design", "fact": "Skyworks posted San Jose co-op 78610 within the Mobile Solutions Division Software Engineering group. It assigns LLM agents connected to circuit simulators such as Spectre/Virtuoso and ADS, RAG over design documents and PDKs, and agent-performance evaluation on LNAs, PAs, switches and bias circuits in Si/SOI processes. The project includes schematic and simulation automation alongside layout tasks. January-June 2027 is the advertised work term. This analog/RF circuit-design research mandate is distinct from the earlier mixed-signal verification-platform co-op; neither posting demonstrates completed deployment.", "sources": [ { "title": "Skyworks Careers: Analog and RF circuit design Winter/Spring Co-Op (78610)", "url": "https://careers.skyworksinc.com/job/Analog-and-RF-circuit-design-WinterSpring-Co-Op-%28Jan-June-%2727%29/78610-en_US/", "checkedAt": "2026-10-25", "summary": "Official posting displays October 14, 2026, requisition 78610, Mobile Solutions Division and the simulator-agent, RAG and circuit-task evaluation duties. The 2027 dates identify the work term.", "status": "available", "archiveUrl": null }, { "title": "Skyworks employer LinkedIn: analog/RF circuit-design co-op", "url": "https://www.linkedin.com/jobs/view/analog-and-rf-circuit-design-winter-spring-co-op-jan-june-27-at-skyworks-solutions-inc-4479579396", "checkedAt": "2026-10-25", "summary": "Full employer description and JobPosting datePosted October 14 confirm the official role. Search snippets giving October 6 are not used as the publication-date basis. Related seasonal hiring is not a separate Event.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/skyworks-2026-10-agentic-analog-rf-design-coop/" }, { "id": "microsoft-2026-10-quantum-ams-modeling-methodology-hiring", "when": { "start": "2026-10-12", "precision": "day" }, "kind": "organizational", "companies": [ "microsoft" ], "people": [], "headline": "Microsoft Quantum advertises system-wide AMS simulation and shared modeling methodology", "fact": "Microsoft posted a Senior Quantum Analog Mixed-Signal Verification Engineer role assigning the Quantum 1st Party Hardware ASIC team system-wide AMS models, simulation environments and test plans. It combines analog and digital blocks across multiple SoCs, supplies behavioral models to full-chip digital verification, and establishes standardized AMS verification/modeling methodology with peers. Qualifications include UVM/OVM, Spectre AMS or Synopsys XA, and modeling corners and process variability. AI-tool use is a general work requirement rather than a specified model-generation method. This records an advertised infrastructure mandate, not deployed quantum-SoC verification results.", "sources": [ { "title": "Microsoft employer LinkedIn: Senior Quantum Analog Mixed-Signal Verification Engineer", "url": "https://www.linkedin.com/jobs/view/senior-quantum-analog-mixed-signal-verification-engineer-at-microsoft-4414607082", "checkedAt": "2026-10-25", "summary": "Full employer-attributed posting and current JobPosting metadata give October 12, 2026. Duties explicitly cover shared AMS methodology, cross-SoC simulation and analog behavioral models for digital verification. No particular HDL or measured AI-generated modeling result is disclosed.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microsoft-2026-10-quantum-ams-modeling-methodology-hiring/" }, { "id": "atrisa-2026-10-analog-design-agent-evaluation-hiring", "when": { "start": "2026-10-10", "precision": "day" }, "kind": "organizational", "companies": [ "atrisa" ], "people": [], "headline": "Atrisa advertises founding analog-design work to build circuit tools and AI-agent evaluations", "fact": "Atrisa posted a Founding Analog Design Engineer role in Bengaluru on its Y Combinator recruiting page. The company describes building AI agents for analog circuit design. The role designs, simulates and verifies analog/mixed-signal blocks and works with software and AI engineers to turn circuit-design problems into tools and evaluations. It includes specification tradeoffs, schematic design, SPICE simulation, layout review and silicon validation. This is an advertised circuit-design and evaluation mandate, not evidence that agents autonomously complete specification-to-layout designs or have achieved silicon results.", "sources": [ { "title": "Atrisa employer listing: Founding Analog Design Engineer", "url": "https://www.ycombinator.com/companies/atrisa/jobs/bQRwY6B-founding-analog-design-engineer", "checkedAt": "2026-10-25", "summary": "Employer-authored YC posting and JobPosting datePosted identify October 10, 2026 at 10:47 UTC. The full role explicitly connects analog circuit work with software/AI tools and evaluations; no particular HDL model language or achieved agent performance is specified.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/atrisa-2026-10-analog-design-agent-evaluation-hiring/" }, { "id": "qualcomm-2026-10-rfchipagent-lna-design-preprint", "when": { "start": "2026-10-07", "precision": "day" }, "kind": "technical", "companies": [ "qualcomm" ], "people": [ "awani-khodkumbhe" ], "headline": "Qualcomm-affiliated authors publish RFChipAgent for LNA topology selection, schematic assembly and verification", "fact": "Awani Khodkumbhe and Qualcomm-affiliated coauthors publish RFChipAgent, a human-supervised LLM-agent flow for analog/RF design. It connects document retrieval, topology selection, schematic and testbench assembly, simulation-guided optimization, and operating-point and stability checks. The reported case is a GF22FDSOI 60 GHz wideband LNA. The paper is a preprint submitted for possible publication, not a product release, measured-silicon result or evidence of company-wide adoption. Khodkumbhe also lists UC Berkeley affiliation.", "sources": [ { "title": "RFChipAgent: arXiv submission record", "url": "https://arxiv.org/abs/2610.10858", "checkedAt": "2026-10-19", "summary": "The record dates v1 to October 7, 2026 and lists the authors, LNA scope and preprint status.", "status": "available", "archiveUrl": null }, { "title": "RFChipAgent v1: author affiliations and design flow", "url": "https://arxiv.org/html/2610.10858v1", "checkedAt": "2026-10-19", "summary": "The HTML manuscript identifies Qualcomm Technologies affiliations and Khodkumbhe's UC Berkeley affiliation; topology and schematic generation qualify beyond fixed-topology sizing.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/qualcomm-2026-10-rfchipagent-lna-design-preprint/" }, { "id": "hrl-2026-10-cryo-cmos-rnm-uvm-ams-verification-hiring", "when": { "start": "2026-10-06", "precision": "day" }, "kind": "organizational", "companies": [ "ibm" ], "people": [], "headline": "HRL advertises cryogenic-CMOS model correlation and UVM-AMS verification leadership", "fact": "HRL Laboratories' Qubit Systems Laboratory posted an AMS verification role for quantum-control cryogenic CMOS. It assigns Verilog-A/AMS, wreal and SV-RNM models aligned with transistor-level implementations; UVM-AMS environments, SVA/PSL and coverage; regression infrastructure; and block-to-top-level integration for ADCs, DACs, PLLs, LDOs, SerDes and power-management blocks. Model correlation spans PVT/corner simulation and later measurements. The employer identifies HRL as an IBM company. These are advertised responsibilities, not demonstrated model accuracy.", "sources": [ { "title": "HRL Careers: Analog/Mixed Signal Verification Engineer, Qubit Systems Laboratory", "url": "https://jobs.lever.co/dodmg/0dd665ca-8391-4aa2-80ec-f6da87bf9a76", "checkedAt": "2026-10-25", "summary": "Official employer page and JobPosting datePosted identify October 6, 2026. Full text names cryogenic CMOS, RNM/Verilog-A/AMS, UVM-AMS, transistor-model alignment, assertions and regression/CI ownership; the page identifies HRL as an IBM company.", "status": "available", "archiveUrl": null }, { "title": "HRL: IBM completes acquisition of HRL Laboratories", "url": "https://www.hrl.com/news/2026/07/23/ibm-to-acquire-hrl-laboratories-to-power-the-future-of-quantum", "checkedAt": "2026-10-25", "summary": "The current official page contains IBM's completion announcement above the earlier July agreement announcement. It supports canonical IBM grouping; the URL's July date is not treated as the acquisition-completion date or a verification milestone.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/hrl-2026-10-cryo-cmos-rnm-uvm-ams-verification-hiring/" }, { "id": "bosch-2026-10-dms-model-equivalence-verification-hiring", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "bosch" ], "people": [], "headline": "Bosch lists a DMS verification role covering model/schematic equivalence and model accuracy checks", "fact": "On October 5, Bosch Service Solutions listed a Valencia DMS Verification Engineer role for mixed-signal SoCs. The position defines the split between DMS and digital verification and model/schematic equivalence, validates behavioral-model accuracy and performance against circuit simulations and measurements, and debugs RTL, gate and schematic behavior. It also assigns verification planning, regressions, functional/code coverage and UVM infrastructure improvements. The posting is a hiring mandate and does not establish measured verification outcomes.", "sources": [ { "title": "Bosch Group: DMS Verification Engineer — official SmartRecruiters posting", "url": "https://jobs.smartrecruiters.com/BoschGroup/744000146778857", "checkedAt": "2026-10-05", "summary": "Official Bosch Service Solutions posting checked October 5, 2026; first publication is not established. It describes DMS/DV partitioning, model/schematic equivalence and model accuracy/performance checks against simulations and measurements.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-2026-10-dms-model-equivalence-verification-hiring/" }, { "id": "imms-2026-10-python-mixed-signal-model-generator-student-project", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "imms" ], "people": [], "headline": "IMMS lists a student project to extend a Python framework for automatic mixed-signal model generation", "fact": "On October 5, IMMS listed an Erfurt student project to extend an existing Python framework for generating behavioral circuit models. The project adds signal-name classification, analog/digital structure detection and recognition of circuit classes, then develops suitable model generators and integrates and validates them. Verilog-AMS is named as an example modeling language. The listing accepts mandatory internships and student research or thesis work, with an application deadline of December 31, 2026. It does not describe the framework as AI-based.", "sources": [ { "title": "IMMS: Student project extending a Python mixed-signal model generator (IMMS_STUD_ME_0726)", "url": "https://jobs.imms.de/jobposting/87ea97ce0a4b30cf0e7f5ee639bed88a762387580", "checkedAt": "2026-10-05", "summary": "Official student posting checked October 5, 2026; first publication is not established. It describes an existing Python framework and proposed classification, circuit recognition, model generation and validation extensions, with a December 31 deadline.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/imms-2026-10-python-mixed-signal-model-generator-student-project/" }, { "id": "infineon-2026-10-ai-sv-rnm-automotive-verification-hiring", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "infineon" ], "people": [], "headline": "Infineon seeks a Senior Staff engineer for AI-based SV-RNM and automotive AMS verification", "fact": "Infineon's Bengaluru Senior Staff Engineer Analog Mixed-Signal Verification posting assigns AI-based SystemVerilog real-number behavioral models with speed/accuracy tradeoffs for pre-silicon verification. The role leads automotive subsystem and analog-on-top full-chip verification, develops AMS plans, SPICE-netlist integration, checkers, assertions and coverage, and models bandgaps, LDOs and buck-boost regulators. This is an advertised development and methodology-leadership mandate; the posting does not disclose an AI algorithm, model-generation results or production adoption.", "sources": [ { "title": "Infineon Careers: Senior Staff Engineer Analog Mixed-Signal Verification", "url": "https://jobs.infineon.com/careers/job/563808971219634", "checkedAt": "2026-10-25", "summary": "Official JobPosting datePosted is October 5, 2026. Assigned work explicitly includes AI-based SV-RNM, accuracy/runtime tradeoffs and automotive subsystem/full-chip verification; this is separate from the earlier graduate and internship advertisements.", "status": "available", "archiveUrl": null }, { "title": "Infineon employer LinkedIn: Senior Staff AMS verification", "url": "https://in.linkedin.com/jobs/view/senior-staff-engineer-analog-mixed-signal-verification-at-infineon-technologies-4426837442", "checkedAt": "2026-10-25", "summary": "Employer-attributed description independently repeats the AI-based SV-RNM assignment. Current LinkedIn metadata dates this copy October 7; that later platform date is not substituted for the official October 5 date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-10-ai-sv-rnm-automotive-verification-hiring/" }, { "id": "mediatek-2026-10-rf-modeling-design-automation-internships", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "mediatek" ], "people": [], "headline": "MediaTek lists 2027 internships for RF wreal models and analog/RF design automation", "fact": "On October 5, MediaTek listed Singapore internships for 2027 covering mixed-signal verification and design automation. The verification role assigns analog/RF macro models for system co-simulation, Verilog/wreal models of RF calibration engines and analog leaf cells, and RF-digital testbench templates. A preserved 2026-internship listing describes the same RF modeling and testbench duties, so the 2027 listing is grouped with that recruiting history rather than treated as a new modeling method. The automation role covers Python, EDA tools, data analysis and exploration of AI for simulation, layout, verification and design workflows. The listings establish advertised student work, not a newly deployed modeling or AI platform.", "sources": [ { "title": "MediaTek Careers: 2027 mixed-signal verification internship (MSL120230327006)", "url": "https://careers.mediatek.com/en/jobs/MSL120230327006", "checkedAt": "2026-10-05", "summary": "Official indexed 2027 listing checked October 5, 2026; first publication is not established and this requisition URL has been reused. It explicitly assigns RF calibration/leaf-cell Verilog/wreal models and co-simulation testbench work.", "status": "available", "archiveUrl": null }, { "title": "MediaTek Careers: 2027 design-automation internship (MSL120260904001)", "url": "https://yourcareers.mediatek.com/en/jobs/MSL120260904001?categorys=9009&locations=0000009291", "checkedAt": "2026-10-05", "summary": "Official indexed listing checked October 5, 2026; first publication is not established. It describes analog/RF/mixed-signal design automation, Python/EDA/data tools and exploratory AI applications.", "status": "available", "archiveUrl": null }, { "title": "MediaTek LinkedIn job listing: [2026 Internship] Mixed Signal Verification Intern", "url": "https://sg.linkedin.com/jobs/view/2026-internship-mixed-signal-verification-intern-at-mediatek-4301977687", "checkedAt": "2026-10-06", "summary": "Preserved closed 2026 internship listing repeats RF macro/co-simulation, calibration and leaf-cell Verilog/wreal model, and RF-digital testbench duties. Its exact first posting date is unconfirmed; no earlier day is inferred from the work-term label or relative age.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/mediatek-2026-10-rf-modeling-design-automation-internships/" }, { "id": "melexis-2026-10-claude-ams-verification-internship", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "melexis" ], "people": [], "headline": "Melexis posts a Claude-based AMS verification internship for automotive sensor ICs", "fact": "Melexis posted Bevaix internship/master's-thesis project 3932 for automotive sensor IC mixed-signal design verification and system integration. The six-month 2027 project assigns Claude Code workflows, test-case development, and automated classification and root-cause analysis of simulation/verification failures. SystemVerilog/Verilog is essential; UVM is beneficial. Optional work compares Chipstack with Claude. Deployment into real projects and efficiency improvements are expected project results, not demonstrated outcomes. The retained official timestamp is October 5 at 20:00 UTC; 2027 identifies the work cohort.", "sources": [ { "title": "Melexis Careers: AI Infrastructure Development for Automotive Sensor IC Design Verification (3932)", "url": "https://www.melexis.com/en/careers/3932/internship-ai-infrastructure-development-for-automotive-sensor-ic-design-verification", "checkedAt": "2026-10-25", "status": "unavailable", "summary": "Previously verified official JobPosting metadata gives October 5, 2026 at 20:00 UTC and identifier 3932; the UTC date corrects the prior October 6 JST record. The official page returns HTTP 403 on October 25, so this is an availability check, not a fresh full-text review. Retained duties concern Claude-based mixed-signal test development and failure triage.", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/melexis-2026-10-claude-ams-verification-internship/" }, { "id": "micron-2026-10-ams-verification-agent-workflows-hiring", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "micron" ], "people": [], "headline": "Micron advertises full-chip AMS verification with AI-agent development and output evaluation", "fact": "Micron advertised October 5 LinkedIn role JR113919 for block-to-full-chip AMS verification, power-loss/brownout checks and agents for requirements-to-test extraction, triage, failure clustering, waveform guidance and coverage gaps. Related official JR114263, dated October 8, adds behavioral/schematic models accurate enough for each verification objective. Both require validated engineering data, human review and evaluation of AI-output usefulness and limitations. Preferred experience measures reduced manual effort, faster debug, traceability or verification completeness; these are evaluation criteria, not reported improvements. The distinct requisitions are grouped as an advertised development mandate.", "sources": [ { "title": "Micron: SR, Engineer - AMS Verification, JR113919 — employer LinkedIn posting", "url": "https://in.linkedin.com/jobs/view/sr-engineer-ams-verification-at-micron-technology-4474274440", "checkedAt": "2026-10-25", "summary": "Employer-attributed full job description and JobPosting metadata identify JR113919 and October 5, 2026 as the LinkedIn posting date. The official Careers first-publication date is not established. This is a distinct requisition from the March JR93301 AI-assisted-coding role.", "status": "available", "archiveUrl": null }, { "title": "Micron Careers: SR, Engineer – AMS Verification (JR114263)", "url": "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/SR--Engineer---AMS-Verification_JR114263", "checkedAt": "2026-10-25", "summary": "Official Workday startDate remains October 8, 2026. Full duties specify objective-appropriate model accuracy and evaluated agent prototypes. Benefit measurement is preferred experience, not demonstrated gains; final verification decisions remain grounded in simulation, specifications and engineering judgment.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/micron-2026-10-ams-verification-agent-workflows-hiring/" }, { "id": "sitime-2026-10-pll-verification-coop", "when": { "start": "2026-10-05", "precision": "day" }, "kind": "organizational", "companies": [ "sitime" ], "people": [], "headline": "SiTime lists a January 2027 Co-op for mixed-signal PLL verification", "fact": "On October 5, SiTime listed an Ottawa ASIC Digital Verification Co-op for sixteen weeks beginning in January 2027. The student role contributes to mixed-signal PLL IC development by learning the verification environment and testbench and writing test cases for ongoing projects. Verilog, SystemVerilog, UVM, Python and Tcl knowledge are welcomed. The posting does not explicitly assign RNM model development to the Co-op.", "sources": [ { "title": "SiTime: ASIC digital-verification Co-op — employer LinkedIn posting", "url": "https://ca.linkedin.com/jobs/view/co-op-asic-digital-verification-engineer-at-sitime-4473987683", "checkedAt": "2026-10-05", "summary": "Employer posting checked October 5, 2026; first publication is not established. It explicitly identifies mixed-signal PLL ICs and a sixteen-week Co-op starting January 2027, with testbench/test-case work and welcomed SystemVerilog/UVM skills.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sitime-2026-10-pll-verification-coop/" }, { "id": "marvell-2026-10-mixed-signal-verification-validation-internships", "when": { "start": "2026-09-30", "precision": "day" }, "kind": "organizational", "companies": [ "marvell" ], "people": [], "headline": "Marvell posts a Singapore AMS verification internship for amplifier verification", "fact": "Marvell posted Singapore AMS Verification Intern – Master’s Degree (2604802) on September 30, 2026. The role assigns verification planning, testbench development and simulation checks for broadband amplifier circuits. Its profile requests control/feedback and automatic-gain-control knowledge; Verilog and Verilog-A are desirable programming experience, rather than explicit commitments to RNM/UVM or model generation. This Event records AMS verification recruitment, not deployed practice; unrelated lab-only validation internships are not included.", "sources": [ { "title": "Marvell Careers: Singapore AMS Verification Intern (2604802)", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Singapore/AMS-Verification-Intern---Master-s-Degree_2604802", "checkedAt": "2026-10-06", "summary": "Official Workday startDate is September 30, 2026. The description concerns amplifier AMS verification and lists Verilog/Verilog-A as desired experience; it does not establish an implemented RNM/UVM flow.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/marvell-2026-10-mixed-signal-verification-validation-internships/" }, { "id": "micron-2026-09-nand-ai-circuit-review-hiring", "when": { "start": "2026-09-30", "precision": "day" }, "kind": "organizational", "companies": [ "micron" ], "people": [], "headline": "Micron NAND analog-design role assigns AI agents to circuit review and specification checks", "fact": "Micron posted Hyderabad Staff Engineer, Analog Design role JR113578 for NAND Flash circuits including charge pumps, regulators, ADCs/DACs, references and sensor interfaces. It assigns development and evaluation of AI agents for specification-to-check extraction, schematic or connectivity review, and verification debug. Reusable workflows connect engineering data, scripts, simulation outputs and design checks, with validation and human review before decisions. These pre-silicon review tasks extend beyond the separate layout-automation and simulation-orchestration duties; the posting does not establish AI-generated circuit topology or achieved deployment benefits.", "sources": [ { "title": "Micron Careers: Staff Engineer, Analog Design (JR113578)", "url": "https://micron.wd1.myworkdayjobs.com/External/job/Hyderabad---Phoenix-Aquila-India/Staff-Engineer--Analog-Design_JR113578-1", "checkedAt": "2026-10-15", "summary": "Official Workday startDate is September 30, 2026. The NAND analog role explicitly assigns agent prototypes for specification-to-check extraction, schematic/connectivity review and debug, with evaluation criteria and human validation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/micron-2026-09-nand-ai-circuit-review-hiring/" }, { "id": "onsemi-2026-09-agentic-analog-design-leadership-hiring", "when": { "start": "2026-09-30", "precision": "day" }, "kind": "organizational", "companies": [ "onsemi" ], "people": [], "headline": "onsemi seeks leadership for analog design agents, architecture exploration and agent qualification", "fact": "onsemi advertised Senior Director, AI NPD Platforms & Engineering Intelligence role 2506790 to define and govern agentic-AI semiconductor development. Duties include analog and verification agents, AI-enabled circuit design and architecture exploration, and an approved agent library with qualification, validation, versioning, release and human-review processes. The role spans additional disciplines, but circuit/architecture and verification work provide the qualifying scope. It is a development and governance hiring mandate, not evidence that the proposed platform or productivity gains have been delivered.", "sources": [ { "title": "onsemi: Senior Director, AI NPD Platforms & Engineering Intelligence — employer LinkedIn posting", "url": "https://www.linkedin.com/jobs/view/senior-director-ai-npd-platforms-engineering-intelligence-at-onsemi-4471777525", "checkedAt": "2026-10-15", "summary": "Employer JobPosting datePosted is September 29, 2026 at 21:55:17 UTC, or September 30 JST, the Event’s date basis. Full duties describe analog/verification agents, circuit architecture exploration and agent governance. The original careers first-publication date is unverified.", "status": "available", "archiveUrl": null }, { "title": "onsemi Careers: AI NPD Platforms & Engineering Intelligence (2506790)", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506790", "checkedAt": "2026-10-15", "summary": "Official application requisition associated with the employer-attributed posting; the LinkedIn channel timestamp, rather than an inferred requisition date, supports chronology.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/onsemi-2026-09-agentic-analog-design-leadership-hiring/" }, { "id": "keysight-2026-09-ai-rfic-schematic-internship", "when": { "start": "2026-09-29", "precision": "day" }, "kind": "organizational", "companies": [ "keysight" ], "people": [], "headline": "Keysight EDA internship explores AI schematic generation for RFIC and analog design", "fact": "Keysight advertised EDA AI/ML Software Intern role 54582 in Calabasas, with retained listings dated September 29. The MS/PhD internship explores AI applications in RFIC/analog schematic generation alongside layout automation, device modeling and design optimization. Responsibilities include Python ML prototypes, training/evaluation pipelines and integration into desktop software. Schematic-generation exploration is the qualifying design task; the advertisement does not establish topology invention, autonomous circuit synthesis or signoff-quality generated designs.", "sources": [ { "title": "Keysight: EDA AI/ML Software Intern — employer LinkedIn posting", "url": "https://www.linkedin.com/jobs/view/eda-ai-ml-software-intern-at-keysight-technologies-4471786772", "checkedAt": "2026-10-15", "summary": "Employer-attributed full duties explicitly include RFIC/analog schematic generation and AI/ML prototype evaluation. The retained application link identifies 54582; direct careers access returned an access error.", "status": "available", "archiveUrl": null }, { "title": "Simplify: retained Keysight EDA AI/ML internship", "url": "https://simplify.jobs/p/f4ec9754-f694-4e49-89d1-e4e407d7d2ff/EDA-AIML-Software-Intern", "checkedAt": "2026-10-15", "summary": "Retained full listing displays September 29, 2026. This secondary date supports the Event chronology; the original official posting timestamp remains unverified.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/keysight-2026-09-ai-rfic-schematic-internship/" }, { "id": "mediatek-2026-09-synopsys-agentic-ams-design-collaboration", "when": { "start": "2026-09-28", "precision": "day" }, "kind": "organizational", "companies": [ "mediatek", "synopsys" ], "people": [ "ching-san-wu" ], "headline": "MediaTek VP Ching San Wu describes continuing collaboration on Synopsys Agentic AI AMS Platform", "fact": "In a Synopsys announcement, MediaTek vice president Ching San Wu describes continuing collaboration on the Agentic AI AMS Platform for creating, optimizing and implementing analog/mixed-signal designs. He distinguishes this work from an earlier deployment of SmartFloorplanning. The release schedules broader AgentEngineer and Autopilot availability for the end of 2026. This records a named customer-side statement about collaboration, not completed deployment of the announced AMS platform or measured company-wide design productivity.", "sources": [ { "title": "Synopsys: long-horizon agents and Autopilot Platform", "url": "https://news.synopsys.com/2026-09-28-Synopsys-Powers-Autonomous-Engineering-with-a-Broad-Portfolio-of-Long-Horizon-Agents-and-Autopilot-Platform", "checkedAt": "2026-10-19", "summary": "September 28, 2026 release quotes MediaTek VP Ching San Wu on continued Agentic AI AMS Platform collaboration; the same release says portfolio availability is planned for the end of 2026.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/mediatek-2026-09-synopsys-agentic-ams-design-collaboration/" }, { "id": "cadence-2026-09-rnm-schematic-correlation-verification-hiring", "when": { "start": "2026-09-25", "precision": "day" }, "kind": "organizational", "companies": [ "cadence" ], "people": [], "headline": "Cadence advertises SystemVerilog RNM model qualification against schematics and analog assertions", "fact": "Cadence posted Mixed-Signal Systems and Verification Engineer R55855. The assigned work develops accurate, simulation-efficient SystemVerilog analog/RF behavioral models, verifies them against analog schematics, integrates them with RTL, and checks analog functionality against specifications using testbenches, scenarios and assertions. Qualifications name RNM, UDN/UDT/UDR, wreal, Verilog-AMS and analog assertion-based verification. Modeling and verification results are documented for formal review. This records an engineering hiring mandate rather than a product release or a reported customer deployment.", "sources": [ { "title": "Cadence Careers: Mixed-Signal Systems and Verification Engineer (R55855)", "url": "https://cadence.wd1.myworkdayjobs.com/en-US/External_Careers/job/Mixed--Signal-Systems-and-Verification-Engineer_R55855", "checkedAt": "2026-10-25", "summary": "Official Workday startDate is September 25, 2026. Full duties explicitly distinguish model development, schematic-correlation checks, RTL integration, specification checks and formal review.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2026-09-rnm-schematic-correlation-verification-hiring/" }, { "id": "texas-instruments-2026-09-battery-charging-ams-verification-hiring", "when": { "start": "2026-09-25", "precision": "day" }, "kind": "organizational", "companies": [ "texas-instruments" ], "people": [], "headline": "Texas Instruments battery-charging role calls for RNM models, analog checkers and mixed-signal regressions", "fact": "A Texas Instruments Battery Charging Products job posting describes AMS verification of battery-management ICs. Its responsibilities include Verilog-A/AMS and wreal RNM behavioral models for top-level simulation, testbenches combining schematics, models and RTL, analog checks during simulation and after processing, RTL and gate-level regressions, and functional coverage through tape-out. UVM, scripting and interest in AI-based verification automation are preferred qualifications. A preserved copy identifies Santa Clara requisition 25018210 and a September 25, 2026 posting timestamp.", "sources": [ { "title": "Texas Instruments: AMS design verification, Battery Charging Products (25018210)", "url": "https://careers.ti.com/en/sites/CX/job/25018210", "checkedAt": "2026-10-05", "summary": "Official application URL for requisition 25018210. The linked recovery copy preserves the employer description and September 25, 2026 posting timestamp.", "status": "available", "archiveUrl": null }, { "title": "Texas Instruments Battery Charging Products posting — SimplyHired recovery copy", "url": "https://www.simplyhired.com/job/y3O7BMEKUu527dEgVYJoPWSQOshHcCdBg7_pqwwrp316ixLp2vuLmA", "checkedAt": "2026-10-05", "summary": "Secondary copy preserves the employer description, job ID 25018210 and September 25, 2026 timestamp. It names RNM/wreal, analog checks, schematic/model/RTL testbenches, coverage and regressions; AI automation is a preferred interest, not a demonstrated deployment.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2026-09-battery-charging-ams-verification-hiring/" }, { "id": "nxp-2026-10-ai-model-migration-testbench-internship", "when": { "start": "2026-09-23", "precision": "day" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP lists an AI-agent internship for migrating behavioral models and generating validation testbenches", "fact": "NXP posted Toulouse internship R-10066989 on September 23 for AI-agent behavioral-model migration and mixed-signal stimuli/testbench generation, using Verilog/SystemVerilog and Verilog-AMS. Evaluation covers code quality, test-scenario coverage, automation rate, time savings and robustness, with regression checks and documented limitations. October 5 role R-10067009 covers AI-generated HDL AMS models and an oscillator/ADC/supply Golden Library. Related October 6 Design Enablement role R-10067212 assigns Python agents, LLM/RAG and surrogate-model generation, verification and qualification; its model language is unspecified. These grouped research advertisements propose evaluation work rather than demonstrate successful deployment.", "sources": [ { "title": "NXP Careers: Stage Ingénieur : Génération semi-automatique de modèles, stimuli et testbenches par agents IA (F/H) (R-10066989)", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Toulouse/Stage-Ingnieur---Gnration-semi-automatique-de-modles--stimuli-et-testbenches-par-agents-IA--F-H-_R-10066989", "checkedAt": "2026-10-25", "summary": "Official Workday startDate remains September 23, 2026. Full proposed evaluation includes automation rate, code quality, scenario coverage, time savings, robustness, regression detection and limitations. These are project metrics to establish, not achieved gains.", "status": "available", "archiveUrl": null }, { "title": "NXP Careers: AMS model generation and maintenance internship (R-10067009)", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Toulouse/Stage-Ingnieur---Automatisation-de-la-gnration-et-de-la-maintenance-de-modles-AMS--l-aide-de-l-IA--F-H-_R-10067009", "checkedAt": "2026-10-25", "summary": "Official Workday startDate is October 5, 2026. The related role describes HDL AMS model generation/maintenance and an oscillator/ADC/supply Golden Library; this later posting does not change the first role’s September 23 date.", "status": "available", "archiveUrl": null }, { "title": "NXP Careers: AI-driven behavioral-model generation and qualification (R-10067212)", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Toulouse/Stage-ingnieur---Gnration-et-qualification-de-modles-comportementaux-pilotes-par-l-IA--F-H-_R-10067212", "checkedAt": "2026-10-25", "summary": "Official Workday startDate is October 6, 2026. Full Design Enablement duties cover Python AI agents, LLM/RAG and prototype evaluation for surrogate behavioral-model generation/verification/qualification. Analog electronics is required; no particular HDL or circuit block is specified.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-10-ai-model-migration-testbench-internship/" }, { "id": "nxp-2026-10-ai-vip-assertion-generation-internship", "when": { "start": "2026-09-23", "precision": "day" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP lists an internship to generate mixed-signal VIP and assertions from specifications using AI agents", "fact": "On September 23, NXP listed a Toulouse internship to prototype and evaluate AI-assisted verification-component generation for digitally controlled mixed-signal IP, particularly DC/DC converters. The project analyzes specifications for interfaces, control sequences and faults, generates reusable SystemVerilog/UVM components and coverage, and proposes assertions for protocols, timing, forbidden states and fault responses. Generated components are to be integrated and tested on representative examples, with robustness and limitations evaluated.", "sources": [ { "title": "NXP Careers: Stage Ingénieur : Génération de VIP et d’assertions pour IP mixtes par agents IA (F/H) (R-10066990)", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Toulouse/Stage-Ingnieur---Gnration-de-VIP-et-d-assertions-pour-IP-mixtes-par-agents-IA--F-H-_R-10066990", "checkedAt": "2026-10-06", "summary": "Official Workday jobPostingInfo.startDate is 2026-09-23. The source describes an advertised research internship, not a deployed methodology.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-10-ai-vip-assertion-generation-internship/" }, { "id": "apple-2026-09-agentic-ams-design-cad-hiring", "when": { "start": "2026-09-22", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple advertises agent governance and AI evaluation for AMS design and CAD workflows", "fact": "Apple posted Analog Mixed-Signal Design Software Engineer role 200684916 on September 22, assigning agentic-AI orchestration for analog design data and a registry for agent versioning, rollback and audits, with human approval of agent changes. Related September 30 CAD role 200686566 assigns agent tuning, evaluation data, quality metrics and EDA integration across custom/analog design and other chip-design flows. These are advertised design-platform responsibilities, not evidence of autonomous analog architecture or behavioral-model generation; the postings do not establish a shared team.", "sources": [ { "title": "Apple Careers: Analog Mixed-Signal Design Software Engineer (200684916)", "url": "https://jobs.apple.com/en-us/details/200684916-0836/analog-mixed-signal-design-software-engineer", "checkedAt": "2026-10-15", "summary": "Official indexed description displays September 22, 2026 and assigns agentic orchestration, design-data infrastructure, agent versioning/rollback/audits and human review in AMS design workflows.", "status": "available", "archiveUrl": null }, { "title": "Apple Careers: AI Methodology Design/CAD Engineer (200686566)", "url": "https://jobs.apple.com/en-us/details/200686566-0836/ai-methodology-design-cad-engineer", "checkedAt": "2026-10-15", "status": "unavailable", "summary": "Official role and search metadata display September 30, 2026. The previously verified description assigns agent evaluation/tuning and EDA integration across analog and other flows. Direct detail retrieval now returns an unavailable shell/error; related later hiring is grouped without changing the September 22 date.", "archiveUrl": null }, { "title": "AnitaB.org: retained Apple CAD role 200686566", "url": "https://jobs.anitab.org/companies/apple/jobs/96225713-ai-methodology-design-cad-engineer", "checkedAt": "2026-10-15", "summary": "Retains Apple’s September 30 summary date and full agent-evaluation, tuning, custom/analog design and verification scope. Its own October 8 listing date is not treated as Apple’s first posting date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-09-agentic-ams-design-cad-hiring/" }, { "id": "nxp-2026-10-nfc-low-power-wreal-formal-internship", "when": { "start": "2026-09-22", "precision": "day" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP lists a 2027 NFC power-management internship combining wreal, SVA, formal proof and AI exploration", "fact": "On September 22, NXP listed a six-month internship starting in the first quarter of 2027 within its Sophia Antipolis Secure Transactions and Identification verification team. The project concerns NFC SoC power management, including power gating, reset, clocking and wreal analog representations. It assigns SystemVerilog test scenarios, SVA, coverage analysis and Jasper formal property verification, alongside investigation of AI/ML approaches for analog and mixed-signal verification. The AI work is exploratory.", "sources": [ { "title": "NXP Careers: Stage Ingénieur : Techniques de vérification basse consommation utilisant l'UVM, les preuves formelles et les capacités de l'IA (H/F) (R-10064619)", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Sophia-Antipolis-Valbonne/Stage-Ingnieur---Techniques-de-vrification-basse-consommation-utilisant-l-UVM--les-preuves-formelles-et-les-capacits-de-l-IA--H-F-_R-10064619", "checkedAt": "2026-10-06", "summary": "Official Workday jobPostingInfo.startDate is 2026-09-22. The source describes an advertised research internship, not a deployed methodology.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-10-nfc-low-power-wreal-formal-internship/" }, { "id": "allegro-microsystems-2026-09-power-ic-mixed-signal-verification-hiring", "when": { "start": "2026-09-21", "precision": "day" }, "kind": "organizational", "companies": [ "allegro-microsystems" ], "people": [], "headline": "Allegro lists power-IC verification roles covering startup checks, RNM models and reusable UVM methodology", "fact": "An employer-supplied Allegro MicroSystems recruiting job posting dated September 21 describes top-level AMS testbenches, Verilog-AMS/RNM/wreal models, and checks of power transitions, brownouts, POR, POK and UVLO over voltage and temperature corners. A related Richardson team-lead posting checked on October 5 assigns Power IC verification strategy, reusable SystemVerilog/UVM infrastructure, behavioral-model development, requirements-to-test traceability, safety checks and exploration of AI automation. Both are public hiring mandates.", "sources": [ { "title": "Allegro MicroSystems: Mixed Signal Design Verification Engineer — ASU recruitment listing", "url": "https://career.eoss.asu.edu/jobs/allegro-microsystems-llc-mixed-signal-design-verification-engineer/", "checkedAt": "2026-10-05", "summary": "Employer-supplied description on the university career board; recruitment began September 21, 2026. This is the board listing date, not a claim about the earliest employer publication. It details AMS/RNM models and startup, brownout and reset checks.", "status": "available", "archiveUrl": null }, { "title": "Allegro Careers: Principal mixed-signal verification team lead (R6656)", "url": "https://allegromicro.wd5.myworkdayjobs.com/en-US/AllegroCareers/job/Principal-Mixed-Signal-Design-Verification--Team-Lead_R6656", "checkedAt": "2026-10-05", "summary": "Official Richardson Power IC leadership listing checked October 5, 2026; its first publication date is not established. It covers reusable UVM, behavioral models, requirements traceability, safety assertions and exploration of AI automation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/allegro-microsystems-2026-09-power-ic-mixed-signal-verification-hiring/" }, { "id": "apple-2026-09-rnm-soc-model-accuracy-verification-hiring", "when": { "start": "2026-09-14", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts an RNM SoC modeling role that ties model accuracy to verification objectives", "fact": "Apple posted a Digital/Mixed Signal Modeling/Verification Engineer role for analog and RF blocks within a large SoC. The description assigns SystemVerilog RNM models with built-in checks, selecting the necessary modeling accuracy for each verification objective, assertions that define analog/digital specification checks and digital verification pass criteria, AMS environment setup with analog designers, and debugging digital-on-top chip testbenches. The scope includes power regulators, bandgaps, data converters, RF blocks and PLLs.", "sources": [ { "title": "Apple: Digital/Mixed Signal Modeling/Verification Engineer (200683595-3956)", "url": "https://jobs.apple.com/hu-hu/details/200683595-3956/digital-mixed-signal-modeling-verification-engineer", "checkedAt": "2026-10-05", "summary": "Official Apple listing dated September 14, 2026. Responsibilities connect RNM accuracy to verification objectives and include built-in model checks, assertions, AMS setup and chip-level debug.", "status": "available", "archiveUrl": null }, { "title": "Apple: September mixed-signal verification recruitment listings", "url": "https://jobs.apple.com/ja-jp/search?location=united-states-USA&team=%25D9%2587%25D9%2586%25D8%25AF%25D8%25B3%25D8%25A9-%25D8%25A7%25D9%2584%25D8%25B3%25D9%258A%25D9%2584%25D9%258A%25D9%2583%25D9%2588%25D9%2586-HRDWR-SILT", "checkedAt": "2026-10-05", "summary": "Apple search results also list related Sunnyvale and Austin roles, 200686375, dated September 29, 2026. These related listings are grouped with the September RNM modeling mandate rather than counted as separate regional Events.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-09-rnm-soc-model-accuracy-verification-hiring/" }, { "id": "cirrus-logic-2026-09-ams-uvm-model-reuse-hiring", "when": { "start": "2026-09-14", "precision": "day" }, "kind": "organizational", "companies": [ "cirrus-logic" ], "people": [], "headline": "Cirrus Logic role links SV-RNM models to analog design, UVM verification, HW/SW validation, and AMS-UVM reuse", "fact": "As observed September 14, Cirrus Logic listed an Analog Mixed Signal Modeling & Verification Engineer role for Austin, Chandler and Greensboro. It assigns equivalent models reused across analog design, UVM verification and HW/SW validation; SV-RNM, SV-UDT and Verilog-AMS; DMS/AMS plans and platforms; regression debug; and verification-component reuse in AMS-UVM. The original UL-01 page is now unavailable. Related current UL-02 role, observed October 25, repeats those duties and adds architectural exploration and design-partitioning input. The postings establish a reusable-model methodology hiring mandate, not measured deployment. No reliable first-publication date is exposed, so the September observation date remains.", "sources": [ { "title": "Cirrus Logic Careers: Analog Mixed Signal Modeling & Verification Engineer (UL - 01)", "url": "https://jobs.eu.lever.co/cirrus/25795154-6942-4b8b-b5e6-37c1bf0eb7c1", "checkedAt": "2026-10-25", "status": "unavailable", "summary": "Previously verified September 14 description covers equivalent-model reuse, SV-RNM/SV-UDT/Verilog-AMS, AMS-UVM, chip integration and regression debug. The original UL-01 page returns HTTP 404 on October 25; this is not a fresh full-text review.", "archiveUrl": null }, { "title": "Cirrus Logic Careers: current job listing", "url": "https://jobs.eu.lever.co/cirrus", "checkedAt": "2026-10-25", "summary": "Current official index lists related UL-02 modeling and GNEG4 mixed-signal modeling/verification roles. The public listing does not provide a reliable creation date.", "status": "available", "archiveUrl": null }, { "title": "Cirrus Logic Careers: Analog Mixed Signal Modeling Engineer (UL - 02)", "url": "https://jobs.eu.lever.co/cirrus/37ead846-469d-449a-bfcf-f4ae192c03a5", "checkedAt": "2026-10-25", "summary": "Current official posting and public Lever response repeat equivalent-model reuse across design, UVM and HW/SW validation, SV-RNM/SV-UDT/Verilog-AMS and AMS-UVM component reuse, with architectural exploration and partitioning responsibilities. Observed October 25; first publication is unconfirmed.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cirrus-logic-2026-09-ams-uvm-model-reuse-hiring/" }, { "id": "micron-2026-09-ai-clock-architecture-internship", "when": { "start": "2026-09-14", "precision": "day" }, "kind": "organizational", "companies": [ "micron" ], "people": [], "headline": "Micron clock-architecture internship combines HBM clock exploration with AI-assisted analysis", "fact": "Micron advertised Richardson internship JR110765 in its HBM Architecture team, with a retained listing dated September 14. The role evaluates clock distribution, WDQS timing, PLL concepts, jitter, noise sensitivity and IO timing margins, compares alternative clock architectures and supports architecture-level decisions. It assigns LLM/GenAI engineering workflows for analysis and data evaluation, and links AI assistance to design exploration. This is an advertised analysis mandate, not proof of AI topology synthesis or HDL model generation.", "sources": [ { "title": "Micron Careers: Intern – Clock Design & Architecture (JR110765)", "url": "https://micron.wd1.myworkdayjobs.com/External/job/Richardson-TX/Intern---Clock-Design---Architecture--Intern_JR110765", "checkedAt": "2026-10-15", "summary": "Full employer-indexed duties identify JR110765 and connect AI-assisted analysis with HBM clock/PLL architecture exploration. Absolute first-publication metadata could not be retrieved; relative posting ages are not used as dates.", "status": "available", "archiveUrl": null }, { "title": "RoleSweep: retained Micron clock-architecture internship", "url": "https://rolesweep.com/jobs/9a4060fab7600c85cc814c4571035e13-intern-clock-design-architecture-intern", "checkedAt": "2026-10-15", "summary": "Retained full description displays September 14, 2026. This secondary posting date is the Event’s date basis, not a newly verified official first-publication date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/micron-2026-09-ai-clock-architecture-internship/" }, { "id": "synopsys-2026-09-customer-ams-simulation-flow-hiring", "when": { "start": "2026-09-13", "precision": "day" }, "kind": "organizational", "companies": [ "synopsys" ], "people": [], "headline": "Synopsys simulation product-engineering role includes customer AMS flows and accuracy/performance trade-offs", "fact": "Synopsys posted a Bengaluru product-engineering role for customer simulation and verification engagements. The position covers regression throughput, compilation and elaboration bottlenecks, debug, assertions, coverage and reference flows for block through full-chip verification. When needed, its AMS responsibilities include analog/digital co-simulation, behavioral models, Verilog-AMS integration and convergence trade-offs. AMS experience, including balancing accuracy and performance, is a preferred qualification. This is a customer-support mandate rather than evidence of a particular customer deployment.", "sources": [ { "title": "Synopsys: Simulation and mixed-signal verification product engineer (18747)", "url": "https://careers.synopsys.com/job/bengaluru/sr-staff-product-engineer-simulation-and-mixed-signal-verification/44408/100607370544", "checkedAt": "2026-10-05", "summary": "Official posting dated September 13, 2026. It assigns AMS support where needed within broader customer simulation work and describes co-simulation, behavioral modeling, Verilog-AMS and reference-flow development.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/synopsys-2026-09-customer-ams-simulation-flow-hiring/" }, { "id": "coseda-2026-09-systemc-ams-verification-virtual-prototypes", "when": { "start": "2026-09-10", "precision": "day" }, "kind": "technical", "companies": [ "coseda-technologies" ], "people": [ "thilo-voertler" ], "headline": "COSEDA tutorial presents SystemC-AMS virtual prototypes as verification reference models", "fact": "The DVCon Japan program lists a tutorial by COSEDA presenters Thilo Vörtler and Karsten Einwich on SystemC and SystemC-AMS virtual prototypes. Its published scope covers executable specifications for heterogeneous systems, analog/digital/software test development and reference models for implementation verification. The tutorial also previews future SystemC-AMS standardization; a preview is not a formally issued standard.", "sources": [ { "title": "COSEDA at DVCon Japan 2026", "url": "https://coseda-tech.com/news-reader/coseda-dvcon-japan-2026", "checkedAt": "2026-10-06", "summary": "COSEDA identifies its presenters, September 10 tutorial and executable-specification, test-development and reference-model scope.", "status": "available", "archiveUrl": null }, { "title": "DVCon Japan 2026 official program", "url": "https://www.dvcon-jpn.org/program/contents/", "checkedAt": "2026-10-06", "summary": "The program lists the SystemC/SystemC-AMS tutorial and COSEDA affiliations. This establishes the listed presentation and its advertised content.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/coseda-2026-09-systemc-ams-verification-virtual-prototypes/" }, { "id": "ecosystem-2026-09-sv-msi-systemverilog-2028-roadmap", "when": { "start": "2026-09-10", "precision": "day" }, "kind": "technical", "companies": [ "cadence" ], "people": [], "headline": "SV-MSI update links mixed-net interoperability to SystemVerilog-2028, SV-AMS, and UVM-MS", "fact": "The DVCon Japan program lists an SV-MSI update by Abhijit Madhu Kumar, identified as a Cadence Principal Solutions Engineer. It describes proposed interoperability between logic nets and RNM/nettype representations toward IEEE 1800-2028, alongside the SV-AMS and UVM-MS roadmap. These are presented proposals and roadmap directions, not already published standard requirements or released functionality.", "sources": [ { "title": "DVCon Japan 2026: SystemVerilog Mixed-Signal Interface Types BoF", "url": "https://www.dvcon-jpn.org/program/contents/", "checkedAt": "2026-10-06", "summary": "The official program identifies Abhijit Madhu Kumar with Cadence and describes mixed-net interoperability proposals toward IEEE 1800-2028 and future SV-AMS/UVM-MS work.", "status": "available", "archiveUrl": null }, { "title": "DVCon Japan 2026 official home page", "url": "https://www.dvcon-jpn.org/", "checkedAt": "2026-09-18", "summary": "The official DVCon Japan site states that DVCon Japan 2026 was held on September 10, 2026 at Pacifico Yokohama North.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ecosystem-2026-09-sv-msi-systemverilog-2028-roadmap/" }, { "id": "infineon-2026-10-ams-model-validation-internships", "when": { "start": "2026-09-09", "precision": "day" }, "kind": "organizational", "companies": [ "infineon" ], "people": [], "headline": "Infineon lists internships and graduate roles for AMS model verification", "fact": "Infineon posted Graduate - Analog Mixed-Signal Design Verification Engineer role HRC1763746 with an official September 9, 2026 date. It assigns Verilog-AMS/SystemVerilog model generation and maintenance, testbenches, nominal/corner simulation, fault injection and regressions. Related Andover and Shanghai internships observed October 5 cover behavioral models, AMS IP/SoC environments, RTL/model integration and model-quality checks. January/summer 2027 are planned employment starts. The official graduate date is the earliest verified publication among these grouped roles; the internships' first publication dates remain unconfirmed. These are hiring requirements, not deployed practices.", "sources": [ { "title": "Infineon: Andover AMS design-verification internship — employer LinkedIn posting", "url": "https://www.linkedin.com/jobs/view/internship-analog-mixed-signal-design-verification-engineer-at-infineon-technologies-4465695379", "checkedAt": "2026-10-25", "summary": "Employer description retains behavioral models, testbenches, nominal/corner checks and regressions. The role was previously observed October 5; current LinkedIn datePosted is October 7, which is not a reliable first-publication date or a reason to erase the earlier observation.", "status": "available", "archiveUrl": null }, { "title": "Infineon: Shanghai mixed-signal verification internship — employer LinkedIn posting", "url": "https://cn.linkedin.com/jobs/view/mixed-signal-verification-intern-at-infineon-technologies-4469893332", "checkedAt": "2026-10-25", "summary": "Employer description retains AMS IP/SoC simulation, RTL/model integration and behavioral-assumption/corner checks. Previously observed October 5; current LinkedIn metadata is October 7 and does not establish original publication.", "status": "available", "archiveUrl": null }, { "title": "Infineon Careers: Graduate - Analog Mixed-Signal Design Verification Engineer (HRC1763746)", "url": "https://jobs.infineon.com/careers/job/563808971876168", "checkedAt": "2026-10-25", "summary": "Official JobPosting datePosted is September 9, 2026 at 13:22:14. Full graduate duties include Verilog-AMS/SystemVerilog models, fault injection, corners and regressions. This earlier verified publication corrects the grouped Event's October observation-date basis; 2027 employment starts are separate.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-10-ams-model-validation-internships/" }, { "id": "sony-2026-09-loadbench-analog-topology-benchmark", "when": { "start": "2026-09-09", "precision": "day" }, "kind": "technical", "companies": [ "sony-ai", "sony-semiconductor-solutions" ], "people": [ "stefan-uhlich", "lorenzo-servadei" ], "headline": "Sony and university researchers present LOADBench for analog circuit generation and topology-selection evaluation", "fact": "The MLCAD 2026 program lists LOADBench with Stefan Uhlich, Lorenzo Servadei and university coauthors in the September 9 analog-design session. The work provides more than 100 SkyWater130 op-amp topologies, annotations and ngspice testbenches, with benchmarks including structural circuit generation and topology selection as well as sizing. The program lists Sony Semiconductor Solutions Europe and Sony AI; the later manuscript uses SonyAI affiliation labels. The October 15 arXiv upload supports this September research milestone and is not treated as a second Event or the first public presentation.", "sources": [ { "title": "MLCAD 2026 official program: September 9, session 8", "url": "https://mlcad.org/symposium/2026/program/", "checkedAt": "2026-10-19", "summary": "The program lists LOADBench on September 9 with its authors and Sony AI/Sony Semiconductor Solutions Europe and university affiliations.", "status": "available", "archiveUrl": null }, { "title": "LOADBench manuscript and artifact description", "url": "https://arxiv.org/html/2610.21591", "checkedAt": "2026-10-19", "summary": "The October 15, 2026 manuscript describes topology data, ngspice testbenches and six benchmark tasks; generation and topology selection qualify beyond sizing-only optimization.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sony-2026-09-loadbench-analog-topology-benchmark/" }, { "id": "analog-devices-2026-09-ai-mixed-signal-systems-design-hiring", "when": { "start": "2026-09-08", "precision": "day" }, "kind": "organizational", "companies": [ "analog-devices" ], "people": [], "headline": "ADI seeks mixed-signal systems design engineers for agentic-AI and LLM workflows", "fact": "ADI posted Staff Systems Design Engineer R264626 for San Jose or Colorado Springs, spanning analog, digital, firmware and system architecture for mixed-signal ICs such as power management, sensor interfaces and data converters. The posting says its team uses agentic AI and LLM workflows for design, verification and process migration and requires willingness to adopt AI-assisted methods. AI-driven design exploration and automated verification are preferred experience. This records the team’s stated workflow and hiring requirements, without independently establishing deployment outcomes or AI-generated circuit architectures.", "sources": [ { "title": "ADI Careers: Staff Systems Design Engineer (R264626)", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/US-CA-San-Jose-Rio-Robles/Staff-Systems-Design-Engineer_R264626", "checkedAt": "2026-10-15", "summary": "Official public Workday jobPostingInfo gives startDate September 8, 2026 and R264626. Full duties cover mixed-signal IC design, agentic AI/LLM design and verification, and process migration. Prior AI experience is preferred; willingness to adopt the methods is essential.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2026-09-ai-mixed-signal-systems-design-hiring/" }, { "id": "broadcom-2026-09-global-dms-verification-methodology-hiring", "when": { "start": "2026-09-08", "precision": "day" }, "kind": "organizational", "companies": [ "broadcom" ], "people": [], "headline": "Broadcom storage-ASIC postings call for cross-site DMS methodology and AI-assisted verification automation", "fact": "A Broadcom Senior Digital / Mixed-Signal IC Design or Verification Engineer posting for Data Center Enterprise Storage, indexed as posted September 8, 2026 under requisition R026970, describes a methodology leader and technical bridge across US and Asia design centers. Its verification scope includes UVM-based block- and system-level testbenches, functional and code coverage closure, SVA and UVM/OVM methodology, event-driven analog-boundary modeling, and AI-assisted workflows for testbench generation and debug. A separate Broadcom careers posting, R025692, describes a closely related DMS verification methodology-leader role with the same cross-site and AI-assisted-automation themes; the postings do not establish that the two requisitions belong to the same team or define a company-wide standard.", "sources": [ { "title": "JobsRadar: Senior Digital / Mixed-Signal IC Design or Verification Engineer (R026970)", "url": "https://jobs-radar.com/en/job/senior-digital-mixed-signal-ic-design-or-verification-engine-at-broadcom-82dadb", "checkedAt": "2026-09-14", "summary": "The indexed Broadcom requisition R026970 is dated September 8, 2026 and describes the Data Center Enterprise Storage role, US/Asia methodology leadership, UVM/SVA verification, analog-boundary modeling, coverage closure, and AI-assisted testbench-generation/debug automation.", "status": "available", "archiveUrl": null }, { "title": "SiliconBoard: Senior Digital / Mixed-Signal IC Design or Verification Engineer (R026970)", "url": "https://siliconboard.co/jobs/senior-digital-mixed-signal-ic-design-or-verification-engine-at-broadcom-08f5ea15", "checkedAt": "2026-09-14", "summary": "A second current index reproduces requisition R026970 and the same mixed-signal verification, methodology, global-team, and AI-assisted automation responsibilities.", "status": "available", "archiveUrl": null }, { "title": "Broadcom Careers: Senior Digital Mixed-Signal (DMS) Verification Engineer (R025692)", "url": "https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-Mendota-Heights-Northland/Senior-Digital-Mixed-Signal--DMS--Verification-Engineer_R025692", "checkedAt": "2026-09-14", "summary": "A separate official Broadcom careers record describes a DMS verification methodology leader spanning US and Asia teams, UVM/OVM, SVA, analog behavioral modeling, coverage closure, and AI-assisted verification automation. It is corroboration of the public hiring signal, not evidence that R025692 and R026970 are the same role.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/broadcom-2026-09-global-dms-verification-methodology-hiring/" }, { "id": "analog-devices-2026-vcm-fpga-svreal-comparison", "when": { "start": "2026-09-06", "precision": "day" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices authors compare FPGA fixed-point modeling with an earlier SVREAL-generated implementation", "fact": "Analog Devices CSS authors published an industrial case study of a synthesizable fixed-point SystemVerilog model for a Voice Coil Motor driver, derived from analog equations and deployed on FPGA for real-time emulation. The paper compares the implementation with an earlier automated real-number RTL generation flow using the SVREAL library, reports reduced FPGA resource use for the manual fixed-point implementation, and validates model fidelity against the reference analog behavioral model.", "sources": [ { "title": "Synthesizable Fixed-Point Model of a Voice Coil Motor Driver for FPGA Emulation", "url": "https://www.mdpi.com/2674-0729/5/3/26", "checkedAt": "2026-09-25", "summary": "The September 6, 2026 Chips paper by Analog Devices CSS authors presents the VCM FPGA-emulation case, compares manual fixed-point RTL with an earlier MSDSL/SVREAL implementation, and reports FPGA resource and model-fidelity results.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2026-vcm-fpga-svreal-comparison/" }, { "id": "ams-osram-2026-09-lsp-rnm-top-level-verification-hiring", "when": { "start": "2026-09-03", "precision": "day" }, "kind": "organizational", "companies": [ "ams-osram" ], "people": [], "headline": "ams OSRAM LSP role combines RNM model validation, UVM integration and AMS top-level checks", "fact": "ams OSRAM posted a Bucharest ASIC Analog Mixed-Signal Verification Engineer role in its Light Sensors & Photonics business unit. The position defines verification strategies and plans, develops and validates analog and real-number behavioral models, integrates analog models into UVM mixed-signal testbenches, and executes top-level AMS verification with automatic checks. The qualifications name SystemVerilog RNM, Verilog-AMS, analog checkers, reusable verification components and scripting.", "sources": [ { "title": "ams OSRAM: ASIC Analog Mixed-Signal Verification Engineer (24163)", "url": "https://jobs.ams-osram.com/en/job/ASIC-Design-Verification-Engineer-d_m_f-Bucharest/24163", "checkedAt": "2026-10-05", "summary": "Official posting identifies Bucharest, LSP, job 24163 and September 3, 2026 publication. It explicitly assigns behavioral model validation, UVM integration and top-level AMS checks.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ams-osram-2026-09-lsp-rnm-top-level-verification-hiring/" }, { "id": "infineon-2026-09-ai-ams-modeling-graduate-hiring", "when": { "start": "2026-09-03", "precision": "day" }, "kind": "organizational", "companies": [ "infineon" ], "people": [], "headline": "Infineon graduate role pairs analog behavioral modeling with AI verification methodology", "fact": "Infineon advertised an Andover Regional Graduate Program – Engineer Verification and Validation role for computing power-management products, with a retained September 3 listing. It assigns AI-based verification-flow improvement for coverage and documentation, alongside Verilog-AMS/SystemVerilog behavioral models, schematic correlation, targeted testbenches and analog/digital integration debug. The AI duty is an assigned methodology task; the posting does not say that AI generates those models. This is distinct from the later general AMS internship advertisements.", "sources": [ { "title": "Infineon: Regional Graduate Program – Engineer Verification and Validation — employer LinkedIn posting", "url": "https://www.linkedin.com/jobs/view/regional-graduate-program-engineer-verification-and-validation-at-infineon-technologies-4462820778", "checkedAt": "2026-10-15", "summary": "Employer-attributed duties explicitly pair an AI verification-methodology assignment with analog behavioral modeling, Verilog-AMS/SystemVerilog and schematic correlation. Current LinkedIn JobPosting metadata gives October 7 UTC, a later channel posting than the retained September record.", "status": "available", "archiveUrl": null }, { "title": "Hardware FYI: retained Infineon graduate verification role", "url": "https://jobs.hardwarefyi.com/jobs/infineon-technologies-regional-graduate-program-engineer-verification-and-validation", "checkedAt": "2026-10-15", "summary": "Retained full description displays September 3, 2026 and the same role/location/duties. This secondary date is used rather than treating the later LinkedIn posting as the first occurrence.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-09-ai-ams-modeling-graduate-hiring/" }, { "id": "infineon-2026-09-svreal-fpga-system-modeling-hiring", "when": { "start": "2026-09-03", "precision": "day" }, "kind": "organizational", "companies": [ "infineon" ], "people": [], "headline": "Infineon posts a SystemVerilog/svreal modeling role for FPGA and firmware validation", "fact": "Infineon posted a Bengaluru Staff Engineer Design role whose description calls for developing RNM with SystemVerilog and svreal, building FPGA prototypes for SoC and system validation, and supporting pre- and post-silicon firmware validation and hardware/software debug. The role also covers simulation and FPGA automation, continuous integration, and modeling and prototyping methodology.", "sources": [ { "title": "Infineon: Staff Engineer Design (HRC1782391)", "url": "https://in.linkedin.com/jobs/view/staff-engineer-design-at-infineon-technologies-4462818766", "checkedAt": "2026-09-09", "summary": "Infineon's company-attributed LinkedIn posting identifies requisition HRC1782391 and the SystemVerilog/svreal, FPGA, firmware-validation, automation, and methodology responsibilities. Its structured posting metadata gives September 3, 2026.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-09-svreal-fpga-system-modeling-hiring/" }, { "id": "synopsys-2026-09-reusable-ip-ams-verification-hiring", "when": { "start": "2026-09-03", "precision": "day" }, "kind": "organizational", "companies": [ "synopsys" ], "people": [], "headline": "Synopsys posts an AMS verification role describing reusable models and monitors across IP families", "fact": "Synopsys posted a Hyderabad senior staff role to own AMS verification plans, environments, coverage, and sign-off for mixed-signal IP blocks and subsystems. Its description combines SystemVerilog/UVM with Verilog-A and Verilog-AMS models and mixed-signal simulators, and calls for behavioral models and monitors to be reused across IP families. Requested circuit knowledge includes bias circuits, regulators, PLLs, ADCs, and DACs. A September 28 posting repeats this IP-verification mandate and is grouped with the September 3 listing.", "sources": [ { "title": "Synopsys: Sr Staff Mixed-Signal Verification Engineer (18564)", "url": "https://careers.synopsys.com/job/hyderabad/sr-staff-mixed-signal-verification-engineer/44408/100174818352", "checkedAt": "2026-09-09", "summary": "The official posting is dated September 3, 2026, and describes AMS verification of Synopsys IP, cross-family model/monitor reuse, and automation. It does not explicitly name RNM.", "status": "available", "archiveUrl": null }, { "title": "Synopsys: Related AMS verification posting (18971)", "url": "https://careers.synopsys.com/en/job/hyderabad/sr-staff-mixed-signal-verification-engineer/44408/101302185280", "checkedAt": "2026-10-05", "summary": "Official posting dated September 28, 2026, repeats the September 3 IP-verification mandate, including reusable behavioral models and monitors. Grouped here rather than represented as another adoption milestone.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/synopsys-2026-09-reusable-ip-ams-verification-hiring/" }, { "id": "texas-instruments-2026-09-mixed-signal-coverage-dv-internship", "when": { "start": "2026-09-03", "precision": "day" }, "kind": "organizational", "companies": [ "texas-instruments" ], "people": [], "headline": "Texas Instruments internship listing includes analog functional coverage, random stimuli and chip-level timing checks", "fact": "A University of Pittsburgh recruiting job posting dated September 3 advertises a Texas Instruments Design Verification Engineering internship. The employer description includes SystemVerilog coverage for voltages, currents and real values alongside digital coverage, constrained-random analog stimulus and automatic result checking. It also assigns RTL and gate-level simulations with SDF for timing between analog and digital circuits, regression scripting, verification planning and improvements to verification methods.", "sources": [ { "title": "Texas Instruments: Design verification internship, MS/PhD (25017546)", "url": "https://careers.ti.com/en/sites/CX/job/25017546", "checkedAt": "2026-10-05", "summary": "Official TI application for the graduate design-verification internship; the employer description is also available in the university recruiting listing.", "status": "available", "archiveUrl": null }, { "title": "Texas Instruments DV internship — University of Pittsburgh recruitment listing", "url": "https://careercentral.pitt.edu/jobs/texas-instruments-inc-design-verification-engineering-intern-ms-phd/", "checkedAt": "2026-10-05", "summary": "Employer-supplied description on the university board, where recruitment began September 3, 2026. The Event uses this board date, not an inferred first employer publication. It explicitly covers analog functional coverage, constrained-random analog stimulus and RTL/gate+SDF checks.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2026-09-mixed-signal-coverage-dv-internship/" }, { "id": "arago-2026-09-mixed-signal-rnm-verification-hiring", "when": { "start": "2026-09-02", "precision": "day" }, "kind": "organizational", "companies": [ "arago" ], "people": [], "headline": "Arago posts mixed-signal verification role for its optical/CMOS computing SoCs", "fact": "Arago posted a senior mixed-signal verification role in Paris or Tel Aviv to own methodology and verification of digital-to-analog interfaces in its SoCs. The responsibilities include block, subsystem, and SoC environments, behavioral and real-number models, assertions, coverage, and sign-off. SystemVerilog and UVM or an equivalent methodology are requested; SystemVerilog RNM, wreal, and Verilog-AMS appear among preferred experience.", "sources": [ { "title": "Arago: Senior Mixed-Signal Verification Engineer", "url": "https://jobs.ashbyhq.com/arago/0c2b7715-f475-4fce-b7d7-e71dadc23525", "checkedAt": "2026-09-09", "summary": "Arago's official Ashby listing describes its optical/CMOS computing context and the mixed-signal verification mandate, with named RNM technologies under nice-to-have experience. The public job-board API gives publication as September 2, 2026.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/arago-2026-09-mixed-signal-rnm-verification-hiring/" }, { "id": "mafra-2026-09-formal-rnm-smt-model-checking", "when": { "start": "2026-09-02", "precision": "day" }, "kind": "technical", "companies": [ "cadence" ], "people": [ "augusto-mafra" ], "headline": "FMCAD paper reports SMT-based formal verification of SystemVerilog RNM", "fact": "TU Wien's repository made available Augusto Mafra and Haniel Barbosa's FMCAD paper on formal verification of SystemVerilog RNM by extending Yosys and Pono. The study uses 31 benchmarks: 17 public GPL-3.0 benchmarks and 14 built from proprietary Cadence models/testbenches. It compares real-arithmetic and IEEE floating-point SMT interpretations, whose semantics can produce different verification results. The v2.0.5 public implementation provides benchmarks, results and fixed revisions of Yosys, Pono and smt-switch. This is a research flow, not a claimed Jasper product feature; September 2 dates the paper's repository availability.", "sources": [ { "title": "Formal Verification of Mixed-Signal Systems Using Real Number Modeling with SMT-based Model Checking", "url": "https://repositum.tuwien.at/handle/20.500.12708/230518?mode=full", "checkedAt": "2026-10-06", "summary": "The record gives September 2 repository availability. The full paper distinguishes 17 GPL-3.0 public and 14 proprietary Cadence benchmarks, mathematical-real versus IEEE floating-point semantics, and research-tool forks rather than a Jasper feature.", "status": "available", "archiveUrl": null }, { "title": "Public RNM formal-verification implementation v2.0.5", "url": "https://github.com/augustomafra/sv_rnm_formal_verification/tree/v2.0.5", "checkedAt": "2026-10-06", "summary": "Public benchmarks, GPL-3.0 license, logs and results; README pins Yosys a726634e9e9883709f94c5e479ce8558af3da704, Pono 3e1453cfa5d18616b05424c8af00d74aa41b4292 and smt-switch 5815833ed9b553ef594a8236b1b0ca323fc6c1f5.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/mafra-2026-09-formal-rnm-smt-model-checking/" }, { "id": "stmicroelectronics-2026-09-dms-power-pll-behavioral-modeling", "when": { "start": "2026-09-02", "precision": "day" }, "kind": "technical", "companies": [ "stmicroelectronics" ], "people": [], "headline": "STMicroelectronics authors present DMS power estimation and feedforward PLL behavioral modeling", "fact": "The DVCon India 2026 Day 2 agenda lists two AMS & Low Power Design presentations co-authored by Amit Singh: “Left-Shift Power Estimation in SoC Design: Verification-Integrated Framework for Early Power Estimation Using Digital Mixed-Signal Simulation” with Isha Sharma, and “Design-Focused Feedforward Behavioural Modeling of PLL IPs for Fast SoC Verification” with Preeti Shukla. Public profiles identify Sharma and Shukla with STMicroelectronics. This Event records the two public technical disclosures without asserting unexposed accuracy, runtime, or deployment results.", "sources": [ { "title": "DVCon India 2026 Day 2 agenda", "url": "https://dvcon-india.org/wp-content/uploads/2026/08/Day2v13_DVCon_India_2026_Agenda-copy.pdf", "checkedAt": "2026-09-21", "summary": "The official September 2 AMS & Low Power Design agenda lists the DMS power-estimation paper by Isha Sharma and Amit Singh and the feedforward PLL behavioral-modeling paper by Preeti Shukla and Amit Singh.", "status": "available", "archiveUrl": null }, { "title": "Isha Sharma public profile", "url": "https://in.linkedin.com/in/isha-sharma-77a771ab", "checkedAt": "2026-09-21", "summary": "The public profile identifies Isha Sharma with STMicroelectronics.", "status": "available", "archiveUrl": null }, { "title": "Preeti Shukla public profile", "url": "https://in.linkedin.com/in/preetishukla-nita", "checkedAt": "2026-09-21", "summary": "The public profile identifies Preeti Shukla with STMicroelectronics.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/stmicroelectronics-2026-09-dms-power-pll-behavioral-modeling/" }, { "id": "enphase-2026-riscv-rnm-closed-loop-verification-hiring", "when": { "start": "2026-09", "precision": "month" }, "kind": "organizational", "companies": [ "enphase" ], "people": [], "headline": "Enphase lists processor-verification roles integrating SV-RNM with analog power-stage closed-loop verification", "fact": "Enphase listed Staff and Sr. Staff processor-verification roles for a custom RISC-V VLIW processor used in energy-conversion control. The descriptions combine RTL simulation, SystemVerilog Real Number Modeling, analog simulation platforms such as NL5, C/C++ power-conversion and plant models, and Python automation in system-level mixed-signal verification, with validation of closed-loop behavior, deterministic timing, fault handling, and interactions between digital control algorithms and analog power stages.", "sources": [ { "title": "Enphase Energy Careers: Sr. Staff Engineer – Processor Verification and Compiler Validation", "url": "https://jobs.jobvite.com/enphase-energy/job/og0NAfwn", "checkedAt": "2026-09-25", "summary": "The live official Fremont role describes the custom RISC-V VLIW processor and the system-level mixed-signal environment spanning SV-RNM, NL5, C/C++ power-stage and plant models, Python automation, and closed-loop verification.", "status": "available", "archiveUrl": null }, { "title": "Enphase Energy engineering careers", "url": "https://jobs.jobvite.com/enphase-energy/search?c=Engineering&p=0", "checkedAt": "2026-09-25", "summary": "The live official engineering-job listing shows both Staff and Sr. Staff Processor Verification and Compiler Validation roles in Fremont during September 2026.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/enphase-2026-riscv-rnm-closed-loop-verification-hiring/" }, { "id": "qualcomm-2026-serdes-modeling-silicon-correlation-hiring", "when": { "start": "2026-09", "precision": "month" }, "kind": "organizational", "companies": [ "qualcomm" ], "people": [], "headline": "Qualcomm lists Staff SerDes role spanning behavioral modeling, system verification, and silicon correlation", "fact": "Qualcomm Canada ULC listed a Cross-Functional Engineer, Staff role for high-speed SerDes work. The description assigns oversight of analog and mixed-signal behavioral-model development and verification, higher-abstraction analog verification, system verification with digital-verification and firmware teams, calibration, power modeling, and correlation of pre-silicon models and predicted power with post-silicon measurements. It asks for 106 Gbps-and-higher SerDes experience and SystemVerilog behavioral modeling, and names clock generation and distribution, VCOs, phase interpolators, PLLs, ADCs, and DACs among relevant circuit experience.", "sources": [ { "title": "Qualcomm: Cross-Functional Engineer, Staff — Toronto", "url": "https://ca.linkedin.com/jobs/view/cross-functional-engineer-staff-at-qualcomm-4468457788", "checkedAt": "2026-09-28", "summary": "The live company-attributed LinkedIn posting identifies Qualcomm Canada ULC and describes the SerDes modeling, mixed-signal/system verification, calibration, power-modeling, post-silicon correlation, SystemVerilog, and 106 Gbps-and-higher scope.", "status": "available", "archiveUrl": null }, { "title": "Cross-Functional Engineer, Staff — Qualcomm Canada", "url": "https://movojobs.ca/qualcomm/jobs/cross-functional-engineer-staff-771575", "checkedAt": "2026-09-28", "summary": "A current recovery copy preserves the original Qualcomm description, lists Toronto and Ottawa, and dates its captured posting to September 19, 2026; the Event uses month precision because public copies expose inconsistent relative/index dates.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/qualcomm-2026-serdes-modeling-silicon-correlation-hiring/" }, { "id": "astera-labs-2026-08-serdes-rnm-ams-verification-hiring", "when": { "start": "2026-08-31", "precision": "day" }, "kind": "organizational", "companies": [ "astera-labs" ], "people": [], "headline": "Astera Labs posts SerDes/PHY verification role covering RNM, AMS co-simulation, and emulation planning", "fact": "Astera Labs posted a principal SerDes/PHY verification role for PCIe Gen6/7, UCIe, UALink, and Ethernet interfaces. The description calls for UVM environments, RNM and behavioral-model collaboration with analog designers, CDR and training checks, and analog handoff validation. It also assigns methodology decisions across AMS co-simulation, gate-level simulation, and emulation, and prefers emulator familiarity and pre/post-silicon correlation experience. A related tech-lead listing checked on October 5 repeats this SerDes/PHY verification scope.", "sources": [ { "title": "Astera Labs: Principal Design Verification Engineer — SerDes/PHY IP", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4729354005", "checkedAt": "2026-09-09", "summary": "The official Greenhouse posting describes the SerDes verification scope; its public job-board API gives first publication as August 31, 2026. It lists RNM and emulation responsibilities but does not state that RNM models execute on the emulators.", "status": "available", "archiveUrl": null }, { "title": "Astera Labs: Design verification tech lead, SerDes/PHY IP", "url": "https://job-boards.greenhouse.io/asteralabs/jobs/4733710005", "checkedAt": "2026-10-05", "summary": "Related official Greenhouse listing checked October 5, 2026 repeats RNM/model collaboration, AMS simulation, interface verification and emulation-planning duties. Retained as another source for the existing mandate; its first publication is not established.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/astera-labs-2026-08-serdes-rnm-ams-verification-hiring/" }, { "id": "mediatek-2026-08-ams-methodology-and-modeling-hiring", "when": { "start": "2026-08-30", "precision": "day" }, "kind": "organizational", "companies": [ "mediatek" ], "people": [], "headline": "MediaTek's careers site shows dedicated AMS modeling and verification methodology groups", "fact": "On August 30, 2026, MediaTek's careers site listed roles in dedicated AMS modeling and verification methodology groups responsible for modeling and verification platforms, coding and validation processes, experiments, deployment, UVM, assertions, coverage closure, and automation. A related modeling role calls for SystemVerilog RNM models of oscillators, voltage references and meters, LDOs, and temperature sensors, with model-versus-schematic verification, coverage, assertions, and Python.", "sources": [ { "title": "Analog/Mixed-Signal Modeling Methodology Development Engineer", "url": "https://careers.mediatek.com/en/jobs/MTK120231030000", "checkedAt": "2026-08-30", "summary": "Official MediaTek role for a dedicated group establishing behavioral-modeling, coding, validation, integration, and deployment processes and a modeling platform.", "status": "available", "archiveUrl": null }, { "title": "Analog/Mixed-Signal Design Verification Methodology Development Engineer", "url": "https://careers.mediatek.com/en/jobs/MTK120231030001", "checkedAt": "2026-08-30", "summary": "Official MediaTek role for a dedicated AMS DV methodology group supporting UVM, assertions, coverage, automation, and deployment across IP and chip teams.", "status": "available", "archiveUrl": null }, { "title": "Analog Modeling Engineer", "url": "https://careers.mediatek.com/en/jobs/MUS120260701001", "checkedAt": "2026-08-30", "summary": "Official MediaTek role for supply- and process-aware SystemVerilog RNM models, model-to-schematic verification, coverage, assertions, and Python.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/mediatek-2026-08-ams-methodology-and-modeling-hiring/" }, { "id": "apple-2026-08-cad-ams-simulation-methodology", "when": { "start": "2026-08-28", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts CAD roles covering cross-team AMS simulation methodology and AI-assisted automation", "fact": "Apple posted related CAD Automation and Mixed-Signal Simulation Engineer roles in Austin and Sunnyvale. The senior description assigns ownership of AMS simulation methodology across analog, RF, interconnect, PMIC, and memory teams, spanning circuit and RTL simulation, behavioral modeling, co-simulation, logic equivalence, sign-off, and automation. Preferred experience includes discipline resolution, binding/IE setup, connect modules, AMSD blocks, wreal, RNM, UDN, and SystemVerilog/Verilog-A/Verilog-AMS. Both roles mention applying LLMs or AI agents to CAD software, test generation, and debug among preferred qualifications, with leadership of that work requested in the senior role.", "sources": [ { "title": "Senior CAD Automation and Mixed-Signal Simulation Engineer", "url": "https://jobs.apple.com/en-us/details/200680373-3956/senior-cad-automation-and-mixed-signal-simulation-engineer", "checkedAt": "2026-09-09", "summary": "The live official senior role 200680373-3956 displays August 28, 2026, with Austin and Sunnyvale work locations. It describes AMS methodology ownership and lists LLM/AI-agent CAD automation leadership among preferred qualifications.", "status": "available", "archiveUrl": null }, { "title": "CAD Automation and Mixed-Signal Simulation Engineer", "url": "https://jobs.apple.com/en-us/details/200680364-3956/cad-automation-and-mixed-signal-simulation-engineer", "checkedAt": "2026-09-09", "summary": "The live official companion role 200680364-3956 also displays August 28, 2026. It covers the same teams and AMS methodology family and prefers familiarity with LLM/AI-agent use in CAD software, test generation, and debugging.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-08-cad-ams-simulation-methodology/" }, { "id": "qorvo-2026-power-management-mixed-signal-verification-hiring", "when": { "start": "2026-08-27", "precision": "day" }, "kind": "organizational", "companies": [ "skyworks" ], "people": [], "headline": "Qorvo posts management and senior principal roles for power-management mixed-signal verification", "fact": "Qorvo posted a manager role to grow and direct a mixed-signal verification team for power-loss protection, PMIC, motor-control, and battery-management products. Its responsibilities include metric-driven plans, constrained-random tests and automated checkers in a UVM environment, RNM or Verilog-AMS models, methodology improvement, and verification automation; SV-UDN/EEnet and AI-workflow familiarity are preferred. A same-day senior principal listing describes the corresponding top-level UVM and RNM/Verilog-AMS work. These postings describe hiring mandates.", "sources": [ { "title": "Qorvo Careers: Sr. Mixed Signal Design Verification Manager (10286)", "url": "https://careers.qorvo.com/job/Richardson-Sr_-Mixed-Signal-Design-Verification-Manager-TX-75081/1404687300/", "checkedAt": "2026-09-09", "summary": "The official Qorvo page exposes an August 27, 2026 posting date and describes the team-growth, product, UVM, RNM/Verilog-AMS, methodology, automation, and preferred SV-UDN/EEnet and AI-workflow scope.", "status": "available", "archiveUrl": null }, { "title": "Qorvo Careers: Sr Principal Mixed Signal Verification Engineer (10289)", "url": "https://careers.qorvo.com/job/Richardson-Sr-Principal-Mixed-Signal-Verification-Engineer-TX-75081/1404684000/", "checkedAt": "2026-09-09", "summary": "The official Richardson posting carries the same August 27, 2026 date in its posting metadata. It describes top-level UVM verification and RNM/Verilog-AMS modeling for the same power-management product family, with preferred SV-UDN/EEnet, assertions, and coverage experience.", "status": "available", "archiveUrl": null }, { "title": "Skyworks Completes Combination with Qorvo", "url": "https://www.qorvo.com/about/news-events/news-releases/2026/skyworks-completes-combination-with-qorvo", "checkedAt": "2026-11-08", "summary": "The official October 5, 2026 completion announcement states that the combined company operates as Skyworks. This source supports current canonical grouping only; the earlier Qorvo hiring Event retains its historical name, ID and date and does not establish methodology transfer.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/qorvo-2026-power-management-mixed-signal-verification-hiring/" }, { "id": "cadence-2026-generative-ai-rnm-internship", "when": { "start": "2026-08-24", "precision": "day" }, "kind": "organizational", "companies": [ "cadence" ], "people": [], "headline": "Cadence internship posting proposes evaluating generative AI for real-number-model creation", "fact": "Cadence posted a Milan internship role that proposes investigating generative AI on industry cases, validating AI flows, and using Model in Minutes in the Virtuoso environment to build real-number models. This is an exploratory internship mandate and product-evaluation signal, not proof of a deployed customer methodology or validated productivity result.", "sources": [ { "title": "Cadence University Careers: Intern on AMS Tool in Milan", "url": "https://cadence.wd1.myworkdayjobs.com/univ_careers/job/milan/intern-on-ams-tool-in-milan_r55238-2", "checkedAt": "2026-08-31", "summary": "Official Cadence requisition R55238-2, posted August 24, 2026, describes the exploratory generative-AI evaluation and Model in Minutes real-number-model work.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2026-generative-ai-rnm-internship/" }, { "id": "sony-2026-08-llm-spicemixer-topology-generation", "when": { "start": "2026-08-24", "precision": "day" }, "kind": "technical", "companies": [ "sony-ai", "sony-semiconductor-solutions" ], "people": [ "stefan-uhlich", "lorenzo-servadei" ], "headline": "Sony AI and Sony Semiconductor Solutions authors publish LLM-SPICEMixer for analog netlist generation", "fact": "Stefan Uhlich, Lorenzo Servadei and coauthors publish LLM-SPICEMixer, combining evolutionary circuit synthesis with an LLM operator that proposes new SPICE netlists from promising candidates. SPICE evaluation, rather than the language model, supplies the circuit reward. The task synthesizes transistor-level analog discriminant circuits. Author affiliations distinguish Sony AI in Switzerland, Sony Semiconductor Solutions in Japan and university collaborators. This is simulated topology-generation research, not fixed-topology sizing alone or evidence of production deployment.", "sources": [ { "title": "Spicing up Genetic Netlist Generation with LLMs: publication record", "url": "https://arxiv.org/abs/2608.23317", "checkedAt": "2026-10-19", "summary": "The arXiv record dates the initial version to August 24, 2026.", "status": "available", "archiveUrl": null }, { "title": "LLM-SPICEMixer v1: affiliations and synthesis flow", "url": "https://arxiv.org/html/2608.23317v1", "checkedAt": "2026-10-19", "summary": "The manuscript explicitly identifies Sony AI and Sony Semiconductor Solutions, the IGEL netlist-proposal operator and transistor-level circuit synthesis evaluated by SPICE.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sony-2026-08-llm-spicemixer-topology-generation/" }, { "id": "blue-origin-2026-08-terawave-ams-cosimulation-methodology-hiring", "when": { "start": "2026-08-21", "precision": "day" }, "kind": "organizational", "companies": [ "blue-origin" ], "people": [], "headline": "Blue Origin advertises TeraWave AMS co-simulation methodology and behavioral-model infrastructure", "fact": "Blue Origin advertised TeraWave AMS Design Verification Engineer R65544 to lead mixed-mode verification methodology. The role defines the co-simulation EDA environment with analog and digital teams, creates Verilog/SystemVerilog testbenches and analog/mixed-signal behavioral models, and develops block- and chip-level verification methods. An August 21 recruiting-board copy predates the current official Workday September 15 date. The earlier retained public posting dates this Event; the role establishes a hiring mandate for model and verification infrastructure, without an assigned AI-verification task.", "sources": [ { "title": "Blue Origin Careers: Analog Mixed-Signal Design Verification Engineer - TeraWave (R65544)", "url": "https://blueorigin.wd5.myworkdayjobs.com/en-US/BlueOrigin/job/Analog-Mixed-Signal-Design-Verification-Engineer---TeraWave_R65544", "checkedAt": "2026-10-25", "summary": "Official Workday full description assigns co-simulation environment/methodology and Verilog/SystemVerilog model and testbench development. Current startDate is September 15, 2026; this is later than the retained public recruiting history.", "status": "available", "archiveUrl": null }, { "title": "FPGAjobs: retained Blue Origin TeraWave AMS role", "url": "https://www.fpgajobs.com/company/blue-origin/job/analog-mixed-signal-design-verification-engineer-t/ykty0rh3FC/", "checkedAt": "2026-10-25", "summary": "Retained employer description and JobPosting datePosted record August 21, 2026. This is the recruiting-board publication date, not a verified first employer publication or the date of completed infrastructure.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/blue-origin-2026-08-terawave-ams-cosimulation-methodology-hiring/" }, { "id": "onsemi-2026-power-management-ams-methodology-hiring", "when": { "start": "2026-08-20", "precision": "day" }, "kind": "organizational", "companies": [ "onsemi" ], "people": [], "headline": "onsemi seeks product-level AMS ownership and methodology development for power-management ICs", "fact": "onsemi posted a Principal AMS Verification Engineer role for new power-management products including DC-DC PMIC and point-of-load devices, multiphase controllers, DrMOS, AC-DC converters, LED and SiC drivers, switches, and eFuses. The role covers complete product verification ownership, behavioral-model requirements, SystemVerilog real, Verilog-AMS and Verilog-A models, configurable testbenches, checkers and coverage, and work in the methodology team to streamline AMS development and integration flows. This is a hiring mandate, not a claim that the methods are deployed across every product.", "sources": [ { "title": "onsemi Careers: Principal AMS Verification Engineer (2506068)", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2506068", "checkedAt": "2026-08-31", "summary": "The official onsemi Oracle recruiting record exposes an August 20, 2026 posting timestamp and describes full-product power-management AMS ownership, real/VAMS/Verilog-A modeling, configurable verification, coverage, and methodology development.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/onsemi-2026-power-management-ams-methodology-hiring/" }, { "id": "samsung-2026-ams-verification-hiring", "when": { "start": "2026-08-20", "precision": "day" }, "kind": "organizational", "companies": [ "samsung" ], "people": [], "headline": "Samsung AMS verification posting seeks converter and LDO modeling experience", "fact": "Samsung posted Bengaluru AMS Verification Engineer role R119757. Under Roles and Responsibilities, the advertisement seeks behavioral-modeling experience for switching converters and LDOs using SV, Verilog, Verilog-AMS or Verilog-A, real-model creation and validation, verification planning and environment development, PSL/SV assertions, scripting and automation. Prior power-management IP and SoC verification is desirable. This describes requested experience for a hiring role, not completed modeling or verification results; the posting does not name UVM.", "sources": [ { "title": "Samsung Careers: AMS Verification Engineer", "url": "https://sec.wd3.myworkdayjobs.com/Samsung_Careers/job/SSIR-Goldstone-Bangalore-India/AMS-Verification-Engineer_R119757", "checkedAt": "2026-11-08", "summary": "The official Workday job data retains startDate August 20, 2026. Its Roles and Responsibilities list the named modeling and assertion experience and desirable prior power-management IP/SoC verification. UVM is not present; the requirements do not establish completed deployment.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2026-ams-verification-hiring/" }, { "id": "skyworks-2026-08-agentic-ams-platform-hiring", "when": { "start": "2026-08-20", "precision": "day" }, "kind": "organizational", "companies": [ "skyworks" ], "people": [], "headline": "Skyworks posts agentic AMS platform roles with verification-data integration and evaluation", "fact": "Skyworks listed a Cedar Rapids AI/software-workflow co-op on August 20 and a central automation role on August 24 for an agentic AMS design/verification platform. The latter assigns encoding analog/RF practice into tool-connected flows and engineering distributed simulation/verification data; Verilog-A/SV-RNM model creation and validation are desired experience. September 24 Irvine co-op 78496 assigns agent tool use, retrieval and evaluation against real testbenches, logs, waveforms and coverage to support mixed-signal debug and closure. These platform-development advertisements do not establish deployment or a shared team across roles.", "sources": [ { "title": "Skyworks Careers: AI Automation & Software Developer Co-op (Winter/Spring 2027), requisition 78222", "url": "https://careers.skyworksinc.com/job/IC-Analog-Mixed-Signal-Verification-Co-op-%28WinterSpring-2027%29/78222-en_US/", "checkedAt": "2026-10-25", "summary": "Official posting start date is August 20, 2026; the work term is January–June 2027. The current title and duties concern AI/software workflow development, with HDL and behavioral modeling as desired background; the URL retains an older title.", "status": "available", "archiveUrl": null }, { "title": "Sr. Design Automation Engineer", "url": "https://careers.skyworksinc.com/job/Sr_-Design-Automation-Engineer/77976-en_US/", "checkedAt": "2026-10-25", "summary": "Official August 24 role 77976 describes a central team, encoding analog/RF circuit practice into agent-connected flows, distributed engineering data, and desired experience creating/verifying Verilog-A and SV-RNM models. Rechecked October 25; requirements are not measured platform results.", "status": "available", "archiveUrl": null }, { "title": "Skyworks Careers: Agentic Mixed Signal Verification Platform Winter/Spring Co-Op, requisition 78496", "url": "https://careers.skyworksinc.com/job/Agentic-Mixed-Signal-Verification-Platform-WinterSpring-Co-Op-%28Jan-June-%2727%29/78496-en_US/", "checkedAt": "2026-10-25", "summary": "Official September 24 role 78496 remains available. It assigns agent evaluation against real verification artifacts and quality reporting; January-June 2027 is the proposed work term. It does not establish a shared platform/team with the other postings.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/skyworks-2026-08-agentic-ams-platform-hiring/" }, { "id": "renesas-2026-08-automotive-pmic-verification-leadership-hiring", "when": { "start": "2026-08-19", "precision": "day" }, "kind": "organizational", "companies": [ "renesas" ], "people": [], "headline": "Renesas posts senior verification roles for automotive PMIC RNM/AMS environments", "fact": "Renesas posted related Senior Principal roles for Automotive PMIC verification, covering RNM/AMS model integration, RTL-to-GLS correlation, PVT analysis, switched-mode regulators/LDOs, cross-team handoffs and methodology leadership. The Chandler role also assigns evaluation of emerging verification technologies and AI-based solutions. A related Staff description requires PMIC RNM/AMS environment architecture and Verilog/SystemVerilog proficiency. These grouped requirements include exploratory AI evaluation, not proof of AI-generated models, deployed tools or measured benefits; the original August 19 Event date is retained.", "sources": [ { "title": "Senior Principal Verification Engineer — Chandler", "url": "https://jobs.renesas.com/job/senior-principal-verification-engineer-in-chandler-arizona-united-states-jid-6707", "checkedAt": "2026-10-15", "summary": "Official Renesas requisition 20032032_2026-08-19 for Automotive PMIC verification leadership, RNM/AMS environment architecture, GLS correlation, PVT, ATE/Silicon Validation handoffs, mentoring, and methodology improvement. Rechecked October 15: the methodology responsibility explicitly includes evaluating emerging verification technologies and AI-based solutions; this is exploratory evaluation rather than a disclosed deployment.", "status": "available", "archiveUrl": null }, { "title": "Senior Principal Design Verification Engineer — Plano", "url": "https://jobs.renesas.com/job/senior-principal-design-verification-engineer-in-plano-texas-united-states-jid-6789", "checkedAt": "2026-09-28", "summary": "Official Renesas requisition 20032030_2026-08-19 repeats the Automotive PMIC RNM/AMS and cross-domain verification mandate and states that the role drives verification strategy across multiple product platforms.", "status": "available", "archiveUrl": null }, { "title": "Renesas Careers: Staff Verification Engineer", "url": "https://api.smartrecruiters.com/v1/companies/RenesasElectronics/postings/744000150387479", "checkedAt": "2026-10-06", "summary": "The official public posting describes automotive PMIC RNM/AMS model integration and Verilog/SystemVerilog proficiency. It currently links to posting 744000152788539; requisition/reposting metadata is not substituted for the existing Event’s date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2026-08-automotive-pmic-verification-leadership-hiring/" }, { "id": "amd-2026-08-pmic-rnm-soc-verification-hiring", "when": { "start": "2026-08-18", "precision": "day" }, "kind": "organizational", "companies": [ "amd" ], "people": [], "headline": "AMD posts a PMIC verification role linking analog-macro RNM, full-SoC tests, and silicon correlation", "fact": "AMD posted a Rochester ASIC Design Verification Engineer role to own verification strategy and coverage closure for mixed-signal power-management IP. Responsibilities include full-SoC SystemVerilog/UVM tests, firmware/RTL co-simulation, analog-macro RNM bring-up and correlation with analog behavior, and relating post-silicon behavior to pre-silicon tests. Preferred experience names wreal, nettype real, and Verilog-AMS.", "sources": [ { "title": "AMD Careers: ASIC Design Verification Engineer (90455)", "url": "https://careers.amd.com/careers-home/jobs/90455", "checkedAt": "2026-09-09", "summary": "The official AMD posting identifies Rochester, the PMIC/full-SoC verification mandate, RNM model fidelity and analog correlation, firmware co-simulation, and silicon correlation. Its structured posting metadata dates publication to August 18, 2026.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/amd-2026-08-pmic-rnm-soc-verification-hiring/" }, { "id": "nvidia-2026-08-cell-modeling-verification-hiring", "when": { "start": "2026-08-14", "precision": "day" }, "kind": "organizational", "companies": [ "nvidia" ], "people": [], "headline": "NVIDIA posts a mixed-signal cell modeling and verification role", "fact": "On August 14, 2026, NVIDIA posted a role to develop behavioral models and verification environments for custom mixed-signal cells used across NVIDIA products. The listing names Verilog, SystemVerilog, Perl, and Python, and covers cells including PLLs and high-speed interconnects, emulation and prototyping, and library- and chip-level integration.", "sources": [ { "title": "Senior Cell Modeling and Verification Engineer", "url": "https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Cell-Modeling-and-Verification-Engineer_JR2015659", "checkedAt": "2026-08-30", "summary": "Official NVIDIA role for behavioral modeling and verification of custom mixed-signal cells, including PLL and high-speed-interconnect applications.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nvidia-2026-08-cell-modeling-verification-hiring/" }, { "id": "siemens-eda-2026-08-mixed-signal-visualizer-boundary-debug", "when": { "start": "2026-08-12", "precision": "day" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [ "neel-natekar" ], "headline": "Siemens describes mixed-signal boundary debugging with MS Visualizer", "fact": "Siemens published a technical overview of Symphony Pro's Mixed-Signal Visualizer for AMS verification. It describes linked hierarchy, netlist, source, and variable views; generated schematics for checking connectivity and port mapping; and paired analog/digital signal representations for inspecting A2D/D2A conversion and boundary elements.", "sources": [ { "title": "Siemens overview of AMS debugging with Mixed-Signal Visualizer", "url": "https://blogs.sw.siemens.com/cicv/2026/08/12/from-complexity-to-clarity-simplifying-ams-verification-with-mixed-signal-visualizer/", "checkedAt": "2026-10-19", "summary": "Siemens authors describe mixed-hierarchy navigation, automatic schematics, and analog/digital boundary inspection in an August 12, 2026 article. The byline names Neel Natekar and Luong Nguyen.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2026-08-mixed-signal-visualizer-boundary-debug/" }, { "id": "credo-2026-08-pll-mixed-signal-verification", "when": { "start": "2026-08-10", "precision": "day" }, "kind": "technical", "companies": [ "credo" ], "people": [], "headline": "Credo presents mixed-signal PLL verification and CTLE BER analysis for a TSMC 2 nm design", "fact": "SNUG Taiwan 2026 proceedings list a Credo presentation by Yenlin Lee and Sung En Wang titled “Time-effective Mixed-Signal PLL Verifications with RTVS Cosim and CTLE BER Analysis with Matlab for TSMC 2nm Design.” Synopsys names it a Best Presentation Award winner. The public record establishes the stated mixed-signal PLL/co-simulation and MATLAB CTLE BER-analysis scope for a TSMC 2 nm design; it does not expose the gated presentation’s measured runtime, correlation, or sign-off results.", "sources": [ { "title": "SNUG Taiwan 2026 proceedings", "url": "https://www.synopsys.com/community/snug/snug-taiwan/location-proceedings-2026.html", "checkedAt": "2026-09-21", "summary": "Synopsys lists the Credo presentation by Yenlin Lee and Sung En Wang under Analog Mixed Signal Design and identifies it as a Best Presentation Award winner.", "status": "available", "archiveUrl": null }, { "title": "SNUG Taiwan 2026 Call for Content portal", "url": "https://my.reviewr.com/s2/site/snug_taiwan2026", "checkedAt": "2026-09-21", "summary": "The official SNUG Taiwan portal states that the conference was held at the Sheraton Hsinchu Hotel on August 10, 2026.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/credo-2026-08-pll-mixed-signal-verification/" }, { "id": "analog-devices-2026-08-data-converter-ams-verification-hiring", "when": { "start": "2026-08-04", "precision": "day" }, "kind": "organizational", "companies": [ "analog-devices" ], "people": [], "headline": "ADI lists AMS model-verification roles spanning data converters, fidelity and reusable testbenches", "fact": "ADI posted Wilmington Advanced Data-converter Group role R263851 on August 4 for analog circuit/system models, mixed-signal SoC connectivity/functional verification and usage-scenario testbenches, requesting SystemVerilog RNM, Verilog-AMS or SystemC. Related Austin/Durham Senior AMS Design Verification role R266818, dated October 13, assigns reusable SystemVerilog/UVM/RNM architecture, behavioral-model validation and fidelity/performance tradeoffs, requirements-traceable coverage, calibration/power-mode checks and regression/triage infrastructure. The later role is grouped with this existing AMS model-verification hiring milestone; a shared team is not established. Neither description assigns AI/ML modeling.", "sources": [ { "title": "Analog Devices Careers: Mixed Signal Design Verification Engineer (R263851)", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/US-MA-Wilmington/Mixed-Signal-Design-Verification-Engineer_R263851", "checkedAt": "2026-10-06", "summary": "Official employer page and public job data confirm the data-converter SoC modeling mandate. JobPosting datePosted and job-data startDate both identify August 4, 2026.", "status": "available", "archiveUrl": null }, { "title": "ADI Careers: Senior Analog/Mixed-Signal Design Verification Engineer (R266818)", "url": "https://analogdevices.wd1.myworkdayjobs.com/en-US/External/job/Senior-Engineer--Digital-Verification_R266818", "checkedAt": "2026-10-25", "summary": "Official public Workday jobPostingInfo gives startDate October 13, 2026 and R266818. The full description explicitly assigns behavioral-model validation, fidelity/performance tradeoffs, traceable coverage and reusable AMS verification architecture.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2026-08-data-converter-ams-verification-hiring/" }, { "id": "ayar-labs-2026-rnm-model-lifecycle-hiring", "when": { "start": "2026-08", "end": "2026-09", "precision": "month" }, "kind": "organizational", "companies": [ "ayar-labs" ], "people": [], "headline": "Ayar Labs lists roles spanning RNM construction, schematic correlation, sign-off, and full-chip integration", "fact": "Ayar Labs listed related Bengaluru analog/mixed-signal modeling and verification roles. Their descriptions call for capturing significant first- and second-order circuit effects in SystemVerilog RNM, comparing models with schematics, signing off models, and integrating them into full-chip digital verification. The senior staff role adds model ownership through the product lifecycle. The postings name UVM and Verilog-AMS and include wreal/EEnet and optical simulation tools among preferred experience.", "sources": [ { "title": "Ayar Labs: Sr. Staff Engineer, Analog/Mixed Signal Modelling and Verification (696)", "url": "https://recruitingbypaycor.com/career/JobIntroduction.action?clientId=8a7883c66a3387ef016a468ba9d104e6&id=8a7887a1a064211201a06813499e744c", "checkedAt": "2026-09-09", "summary": "The official Ayar Labs ATS description specifies schematic-derived RNM, model comparison, sign-off, full-chip integration, lifecycle ownership, and preferred wreal/EEnet and optical-tool experience. It exposes no absolute posting date.", "status": "available", "archiveUrl": null }, { "title": "Ayar Labs senior engineer listing — Insight Partners portfolio jobs", "url": "https://jobs.insightpartners.com/companies/ayar-labs/jobs/91490870-sr-engineer-analog-mixed-signal-modelling-and-verification", "checkedAt": "2026-09-09", "summary": "The investor portfolio listing dates senior engineer role 693 to August 28, 2026, and preserves its RNM construction, schematic comparison, sign-off, and full-chip integration responsibilities.", "status": "available", "archiveUrl": null }, { "title": "Ayar Labs senior staff listing — Playground Global portfolio jobs", "url": "https://careers.playground.global/companies/ayar-labs/jobs/92215361-sr-staff-engineer-analog-mixed-signal-modelling-and-verification", "checkedAt": "2026-09-09", "summary": "The investor portfolio listing dates senior staff role 696 to September 4, 2026. Together with the August senior engineer listing, it supports an August–September cluster; these are public listing dates, not independently established original ATS publication dates.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ayar-labs-2026-rnm-model-lifecycle-hiring/" }, { "id": "analog-port-2026-07-chiplet-mixed-signal-verification", "when": { "start": "2026-07-29", "precision": "day" }, "kind": "technical", "companies": [ "analog-port", "siemens-eda" ], "people": [ "neel-natekar" ], "headline": "Analog Port and Siemens report a UVM-based chiplet mixed-signal verification flow", "fact": "At DAC 2026, Analog Port and Siemens EDA authors described a top-down mixed-signal verification methodology for a 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface. The flow extends a UVM-based digital verification environment into the mixed-signal domain, using SPICE simulation for critical analog blocks and high-performance digital simulation for the broader system. The authors report up to 26x memory savings and more than 3x performance gain for the presented RX and TX simulations; these are case-specific presentation results.", "sources": [ { "title": "Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification", "url": "https://63dac.conference-program.com/presentation/?id=ENGPOST278&sess=sess296", "checkedAt": "2026-10-19", "summary": "The official DAC 2026 record identifies the Analog Port and Siemens authors, July 29 presentation, UVM-based top-down methodology, selective SPICE/digital partitioning, 32 Gbps 16-TX/16-RX interface, and reported up-to-26x memory and greater-than-3x performance results. Neel Natekar is listed among the Siemens authors.", "status": "available", "archiveUrl": null }, { "title": "How Siemens Symphony Pro enabled AnalogPort to verify complex chip interfaces", "url": "https://resources.sw.siemens.com/en-US/white-paper-how-siemens-symphony-pro-enabled-analogport-to-verify-complex-chip-designs/", "checkedAt": "2026-09-25", "summary": "Siemens' vendor-authored white paper separately documents the presented methodology's UVM extension, SPICE treatment of critical analog blocks, digital simulation of the broader system, and the 32 Gbps 16-transmit/16-receive full-duplex interface.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-port-2026-07-chiplet-mixed-signal-verification/" }, { "id": "ekepower-2026-07-variation-aware-mixed-signal-verification", "when": { "start": "2026-07-29", "precision": "day" }, "kind": "technical", "companies": [ "ekepower", "siemens-eda" ], "people": [], "headline": "EKEPOWER and Siemens describe variation-aware verification and trimming for mixed-signal printing ICs", "fact": "A DAC 2026 abstract by EKEPOWER's Irving Hsu and Siemens' Lih-Jen Hou describes a Solido flow combining transient, RF, and mixed-signal analysis for printing ICs with motor/printhead drivers, timing references, and RF sensors. The authors report up to 7.6x speed improvement over their conventional methods and an AI-assisted trimming flow that reduces top-level voltage variation; these are presentation-reported results.", "sources": [ { "title": "DAC 2026 abstract on EKEPOWER variation-aware analog/mixed-signal optimization", "url": "https://63dac.conference-program.com/presentation/?id=ENGPOST268&sess=sess296", "checkedAt": "2026-09-07", "summary": "Official abstract identifies both authors and affiliations, July 29 poster scheduling, analysis modes, and reported speed and trimming results.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ekepower-2026-07-variation-aware-mixed-signal-verification/" }, { "id": "microchip-2026-selective-spice-digital-top-verification", "when": { "start": "2026-07-29", "precision": "day" }, "kind": "technical", "companies": [ "microchip", "siemens-eda" ], "people": [ "neel-natekar" ], "headline": "Microchip and Siemens authors report selective-SPICE digital-top verification with RTL and UPF", "fact": "A Microchip and Siemens DAC 2026 presentation reports a digital-on-top mixed-signal flow combining selected SPICE blocks with RTL and UPF power intent. The presentation describes AI-accelerated Solido analysis and reports more than 22× acceleration for the presented case. This preserves the customer/vendor presentation modality and does not imply the result applies to every Microchip design.", "sources": [ { "title": "Comprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification Methodology", "url": "https://63dac.conference-program.com/presentation/?id=ENGPOST281&sess=sess296", "checkedAt": "2026-10-19", "summary": "The official DAC 2026 record identifies Microchip and Siemens authors and describes the selective-SPICE, RTL, UPF, and AI-accelerated flow with a reported greater-than-22× result. Neel Natekar is explicitly listed as a Siemens coauthor.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2026-selective-spice-digital-top-verification/" }, { "id": "microchip-2026-07-full-chip-pvt-calibration-ams", "when": { "start": "2026-07-28", "precision": "day" }, "kind": "technical", "companies": [ "microchip", "siemens-eda" ], "people": [ "neel-natekar" ], "headline": "Microchip and Siemens report full-chip AMS verification for FPGA I/O PVT calibration", "fact": "At DAC 2026, Microchip and Siemens authors described full-chip analog mixed-signal verification of FPGA I/O PVT calibration spanning distributed I/O banks. The presented calibration combines a SAR-based digital block with analog circuitry that manages reference currents and voltages. The authors report that Siemens Symphony Pro reduced simulation time by about 3x and memory usage by about 2-3x while supporting regression across multiple I/O standards and extreme PVT conditions; these are presentation-reported results for the described case.", "sources": [ { "title": "An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Systems", "url": "https://63dac.conference-program.com/presentation/?id=ENGPOST276&sess=sess295", "checkedAt": "2026-10-19", "summary": "The official DAC 2026 record identifies the Microchip and Siemens authors, July 28 presentation, SAR/digital-plus-analog PVT-calibration architecture, full-chip verification scope, and reported approximately-3x simulation-time and 2-3x memory improvements. Neel Natekar is listed among the Siemens authors.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2026-07-full-chip-pvt-calibration-ams/" }, { "id": "texas-instruments-2026-07-ana-modelgen-generation-validation", "when": { "start": "2026-07-28", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "aadhar-sharma" ], "headline": "TI authors present ANA-MODELGEN for analog behavioral-model generation and SPICE-based validation", "fact": "The DAC 2026 program lists ANA-MODELGEN by Aadhar Sharma and Texas Instruments coauthors. Its abstract describes automated generation of analog IP behavioral models and validation testbenches, with equivalence checks against SPICE references. The authors report use in production SoC verification flows and improvements in execution speed and functional coverage. This records the presented method and author-reported application; the public abstract does not establish use of an LLM or disclose independently verified results. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.", "sources": [ { "title": "DAC 2026: ANA-MODELGEN", "url": "https://63dac.conference-program.com/presentation/?id=ENGPRES367&sess=sess272", "checkedAt": "2026-10-19", "summary": "Official program identifies the TI authors including Aadhar Sharma, July 28 presentation, behavioral-model/testbench generation and SPICE equivalence scope. No AI mechanism is specified in the abstract.", "status": "available", "archiveUrl": null }, { "title": "Aadhar Sharma: DAC 2026 reflections on ANA-MODELGEN and UVM-MS", "url": "https://www.linkedin.com/posts/aadharsharma218_dac2026-designautomation-semiconductors-activity-7497927138050895872-jnpv", "checkedAt": "2026-10-25", "summary": "The presenter's own public post, dated August 25, 2026 at 08:05 UTC, names both presentations and attributes them to his TI teams. It supports personal participation and stated follow-up plans; its publication date is distinct from the July presentations.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2026-07-ana-modelgen-generation-validation/" }, { "id": "maieutic-2026-07-generative-analog-topology-presentation", "when": { "start": "2026-07-27", "precision": "day" }, "kind": "technical", "companies": [ "maieutic-semiconductors" ], "people": [ "rakesh-kumar" ], "headline": "Maieutic announces Rakesh Kumar presentation on generative analog circuits beyond parameter tuning", "fact": "Maieutic's company account announces Rakesh Kumar's DAC 2026 presentation, GenAI Powered Circuits: Beyond Parametric Tuning, in a Silicon Integration Initiative session. The company's public materials position its analog-design work around generative circuit design rather than parameter adjustment alone. The date is the explicitly advertised July 27 session, not the relative age of the LinkedIn post. This records the named presentation and advertised scope, not independently verified design results or a customer deployment.", "sources": [ { "title": "Maieutic company announcement: Rakesh Kumar at DAC 2026", "url": "https://www.linkedin.com/company/maieutic-semiconductors", "checkedAt": "2026-10-19", "summary": "The company post explicitly gives July 27, 2026, room 104C, noon, the presenter and the GenAI circuit-design topic.", "status": "available", "archiveUrl": null }, { "title": "UTEC: Maieutic founders and analog-design scope", "url": "https://www.ut-ec.co.jp/english/our_companies/maieutic-semiconductors-pvt-ltd/", "checkedAt": "2026-10-19", "summary": "The investor identifies Rakesh Kumar as cofounder/CPO and explains the team's analog IC design experience and AI-assisted design mission; prior Renesas employment is not treated as a technology-transfer claim.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/maieutic-2026-07-generative-analog-topology-presentation/" }, { "id": "nvidia-2026-agentic-custom-ip-verification-hiring", "when": { "start": "2026-07-27", "precision": "day" }, "kind": "organizational", "companies": [ "nvidia" ], "people": [], "headline": "NVIDIA job posting seeks agentic-AI workflows for custom-IP verification", "fact": "An NVIDIA Senior ASIC Design Verification Engineer posting for its Circuit Solutions Group describes custom IP spanning clocking, voltage regulation, and silicon correlation. It asks the role to help develop and deploy agentic-AI frameworks for stimulus generation, regression triage, debug, and root-cause analysis, while listing real-number modeling of low-level digital or mixed-signal designs and VCS-XA co-simulation as differentiating experience. This is evidence of a public hiring mandate, not proof of the capability or measured effect of a completed framework.", "sources": [ { "title": "NVIDIA Careers: Senior ASIC Design Verification Engineer (JR2017926)", "url": "https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Senior-ASIC-Design-Verification-Engineer_JR2017926", "checkedAt": "2026-09-02", "summary": "The official NVIDIA posting describes the custom-IP scope, agentic-AI verification responsibilities, and RNM and mixed-signal co-simulation experience.", "status": "available", "archiveUrl": null }, { "title": "NVIDIA Workday record for JR2017926", "url": "https://nvidia.wd5.myworkdayjobs.com/wday/cxs/nvidia/NVIDIAExternalCareerSite/job/Senior-ASIC-Design-Verification-Engineer_JR2017926", "checkedAt": "2026-09-02", "summary": "The first-party Workday record supplies the absolute July 27, 2026 start date for the requisition and the same job description.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nvidia-2026-agentic-custom-ip-verification-hiring/" }, { "id": "texas-instruments-2026-uvm-ms-analog-vip", "when": { "start": "2026-07-27", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "aadhar-sharma" ], "headline": "TI authors report using UVM-MS analog VIP for mixed-signal verification", "fact": "A Texas Instruments DAC 2026 presentation reports a UVM-MS-based flow in which verification components drive and monitor analog signals without traditional connect modules. The authors describe reusable analog VIP and report improvements in simulation runtime and verification coverage for the presented use cases. The record supports this reported TI application, not universal adoption across the company. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.", "sources": [ { "title": "UVM-MS: A Novel Approach to Mixed-Signal IP Verification", "url": "https://63dac.conference-program.com/presentation/?id=ENGPRES340&sess=sess265", "checkedAt": "2026-08-31", "summary": "The official DAC 2026 record identifies the TI authors and describes analog VIP, removal of connect-module dependence, and reported runtime and coverage improvements.", "status": "available", "archiveUrl": null }, { "title": "Aadhar Sharma: DAC 2026 reflections on ANA-MODELGEN and UVM-MS", "url": "https://www.linkedin.com/posts/aadharsharma218_dac2026-designautomation-semiconductors-activity-7497927138050895872-jnpv", "checkedAt": "2026-10-25", "summary": "The presenter's own public post, dated August 25, 2026 at 08:05 UTC, names both presentations and attributes them to his TI teams. It supports personal participation and stated follow-up plans; its publication date is distinct from the July presentations.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2026-uvm-ms-analog-vip/" }, { "id": "ibm-2026-07-hrl-topo-analog-topology-synthesis", "when": { "start": "2026-07-26", "precision": "day" }, "kind": "technical", "companies": [ "ibm" ], "people": [ "xin-zhang" ], "headline": "IBM authors publish HRL-Topo for LLM-guided hierarchical analog circuit topology synthesis", "fact": "IBM Research lists HRL-Topo by Prashanth Vijayaraghavan, Xin Zhang and coauthors as a DAC 2026 publication dated July 26. The work combines language-model circuit guidance with hierarchical reinforcement learning to construct analog circuit topologies and evaluate them through simulation. This records a topology-synthesis research publication, rather than fixed-topology sizing alone or deployment across IBM design teams. The date is IBM's publication-record date, not a separately verified presentation time.", "sources": [ { "title": "IBM Research: HRL-Topo", "url": "https://research.ibm.com/publications/hrl-topo-hierarchical-reinforcement-learning-with-large-language-models-for-analog-circuit-topology-synthesis", "checkedAt": "2026-10-19", "summary": "IBM lists July 26, 2026, DAC 2026, the author group including Xin Zhang, and the hierarchical reinforcement-learning/LLM topology-synthesis scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ibm-2026-07-hrl-topo-analog-topology-synthesis/" }, { "id": "bosch-sensortec-2026-agentic-ai-mixed-signal-verification-hiring", "when": { "start": "2026-07-24", "precision": "day" }, "kind": "organizational", "companies": [ "bosch-sensortec" ], "people": [], "headline": "Bosch Sensortec posts a PhD role applying agentic AI to ASIC and mixed-signal verification", "fact": "Bosch Sensortec posted a Dresden PhD role to develop agentic-AI software for accelerating ASIC design, verification, and test. The posting explicitly includes mixed-signal verification and testing and names coverage-driven regression optimization, AMS testbench generation, and closed-loop test-case evaluation and optimization among its example use cases.", "sources": [ { "title": "PhD - Agentic AI for ASIC Development Acceleration", "url": "https://jobs.bosch.de/job/PhD-Agentic-AI-for-ASIC-Development-Acceleration-Dresden?id=6b2db6df-8415-4cb0-9438-28710b9032f8", "checkedAt": "2026-08-30", "summary": "Official Bosch posting REF292240Q, published July 24, 2026 by Bosch Sensortec GmbH in Dresden, covering agentic-AI work across ASIC design, verification, test, mixed-signal verification, regressions, AMS testbenches, and test-case optimization.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-sensortec-2026-agentic-ai-mixed-signal-verification-hiring/" }, { "id": "cadence-2026-07-virastack-analog-design-agent-presentation", "when": { "start": "2026-07-17", "precision": "day" }, "kind": "technical", "companies": [ "cadence" ], "people": [ "tadokoro-haruko" ], "headline": "Cadence Japan presents ViraStack agents for analog/custom circuit design and verification workflows", "fact": "CadenceLIVE Japan lists a presentation by 田所 晴子 of Cadence Japan on ViraStack, a natural-language-operated AI agent for analog and custom design in Virtuoso. Its advertised scope spans circuit design, layout and verification rather than layout automation alone. The speaker biography identifies application-engineering work on Virtuoso ADE and Spectre since 2005. This records the scheduled technical presentation and public abstract, not customer adoption, measured productivity gains or responsibility for developing the product.", "sources": [ { "title": "CadenceLIVE Japan 2026", "url": "https://www.cadence.com/en_US/home/company/events/industry-events/cadencelive-silicon-valley-20261.html", "checkedAt": "2026-10-19", "summary": "Cadence dates its Tokyo event to July 17, 2026.", "status": "available", "archiveUrl": null }, { "title": "Session B-3: ViraStack for custom design", "url": "https://cadencelivejapan2026.smktg.jp/public/session/view/19", "checkedAt": "2026-10-19", "summary": "The official session page names the speaker, Cadence Japan affiliation and circuit/layout/verification agent scope. The Person retains the name as published.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2026-07-virastack-analog-design-agent-presentation/" }, { "id": "apple-2026-07-wireless-dms-hiring", "when": { "start": "2026-07-16", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple lists multiple Wireless Silicon Digital Mixed-Signal Modeling roles", "fact": "Apple listed Wireless Silicon Digital Mixed-Signal Modeling Engineer roles in the San Francisco Bay Area and Beaverton on July 16. Related October 16 role 200689643 assigns accurate, simulation-efficient SystemVerilog models for analog/RF blocks, reusable monitors/checkers, test-plan execution, debug and flow automation. It explicitly develops emulation-ready models and requests understanding of synthesis-ready mixed-signal model requirements, with SystemC/C++ and high-level synthesis among preferred skills. These related postings are grouped with the existing wireless modeling mandate; the later role does not establish successful emulator execution or change the July Event date.", "sources": [ { "title": "Digital Mixed-Signal Modeling Engineer — San Francisco Bay Area", "url": "https://jobs.apple.com/en-us/details/200672770-3401/digital-mixed-signal-modeling-engineer", "checkedAt": "2026-08-30", "summary": "Official Apple role dated July 16, 2026, for wireless-silicon SystemVerilog modeling and verification in the San Francisco Bay Area.", "status": "available", "archiveUrl": null }, { "title": "Digital Mixed-Signal Modeling Engineer — Beaverton", "url": "https://jobs.apple.com/en-us/details/200672770-0505/digital-mixed-signal-modeling-engineer", "checkedAt": "2026-08-30", "summary": "Official Apple location variant dated July 16, 2026, for the same wireless-silicon modeling and verification work in Beaverton.", "status": "available", "archiveUrl": null }, { "title": "Apple Careers: Wireless Digital Mixed-Signal Modeling Engineer (200689643)", "url": "https://jobs.apple.com/en-us/details/200689643-0505/digital-mixed-signal-modeling-engineer", "checkedAt": "2026-10-25", "summary": "Official posting displays October 16, 2026. Assigned work includes SystemVerilog analog/RF models and emulation readiness; synthesis-ready requirements, SystemC and high-level synthesis appear in qualifications. The Beaverton/Sunnyvale variants are not separate Events.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-07-wireless-dms-hiring/" }, { "id": "ibm-2026-07-explore-language-model-topology-search", "when": { "start": "2026-07-15", "precision": "day" }, "kind": "technical", "companies": [ "ibm" ], "people": [ "xin-zhang" ], "headline": "IBM and Duke researchers publish EXPLORE for language-model-guided analog topology exploration", "fact": "Guanglei Zhou, Xin Zhang and coauthors publish EXPLORE, combining an autoregressive circuit language model with Monte Carlo tree search and simulation feedback to explore analog circuit topologies. The manuscript lists Duke University, MIT-IBM Watson AI Lab and IBM Research affiliations. It concerns generating circuit structure as well as optimizing candidate designs. July 15 is the initial arXiv publication date; later MLCAD presentation is supporting context for the same research, not evidence of production adoption.", "sources": [ { "title": "EXPLORE: arXiv publication record", "url": "https://arxiv.org/abs/2607.13416", "checkedAt": "2026-10-19", "summary": "The record dates the first public arXiv version to July 15, 2026.", "status": "available", "archiveUrl": null }, { "title": "EXPLORE v1: author affiliations and methodology", "url": "https://arxiv.org/html/2607.13416v1", "checkedAt": "2026-10-19", "summary": "The manuscript identifies the university and IBM affiliations, including Xin Zhang at IBM, and describes language-model/MCTS topology generation with simulator feedback.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ibm-2026-07-explore-language-model-topology-search/" }, { "id": "broadcom-2026-07-dms-modeling-hiring", "when": { "start": "2026-07-07", "precision": "day" }, "kind": "organizational", "companies": [ "broadcom" ], "people": [], "headline": "Broadcom lists DMS modeling for touch, wireless-power, health-sensing, and satellite analog front ends", "fact": "Broadcom posted an Analog/Mixed Signal Verilog Modeling Design Engineer role for touch-controller, wireless-power, health-sensing, and satellite analog front ends. The description calls for SystemVerilog DMS models, UDT/UDR nettypes including wreal or EEnet, model-versus-schematic verification, and experience using Cursor or chipAgents to generate analog SystemVerilog models and testbenches.", "sources": [ { "title": "Analog/Mixed Signal Verilog Modeling Design Engineer", "url": "https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-CA-Irvine-Alton-Parkway-Bldg-1/Analog-Mixed-Signal-Verilog-Modeling-Design-Engineer_R024672", "checkedAt": "2026-08-30", "summary": "Official Broadcom role dated July 7, 2026, for product-scoped DMS modeling, nettypes, schematic correlation, and AI-assisted generation experience.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/broadcom-2026-07-dms-modeling-hiring/" }, { "id": "semtech-2026-07-signal-integrity-modeling-trainee", "when": { "start": "2026-07-06", "precision": "day" }, "kind": "organizational", "companies": [ "semtech" ], "people": [], "headline": "Semtech Signal Integrity trainee role includes analog behavioral modeling and mixed-level simulation", "fact": "Semtech posted Digital Design Verification Trainee REQ3462 in Aguascalientes for the Signal Integrity Product Business Unit’s Digital Design group, which develops mixed-signal ICs for data communications and video broadcast. The description allocates 50% of responsibilities to constrained-random digital verification, 10% to analog behavioral modeling and analog/digital mixed-level simulation, and 10% to verification-methodology improvement. SystemVerilog is preferred in the qualifications. This is a training and hiring mandate, not evidence of completed deployment or a specified RNM implementation.", "sources": [ { "title": "Semtech Careers: Digital Design Verification Trainee (REQ3462)", "url": "https://semtech.wd1.myworkdayjobs.com/SemtechCareers/job/MEX---Aguascalientes/Digital-Design-Verification-Trainee_REQ3462", "checkedAt": "2026-11-07", "summary": "Official public Workday startDate is July 6, 2026. Full duties identify the Signal Integrity Product team and responsibility percentages; applications remained enabled at this check. This is a different business unit from the existing sensing-IC hiring record.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/semtech-2026-07-signal-integrity-modeling-trainee/" }, { "id": "skyworks-2026-07-central-ams-verification-hiring", "when": { "start": "2026-07-06", "precision": "day" }, "kind": "organizational", "companies": [ "skyworks" ], "people": [ "prabal-bhattacharya" ], "headline": "Skyworks posts a director role to found a Central AMS Verification team", "fact": "Skyworks posted a Director, Central AMS Verification role to found and lead a central AMS SoC verification team. The mandate includes an enterprise-wide UVM/RNM/AMS platform, common model and verification-IP libraries, coverage, assertions, convergence, and automation. Prabal K. Bhattacharya's public profile identifies him as leading global EDA at Skyworks, and his public post says he is hiring for this role to raise AMS verification across the company. These records establish the leadership connection and hiring mandate, not that the team is staffed or the platform deployed.", "sources": [ { "title": "Director, Central AMS Verification", "url": "https://careers.skyworksinc.com/job/Director%2C-Central-AMS-Verification/76940-en_US/", "checkedAt": "2026-08-30", "summary": "Official Skyworks role posted July 6, 2026, with a mandate to found a central team and build common AMS verification infrastructure.", "status": "available", "archiveUrl": null }, { "title": "Prabal Bhattacharya public professional profile", "url": "https://www.linkedin.com/in/prabalbhattacharya", "checkedAt": "2026-08-30", "summary": "Public professional profile identifying Bhattacharya as the leader of global EDA at Skyworks.", "status": "available", "archiveUrl": null }, { "title": "Prabal Bhattacharya public hiring post", "url": "https://www.linkedin.com/posts/prabalbhattacharya_i-am-hiring-for-this-verification-leadership-activity-7444950236587945984--IZT", "checkedAt": "2026-08-30", "summary": "Public post in which Bhattacharya says he is hiring for the verification leadership role and describes its company-wide AMS verification purpose.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/skyworks-2026-07-central-ams-verification-hiring/" }, { "id": "infineon-2026-generative-ai-rnm-verification-keynote", "when": { "start": "2026-07-02", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "joachim-glas" ], "headline": "Infineon keynote describes generative-AI real-number-model creation within an AI-based verification methodology", "fact": "A SMACD 2026 keynote by an Infineon principal engineer describes industrial experience connecting AI assistants, retrieval-augmented knowledge systems, and EDA tools through APIs, along with a current focus on an AI-based verification methodology. Its concrete example generates SystemVerilog real-number models from schematics, specifications, or other source models while emphasizing domain knowledge, guardrails, compliance, and human review. This Event records the scope described by the keynote, not a measured deployment result.", "sources": [ { "title": "AI Transformation in IC Development: An Industrial Perspective on Reshaping Verification Methodology in the Generative-AI Era", "url": "https://smacd-conference.org/keynote.html", "checkedAt": "2026-10-19", "status": "unavailable", "summary": "The original URL returned 404 on October 19, 2026. The September 23 archive was reviewed on October 19 and explicitly identifies Joachim Glas, Infineon and the AI-assistant, RAG, EDA-API, guardrail, human-review and SystemVerilog RNM example scope.", "archiveUrl": "https://web.archive.org/web/20260923040441/https://smacd-conference.org/keynote.html" }, { "title": "SMACD 2026 programme", "url": "https://smacd-conference.org/programme_extended2.html", "checkedAt": "2026-10-19", "status": "unavailable", "summary": "The original URL returned 404 on October 19, 2026. The September 23 archive was reviewed on October 19: the Day 4 Thursday, July 2 table places Joachim Glas and AI Transformation in IC Development in the 09:00 keynote row of the SMACD 2026 programme.", "archiveUrl": "https://web.archive.org/web/20260923040441/https://smacd-conference.org/programme_extended2.html" } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-generative-ai-rnm-verification-keynote/" }, { "id": "amd-2026-pll-ams-verification-lead-hiring", "when": { "start": "2026-06-30", "precision": "day" }, "kind": "organizational", "companies": [ "amd" ], "people": [], "headline": "AMD job posting seeks leadership for complex PLL mixed-signal verification", "fact": "AMD posted a role for a silicon design engineer that describes leading verification of complex PLLs across RTL, gate-level, and analog/mixed-signal simulation, with UVM, coverage, co-simulation, planning, and technical leadership responsibilities. This is evidence of a public hiring mandate, not proof that every requested flow was already deployed across AMD.", "sources": [ { "title": "AMD Careers requisition 87581", "url": "https://careers.amd.com/careers-home/jobs/87581", "checkedAt": "2026-08-31", "summary": "Official AMD requisition 87581, posted June 30, 2026, describes the complex-PLL verification leadership scope across RTL, gate-level, AMS, UVM, coverage, and co-simulation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/amd-2026-pll-ams-verification-lead-hiring/" }, { "id": "broadcom-2026-clocking-msv-rnm-hiring", "when": { "start": "2026-06-30", "precision": "day" }, "kind": "organizational", "companies": [ "broadcom" ], "people": [], "headline": "Broadcom clocking-design role calls for MSV and RNM strategies in PLL, FLL, and DLL verification", "fact": "Broadcom posted a Digital Mixed-Signal Lead role for the digital control infrastructure of PLL, FLL, and DLL clocking subsystems. The description assigns partnership with verification teams to drive mixed-signal-verification and real-number-modeling strategies for high-coverage loop simulations and also names full-chip CDC and RDC sign-off for the clocking network. This is evidence of a public hiring mandate, not proof that the listed verification strategies were already deployed across Broadcom.", "sources": [ { "title": "Broadcom Careers: Mixed Signal Digital Design Lead (R026040)", "url": "https://broadcom.wd1.myworkdayjobs.com/en-US/External_Career/job/USA-Colorado-Fort-Collins-4380-Ziegler-Road/Mixed-Signal-Digital-Design-Lead_R026040", "checkedAt": "2026-08-31", "summary": "The official Broadcom Workday record exposes a June 30, 2026 start date and describes the PLL/FLL/DLL digital-control, MSV/RNM verification-partnership, and full-chip CDC/RDC scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/broadcom-2026-clocking-msv-rnm-hiring/" }, { "id": "micron-2026-ddr-onfi-uvm-ams-verification-hiring", "when": { "start": "2026-06-30", "precision": "day" }, "kind": "organizational", "companies": [ "micron" ], "people": [], "headline": "Micron posts UVM-AMS and RNM verification role for DDR and ONFI PHY", "fact": "Micron posted a Staff Engineer role for a high-speed DDR and ONFI PHY team whose description calls for reusable SystemVerilog/UVM environments with mixed-signal simulators and fast behavioral models using SystemVerilog EEnet or wreal, or Verilog-AMS, in place of SPICE subcircuits. It also covers full-chip gate-level, power-aware, and mixed-signal co-simulation plus model validation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.", "sources": [ { "title": "Micron Careers: Staff engineer, ASIC AMS Verification", "url": "https://careers.micron.com/careers/job/42799659?domain=micron.com", "checkedAt": "2026-08-31", "summary": "The official Micron page's JobPosting data exposes a June 30, 2026 date and describes the DDR/ONFI PHY, UVM-AMS, EEnet/wreal or Verilog-AMS model, full-chip co-simulation, power-aware, and model-validation scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/micron-2026-ddr-onfi-uvm-ams-verification-hiring/" }, { "id": "texas-instruments-2026-06-hvp-ams-verification-hiring", "when": { "start": "2026-06-22", "precision": "day" }, "kind": "organizational", "companies": [ "texas-instruments" ], "people": [], "headline": "Texas Instruments posts AMS verification role for a Bengaluru high-voltage power team", "fact": "Texas Instruments posted an AMS verification engineer/lead role describing a high-voltage power team being built in Bengaluru for AC/DC controllers, isolated DC/DC converters, and GaN-integrated power stages. The role calls for SV-RNM and Verilog-AMS wreal/electrical models, system-level AMS tests, SystemVerilog/UVM testbenches, assertions and coverage, methodology development, and participation in post-silicon validation and debug.", "sources": [ { "title": "Texas Instruments: AMS Design Verification Lead — Mixed-Signal SoC / GaN", "url": "https://in.linkedin.com/jobs/view/ams-design-verification-lead-%E2%80%93-mixed-signal-soc-gan-at-texas-instruments-4414157409", "checkedAt": "2026-09-09", "summary": "The company-attributed LinkedIn posting names a TI recruiter and describes the Bengaluru HVP hiring mandate. Its structured datePosted is June 22, 2026; this dates the public posting, rather than conflicting dates on secondary copies or completion of the described team build-out.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2026-06-hvp-ams-verification-hiring/" }, { "id": "asfigo-2026-06-uvm-ms-customer-use-feedback", "when": { "start": "2026-06-17", "precision": "day" }, "kind": "organizational", "companies": [ "asfigo" ], "people": [ "srinivasan-venkataramanan", "evgeny-vlasov" ], "headline": "Srinivasan Venkataramanan reports UVM-MS customer work and shares working-group feedback discussions", "fact": "In a June 17 public post, Srinivasan Venkataramanan reported that AsFigo's Ajeetha Kumari was deploying UVM-MS v1.0 on customer projects and had reviewed DVCon India papers from users of the standard. He shared a digest attributed to UVM-AMS working-group chair Evgeny Vlasov describing feedback from companies using v1.0 and proposals for driver/proxy/core communication while defining possible v2.0 scope. These are attributed reports of customer work and standards discussions, without named customers, independently verified adoption results or an issued v2.0 release. June 17 dates Venkataramanan's post, not the underlying meetings.", "sources": [ { "title": "Srinivasan Venkataramanan: UVM-MS customer use and shared WG digest", "url": "https://www.linkedin.com/posts/svenka3_genai-uvm-dvcon-activity-7473135252048257024-eUqk", "checkedAt": "2026-10-25", "summary": "Public SocialMediaPosting metadata gives June 17, 2026 at 22:11 UTC. The author's own text reports AsFigo customer deployment and paper review; sharedContent attributes the feedback/proxy-layer digest to Evgeny Vlasov. Exact customer and committee-meeting dates are not established.", "status": "available", "archiveUrl": null }, { "title": "Accellera: UVM-MS Working Group", "url": "https://www.accellera.org/activities/working-groups/uvm-ms", "checkedAt": "2026-10-25", "summary": "Current official working-group page identifies Evgeny Vlasov as chair and describes driving/monitoring mixed-signal nets and extending verification components. It provides standards context, not proof of customer adoption or a v2.0 release.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/asfigo-2026-06-uvm-ms-customer-use-feedback/" }, { "id": "renesas-2026-06-digital-power-verification-architect", "when": { "start": "2026-06-16", "precision": "day" }, "kind": "organizational", "companies": [ "renesas" ], "people": [], "headline": "Renesas posts an architect role to define cross-domain verification for digital power products", "fact": "Renesas posted a Mixed Signal Verification Architect role to define scalable verification and validation for digital power products used in AI, datacenter, and high-performance computing applications. The mandate connects requirements, behavioral models, RTL, AMS simulation, emulation, bench validation, and silicon through measurable criteria, coverage expectations, correlation methods, automation, and reusable evidence.", "sources": [ { "title": "Mixed Signal Verification Architect", "url": "https://jobs.renesas.com/job/mixed-signal-verification-architect-in-austin-texas-united-states-jid-6393", "checkedAt": "2026-08-30", "summary": "Official expired Renesas requisition dated June 16, 2026, whose mandate was to define cross-domain digital-power verification and correlation methods.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2026-06-digital-power-verification-architect/" }, { "id": "microchip-2026-06-chiplet-ams-verification-hiring", "when": { "start": "2026-06-14", "precision": "day" }, "kind": "organizational", "companies": [ "microchip" ], "people": [], "headline": "Microchip lists system-level AMS verification across full-chip and chiplet boundaries", "fact": "Microchip posted a Technical Staff Engineer role for system-level AMS verification and power and signal integrity on SoCs and chiplet platforms. The description covers subsystem, full-chip, and cross-chiplet AMS and SPICE simulation, mature-node analog integrated with advanced-node digital, multi-voltage domains, methodology development, silicon bring-up, and simulation-to-silicon correlation.", "sources": [ { "title": "Technical Staff Engineer - AMS Verification", "url": "https://microchiphr.wd5.myworkdayjobs.com/en-US/External/job/AZ---Chandler/Technical-Staff-Engineer---AMS-Verification_R1531-26", "checkedAt": "2026-08-30", "summary": "Official Microchip Workday role dated June 14, 2026, for system-level AMS, full-chip and chiplet simulation, methodology, and silicon correlation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2026-06-chiplet-ams-verification-hiring/" }, { "id": "analog-devices-2026-ai-ml-ams-verification-hiring", "when": { "start": "2026-06-11", "precision": "day" }, "kind": "organizational", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices job posting seeks AI/ML methods for mixed-signal design verification", "fact": "ADI’s June 11 Staff Design Verification Engineer posting R263414 assigns AI/ML failure clustering, regression triage, anomaly detection and coverage optimization in mixed-signal/UVM verification. Related Shanghai role R262078, dated July 14, explicitly includes analog behavioral models and digital/analog interface checks, with Verilog-AMS/RNM familiarity. Graduate role R266482, dated September 22, assigns agentic AI to testbench development, debug and regression analysis with engineer review; Shanghai preferences include AMS co-simulation. These related hiring mandates are grouped without assuming a shared team or demonstrated production deployment.", "sources": [ { "title": "Analog Devices Careers: Staff Design Verification Engineer (AI/ML)", "url": "https://analogdevices.wd1.myworkdayjobs.com/en-US/External/job/Staff-Design-Verification-Engineer--AI-ML-_R263414", "checkedAt": "2026-08-31", "summary": "Official ADI requisition R263414, posted June 11, 2026, lists the mixed-signal/UVM scope and AI/ML applications in failure clustering, regression triage, anomaly detection, and coverage optimization.", "status": "available", "archiveUrl": null }, { "title": "ADI Careers: Staff Design Verification Engineer, Shanghai (R262078)", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/China-Shanghai-Puxi/Staff-Engineer--Digital-Design-Engineering_R262078", "checkedAt": "2026-10-15", "summary": "Official public Workday startDate is July 14, 2026. Full duties explicitly connect AI/ML verification analysis with analog behavioral modeling and analog/digital interface checks; Verilog-AMS/RNM appears in qualifications.", "status": "available", "archiveUrl": null }, { "title": "ADI Careers: Digital Verification Engineer, Shanghai (R266482)", "url": "https://analogdevices.wd1.myworkdayjobs.com/External/job/China-Shanghai-Pudong-ZuChongzhi/Digital-Verification-Engineer_R266482", "checkedAt": "2026-10-15", "summary": "Official public Workday startDate is September 22, 2026. Graduate MDV duties assign agentic AI testbench/debug/regression work with reviewed outputs; Shanghai-specific preferred experience includes AMS co-simulation. Neither later source changes the original June Event date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2026-ai-ml-ams-verification-hiring/" }, { "id": "monolithic-power-systems-2026-06-ams-verification-internship", "when": { "start": "2026-06-11", "precision": "day" }, "kind": "organizational", "companies": [ "monolithic-power-systems" ], "people": [], "headline": "MPS student listing assigns chip-top AMS verification and RNM, wreal and schematic models", "fact": "An Arizona State University recruiting listing dated June 11 advertised an MPS Analog Mixed Signal Verification Intern role in San Jose for a 20–24 week Summer/Fall 2026 placement. The employer description assigns chip-top verification planning and AMS simulation for full-custom precision analog signal-chain ASICs, behavioral models ranging from RNM and logical models to Verilog-AMS electrical/wreal and schematic models, register and trim-mode debug with analog schematics and post-layout RTL, and regression and infrastructure support. June 11 is the university listing's recruitment date; the listed application deadline was June 19.", "sources": [ { "title": "Arizona State University Career Services: MPS Analog Mixed Signal Verification Intern", "url": "https://career.eoss.asu.edu/jobs/monolithic-power-systems-inc-analog-mixed-signal-verification-intern/", "checkedAt": "2026-10-06", "status": "unavailable", "summary": "University recruiting record begins June 11, 2026 and expires June 19. Its indexed employer description explicitly assigns chip-top AMS, RNM/wreal/schematic models and regression work. The direct page is no longer available when checked.", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/monolithic-power-systems-2026-06-ams-verification-internship/" }, { "id": "marvell-2026-serdes-ams-ip-verification-hiring", "when": { "start": "2026-06-09", "precision": "day" }, "kind": "organizational", "companies": [ "marvell" ], "people": [], "headline": "Marvell AMS IP role spans reusable verification for SerDes, DDR, die-to-die, and PHY interfaces", "fact": "Marvell posted a Senior Staff Engineer role in its Central Engineering AMS IP team with end-to-end verification ownership for SerDes and other AMS or mixed-signal IP across 5 nm, 3 nm, and 2 nm nodes. The mandate covers calibration, link training, power modes, analog-digital and firmware interactions, coverage, regression, sign-off, and reusable automation using SystemVerilog and UVM. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.", "sources": [ { "title": "Marvell Careers: Senior Staff Engineer — AMS IP Verification (2601686)", "url": "https://marvell.wd1.myworkdayjobs.com/en-US/MarvellCareers/job/Bangalore/Senior-Staff-Engineer---Design-Verification---SerDes-PHY-AMS_2601686", "checkedAt": "2026-08-31", "summary": "The official Marvell Workday record exposes a June 9, 2026 start date and describes the Central Engineering team's interface scope, end-to-end verification ownership, UVM methodology, sign-off, and reusable infrastructure responsibilities.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/marvell-2026-serdes-ams-ip-verification-hiring/" }, { "id": "ubitium-2026-06-rnm-veloce-pll-emulation", "when": { "start": "2026-06-09", "precision": "day" }, "kind": "technical", "companies": [ "ubitium", "siemens-eda" ], "people": [], "headline": "Siemens publishes a Ubitium PLL case connecting RNM to Veloce Strato emulation", "fact": "Siemens published a Ubitium case-study abstract describing real-number models of analog blocks integrated into Veloce Strato hardware emulation. Its PLL example operates in a RISC-V system environment, and the abstract reports acceleration while retaining correlation with traditional simulation.", "sources": [ { "title": "Ubitium: Mixed-signal design and verification using RNM and Veloce", "url": "https://resources.sw.siemens.com/en-US/video-ubitium-mixed-signal-design-and-verification-using-rnm-and-veloce/", "checkedAt": "2026-09-09", "summary": "The public abstract describes the RNM, PLL, RISC-V, Veloce Strato, and simulation-correlation scope. Siemens' public resource index dates publication to June 9, 2026. The recording requires registration; this Event uses only the public abstract.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ubitium-2026-06-rnm-veloce-pll-emulation/" }, { "id": "skyworks-2026-06-ams-verification-hiring", "when": { "start": "2026-06-08", "precision": "day" }, "kind": "organizational", "companies": [ "skyworks" ], "people": [], "headline": "Skyworks lists related AMS verification roles from behavioral models through full-chip simulation", "fact": "Skyworks posted related AMS verification roles whose descriptions cover Verilog-A and SystemVerilog RNM behavioral models, model-versus-schematic equivalence, AMS and DMS verification, and block-to-full-chip RFIC work. The roles name PLLs, ADCs, DACs, LDOs, oscillators, power-aware verification, and flow automation, while emphasizing scalable, reusable, and portable environments.", "sources": [ { "title": "Staff AMS Verification Engineer", "url": "https://careers.skyworksinc.com/job/Sr_-Electrical-Engineer/77439-en_US/", "checkedAt": "2026-08-30", "summary": "Official Skyworks role posted June 8, 2026, covering Verilog-A, SV-RNM, equivalence, AMS/DMS, and RFIC block-to-full-chip verification.", "status": "available", "archiveUrl": null }, { "title": "Audio AMS Verification Engineer", "url": "https://careers.skyworksinc.com/job/Sr_-Electrical-Engineer/77675-en_US/", "checkedAt": "2026-08-30", "summary": "Official Skyworks role posted June 24, 2026, adding PLL, converter, LDO, power-aware, chip-level performance, and automation scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/skyworks-2026-06-ams-verification-hiring/" }, { "id": "synopsys-2026-serdes-ams-verification-manager-hiring", "when": { "start": "2026-06-08", "precision": "day" }, "kind": "organizational", "companies": [ "synopsys" ], "people": [], "headline": "Synopsys job posting seeks a senior manager for distributed SERDES mixed-signal verification", "fact": "A Synopsys careers posting seeks a senior verification manager to lead and grow distributed SERDES PHY mixed-signal verification work spanning UVM, co-simulation, emulation, and laboratory correlation. It also asks the manager to drive AI-assisted regression triage where measurable. This is evidence of a public leadership and hiring mandate, not proof that all listed methods or AI-assisted triage were already deployed.", "sources": [ { "title": "Synopsys Careers: Senior Verification Manager, SERDES PHY", "url": "https://careers.synopsys.com/job/mississauga/senior-verification-manager-serdes-phy/44408/96193430288", "checkedAt": "2026-08-31", "summary": "The official Synopsys posting, dated June 8, 2026, describes the distributed SERDES mixed-signal verification leadership scope and the requested, measurability-bounded AI-assisted regression-triage responsibility.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/synopsys-2026-serdes-ams-verification-manager-hiring/" }, { "id": "chipagents-2026-agentic-ams-behavioral-modeling", "when": { "start": "2026-06-05", "precision": "day" }, "kind": "technical", "companies": [ "chipagents" ], "people": [ "sidharth-kannan" ], "headline": "ChipAgents describes an agentic workflow for generating and validating AMS behavioral models", "fact": "A ChipAgents-authored technical post describes an agentic workflow for PLL, ADC, DAC, and LDO behavioral models: create reference data with a full-physics simulator, generate Verilog-A models, validate waveforms and operating behavior against golden simulation data using the same or reserved stimulus sets, detect gaps, select new simulations through active learning, retrain, and integrate models through Verilog-A, SystemVerilog, or C++ DPI interfaces. The post says the company's platform produces tests, comparison results, and plots for human review. This records the company's own platform description, not independent evidence of model accuracy or customer deployment.", "sources": [ { "title": "Why Chip Engineers Should Care About AI-Created Behavioral Models", "url": "https://chipagents.ai/blogs/ai-created-behavioral-models", "checkedAt": "2026-10-19", "summary": "The June 5, 2026 article identifies Sidharth Kannan as author. Step 4 allows the same or reserved stimulus sets; it does not require an independent validation set. This is the developer/vendor's account, not customer-confirmed adoption.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/chipagents-2026-agentic-ams-behavioral-modeling/" }, { "id": "infineon-2026-06-systemc-ams-virtual-testing-thesis", "when": { "start": "2026-06-04", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Doctoral thesis reports SystemC-AMS virtual testing for gate-driver test hardware", "fact": "Davide Turossi reported defending his doctoral thesis at the University of Milano-Bicocca on June 4, 2026 and explicitly thanked Infineon for hosting and supporting the research. The university abstract describes a SystemC-AMS/COSIDE framework modeling automatic test equipment, devices under test and probe-card circuitry. Its gate-driver cases address over-current protection and output peak-current measurement, comparing virtual test solutions with measurements on manufactured hardware. This records the thesis and acknowledged research support, not company-wide adoption.", "sources": [ { "title": "University record: SystemC-AMS virtual testing dissertation", "url": "https://boa.unimib.it/handle/10281/610004", "checkedAt": "2026-10-06", "status": "unavailable", "summary": "The official indexed record identifies the 2026 dissertation, June 4 defense and SystemC-AMS/COSIDE gate-driver case studies. Direct retrieval was access-limited; the public abstract was checked, but the thesis PDF was not reviewed.", "archiveUrl": null }, { "title": "Davide Turossi: doctoral defense and research acknowledgments", "url": "https://it.linkedin.com/in/davide-turossi-514a09205", "checkedAt": "2026-10-06", "summary": "The author explicitly reports the June 4, 2026 defense and Infineon hospitality/support during the PhD. Current employment is not used to infer the research affiliation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-06-systemc-ams-virtual-testing-thesis/" }, { "id": "marvell-2026-05-cordoba-analog-modeling-internship", "when": { "start": "2026-05-22", "precision": "day" }, "kind": "organizational", "companies": [ "marvell" ], "people": [], "headline": "Marvell Córdoba internship pairs SystemVerilog analog models with SPICE comparison and co-simulation", "fact": "Marvell posted Analog Modeling & Testing Engineer Intern 2602068 for its Central Engineering team at the Córdoba design center. The training mandate includes modeling analog circuits in SystemVerilog, comparing SV and SPICE simulations, running digital/analog co-simulation and improving analog-IC design flows, alongside Python/firmware-based circuit testing. These are advertised assignments rather than a report of completed work. The named Córdoba modeling program is distinct from the Singapore amplifier-verification internship.", "sources": [ { "title": "Marvell Careers: Analog Modeling & Testing Engineer Intern (2602068)", "url": "https://marvell.wd1.myworkdayjobs.com/MarvellCareers/job/Cordoba-Argentina/Analog-Modeling---Testing-Engineer-Intern_2602068", "checkedAt": "2026-11-07", "summary": "Official public Workday startDate is May 22, 2026. The full description names Central Engineering in Córdoba and the SV-to-SPICE comparison, co-simulation and flow-improvement training; applications remained enabled at this check.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/marvell-2026-05-cordoba-analog-modeling-internship/" }, { "id": "texas-instruments-2026-05-ai-analog-circuit-design-hiring", "when": { "start": "2026-05-21", "precision": "day" }, "kind": "organizational", "companies": [ "texas-instruments" ], "people": [], "headline": "TI advertises AI/ML-assisted analog circuit creation and design-methodology adoption", "fact": "Texas Instruments posted Bengaluru role 25010677, Analog Circuit Design Engineer – AI/ML methodology. It assigns analog IC definition, modeling and schematic design, plus use of AI/ML-enabled tools and flows to accelerate development and create novel circuits. The engineer is also to drive adoption of those methods across product teams. Example circuit experience includes references, ADCs/DACs, amplifiers, oscillators and power-management blocks. This is a hiring mandate beyond device sizing alone; it does not demonstrate autonomous topology generation or measured design improvements.", "sources": [ { "title": "TI Careers: Analog Circuit Design Engineer – AI/ML methodology (25010677)", "url": "https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/ja/sites/CX/job/25010677/", "checkedAt": "2026-10-15", "summary": "Official employer ATS description and Job Info display May 21, 2026. The duties explicitly connect AI/ML-enabled flows with novel circuit creation and product-team adoption; no topology-generation algorithm or achieved benefit is disclosed.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2026-05-ai-analog-circuit-design-hiring/" }, { "id": "onsemi-2026-treo-analog-ip-mixed-signal-verification-hiring", "when": { "start": "2026-05-19", "precision": "day" }, "kind": "organizational", "companies": [ "onsemi" ], "people": [], "headline": "onsemi Treo role calls for reusable digital-on-top verification of analog power and clock IP", "fact": "onsemi posted a Mixed-Signal Verification Engineer role for analog IP integrated into digital-on-top SoCs on its 65 nm Treo BCD platform. The position owns SystemVerilog and UVM testbenches, real-number and Verilog-A/AMS behavioral models for PLLs, LDOs, DC-DC converters, and oscillators, executable plans, assertions, coverage and checkers, regression debug, and model-validation strategies. This is evidence of a public hiring mandate, not proof of completed verification outcomes. A Spring 2027 internship listing dated September 29 describes possible assignments in Treo digital-on-top verification, assertions, coverage, behavioral models and exploration of AI-assisted design.", "sources": [ { "title": "onsemi Careers: Mixed-Signal Verification Engineer – Analog IP (2505537)", "url": "https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/job/2505537", "checkedAt": "2026-08-31", "summary": "The official onsemi Oracle recruiting record exposes a May 19, 2026 posting timestamp and describes Treo digital-on-top AMS verification, reusable UVM environments, RNM/VAMS models, assertions, coverage, and model validation.", "status": "available", "archiveUrl": null }, { "title": "onsemi: Spring 2027 IC design internship — ASU recruitment listing", "url": "https://career.eoss.asu.edu/jobs/onsemi-spring-2027-ic-design-engineer-intern/", "checkedAt": "2026-10-05", "summary": "Employer-supplied university listing dated September 29, 2026 describes Treo and possible student assignments in digital-on-top analog-IP verification, SystemVerilog assertions/coverage, Verilog-A/AMS models and AI-assisted design exploration. These are possible assignments, not duties promised to every intern.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/onsemi-2026-treo-analog-ip-mixed-signal-verification-hiring/" }, { "id": "apple-2026-05-wireless-mixed-signal-verification-hiring", "when": { "start": "2026-05-13", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple lists wireless Mixed-Signal Verification Engineer roles", "fact": "Apple listed Mixed-Signal Verification Engineer roles for RF and mixed-signal blocks and interfaces in wireless SoCs. The descriptions assign verification planning, mixed-signal and digital UVM testbenches, reusable monitors and checkers, coverage closure, automation, and methodology improvement using AI; real-numbered SystemVerilog behavioral-model experience appears as a preferred qualification.", "sources": [ { "title": "Mixed-Signal Verification Engineer", "url": "https://jobs.apple.com/en-us/details/200662891-3401/mixed-signal-verification-engineer", "checkedAt": "2026-09-02", "summary": "Official Apple posting dated May 13, 2026, describing RF and mixed-signal SoC verification with UVM, monitors and checkers, coverage, automation, AI-assisted methodology improvement, and preferred real-number modeling experience.", "status": "available", "archiveUrl": null }, { "title": "Mixed-Signal Verification Engineer — early-career variant", "url": "https://jobs.apple.com/en-us/details/200662889-3401/mixed-signal-verification-engineer", "checkedAt": "2026-09-02", "summary": "Official Apple role variant dated May 13, 2026, expressing the same wireless mixed-signal verification mandate at a different experience level.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-05-wireless-mixed-signal-verification-hiring/" }, { "id": "hmt-2026-05-requirement-driven-mixed-signal-verification", "when": { "start": "2026-05-12", "precision": "day" }, "kind": "technical", "companies": [ "hmt-microelectronic" ], "people": [], "headline": "HMT presents a Polarion-to-SystemVerilog workflow for mixed-signal ASIC verification", "fact": "At User2User Europe 2026, HMT Microelectronic's Vincent Camus presented a requirement-driven mixed-signal ASIC verification workflow. The public session description connects Siemens Polarion requirements to VIP-based SystemVerilog testbenches, SVA assertions and chip-level mixed-signal validation. It describes automated pass/fail reporting and centralized model hierarchy, simulation configuration and version management. Simulator independence and functional-safety compliance are claims in the presentation description; no third-party certification or quantified verification result was established.", "sources": [ { "title": "Siemens User2User Europe 2026: HMT session description", "url": "https://event-new.sw.siemens.com/_widgets/10372/agenda/235901/large/session_popup/63836633/3/eng/false/94351", "checkedAt": "2026-10-09", "summary": "Official session detail, linked from the Functional Design & Verification catalog, identifies HMT, Vincent Camus and May 12, 2026. Its public description specifies Polarion, SystemVerilog, SVA, mixed-signal validation and traceability.", "status": "available", "archiveUrl": null }, { "title": "Verification Academy: Automated requirement-driven, SystemVerilog-based verification workflow for mixed-signal ASICs", "url": "https://verificationacademy.com/topics/functional-safety/automated-requirement-driven-systemverilog-based-verification-workflow-for-mixed-signal-asics/", "checkedAt": "2026-10-09", "summary": "Public abstract corroborates the workflow and affiliation. The member-only recording was not reviewed; the Event date comes from the official conference session, not the page update.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/hmt-2026-05-requirement-driven-mixed-signal-verification/" }, { "id": "cadence-2026-05-verilog-a-circuit-modeling-tutorials", "when": { "start": "2026-05-06", "precision": "day" }, "kind": "technical", "companies": [ "cadence" ], "people": [], "headline": "Cadence blog introduces Verilog-A tutorials for analog circuit blocks", "fact": "A Cadence official blog introduces Verilog-A teaching material for circuit and functional blocks, including ADCs, DACs, operational transconductance amplifiers, phase detectors and signal sources. It discusses Laplace- and Z-transform modeling for transfer functions. The Event dates the blog introduction, not the initial publication of every linked video, and is limited to circuit-block modeling rather than the device examples also mentioned in the article.", "sources": [ { "title": "Analog circuit modeling using Verilog-A in Virtuoso", "url": "https://community.cadence.com/cadence_blogs_8/b/cic/posts/analog_2d00_circuit_2d00_modeling_2d00_verilog_2d00_a_2d00_virtuoso", "checkedAt": "2026-10-06", "summary": "Official article dated May 6, 2026 introduces circuit-block tutorials and transfer-function models. Some linked teaching videos require customer access; their full contents and first publication dates were not verified.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2026-05-verilog-a-circuit-modeling-tutorials/" }, { "id": "cirrus-logic-2026-05-ams-modeling-verification-co-op", "when": { "start": "2026-05-02", "precision": "day" }, "kind": "organizational", "companies": [ "cirrus-logic" ], "people": [], "headline": "Cirrus Logic advertises a Fall co-op for SV-RNM, user-defined types and audio ASIC verification", "fact": "Cirrus Logic's company account advertised a Fall 2026 Mixed Signal Modeling & Verification Engineer co-op in Austin on May 2. The preserved job description assigns top-down SystemVerilog model development and validation, AMS/UVM verification planning for audio-processing ASICs, behavioral models using SV-RNM, SystemVerilog user-defined types and Verilog-AMS, schematic abstraction, and regression and flow support. The advertised student placement lasts 12–14 weeks. The Event date is the employer's public announcement, not the Fall work term or an inferred first posting date.", "sources": [ { "title": "Cirrus Logic: Fall 2026 Mixed Signal Modeling & Verification co-op announcement", "url": "https://www.linkedin.com/posts/cirrus-logic_hiring-activity-7456302537520971776-cUHQ", "checkedAt": "2026-10-06", "summary": "The employer's public announcement identifies the role and Austin location. Its JSON-LD datePublished is May 2, 2026 at 11:24 UTC.", "status": "available", "archiveUrl": null }, { "title": "Dice: Cirrus Logic Fall 2026 Co-Op - Mixed Signal Modeling & Verification Engineer", "url": "https://www.dice.com/job-detail/c88ff87a-5f0c-4e27-a386-73996aaa8979", "checkedAt": "2026-10-06", "status": "unavailable", "summary": "Indexed employer-description copy supplies the audio ASIC, AMS/UVM, SV-RNM/SV-UDT/Verilog-AMS, schematic-abstraction and regression duties. The direct page returns HTTP 410 when checked; this is a historical recruiting record.", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cirrus-logic-2026-05-ams-modeling-verification-co-op/" }, { "id": "infineon-2026-p1687-2-uvm-shift-left", "when": { "start": "2026-05", "precision": "month" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon retargets IEEE P1687.2 test descriptions into SystemVerilog UVM for automotive smart-power shift-left", "fact": "An Infineon Automotive Power paper at ETS 2026 describes retargeting IJTAG/IEEE P1687.2 test-case descriptions through a renderer and a pin-level time-stamp/value transport such as STIL into top-level SystemVerilog UVM testbenches for pre-silicon functional verification of automotive smart-power devices. Its SoC DUT combines digital RTL with analog behavioral models, while UVM-compatible agents apply external analog and supply stimuli. The paper illustrates replay of a measured noisy supply waveform and shows a charge-pump voltage (VDD CP) response to supply interruptions followed by an SPI diagnostic readout. These are paper-reported verification results, not measured silicon performance or evidence of wider adoption.", "sources": [ { "title": "Shift-Left by applying IEEE P1687.2 to SystemVerilog test-benches for Automotive Smart-Power devices", "url": "https://www.researchgate.net/publication/405440166_Shift-Left_by_applying_IEEE_P16872_to_SystemVerilog_test-benches_for_Automotive_Smart_Power_devices", "checkedAt": "2026-11-07", "summary": "Infineon Automotive Power paper: Section III describes digital RTL enriched by analog behavioral models and external analog/supply stimuli applied by UVM-compatible agents; Section II B/Figures 5–6 illustrates noisy-supply waveform replay, and Section V/Figure 8 shows the charge-pump voltage response to supply interruptions followed by an SPI diagnostic readout in the pre-silicon testbench.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2026-p1687-2-uvm-shift-left/" }, { "id": "apple-2026-04-pmu-dms", "when": { "start": "2026-04-23", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts a PMU Digital Mixed Signal Modeling role", "fact": "Apple posted PMU Digital Mixed Signal Modeling role 200659736, assigning SystemVerilog RNM, model-versus-schematic simulation, standalone validation, full-chip integration, reusable libraries, model accuracy metrics, regression and Python automation. The description states typical RNM closed-loop simulations exceed schematic speed by 100 times. Preferred experience includes LLM/AI-assisted coding for model or RTL development. This is a qualification signal, not an assigned AI model-generation workflow or independently verified speedup.", "sources": [ { "title": "Digital Mixed Signal Modeling Engineer", "url": "https://jobs.apple.com/en-us/details/200659736", "checkedAt": "2026-09-02", "status": "unavailable", "summary": "Official Apple PMU DMS job description listing RNM, validation, full-chip integration, regression, reuse, automation, correlation, and a stated typical speedup of more than 100 times for RNM-based closed-loop simulation.", "archiveUrl": null }, { "title": "Digital Mixed Signal Modeling Engineer — recovery copy", "url": "https://tryjeremy.com/jobs/apple-digital-mixed-signal-modeling-engineer-019dbbc8fba3", "checkedAt": "2026-09-02", "summary": "Recovery copy of Apple role 200659736 preserving the PMU scope, verification responsibilities, and stated typical speedup of more than 100 times for RNM-based closed-loop simulation.", "status": "available", "archiveUrl": null }, { "title": "Apple Careers: Digital Mixed Signal Modeling Engineer (200659736-0157)", "url": "https://jobs.apple.com/en-au/details/200659736-0157/digital-mixed-signal-modeling-engineer?team=HRDWR", "checkedAt": "2026-10-15", "summary": "Retained official indexed text displays April 23, 2026 and explicitly lists LLM/AI-assisted coding for model/RTL development among preferred qualifications. Direct regional pages may return a shell; this does not establish that the wording was newly added.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-04-pmu-dms/" }, { "id": "bosch-sensortec-2026-04-systemc-ams-solver-evaluation", "when": { "start": "2026-04-23", "precision": "day" }, "kind": "technical", "companies": [ "bosch-sensortec" ], "people": [ "alexandra-kuester" ], "headline": "Bosch Sensortec presents SystemC-AMS solver evaluation with MEMS and C2V models", "fact": "At SystemC Evolution Fika, Alexandra Küster of Bosch Sensortec presented an evaluation of solver efficiency in heterogeneous SystemC-AMS virtual prototypes. The slides compare PRECALC and SEGMENT approaches, adaptive time steps, feedback and discrete-event handling using MEMS and capacitance-to-voltage (C2V) models under repeated-shock conditions. This Event records the 2026 presentation, rather than the first publication of the underlying solver research.", "sources": [ { "title": "SystemC Evolution Fika: April 23, 2026", "url": "https://systemc.org/events/scef202604/", "checkedAt": "2026-10-06", "summary": "The official program identifies the April 23 presentation, Alexandra Küster and Bosch Sensortec.", "status": "available", "archiveUrl": null }, { "title": "Toward Fast Heterogeneous Virtual Prototypes: Increasing the Solver Efficiency in SystemC AMS", "url": "https://workspace.accellera.org/document/dl/14309", "checkedAt": "2026-10-06", "summary": "Presentation slides describe PRECALC/SEGMENT, adaptive time steps, feedback/discrete events and MEMS/C2V evaluation scenarios. The underlying cited paper is from 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-sensortec-2026-04-systemc-ams-solver-evaluation/" }, { "id": "nxp-2026-04-systemc-ams-standardization-regressions", "when": { "start": "2026-04-23", "precision": "day" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "martin-barnasconi" ], "headline": "NXP-affiliated Accellera chair reports SystemC-AMS revision and regression-test progress", "fact": "Martin Barnasconi, identified with NXP and as Accellera SystemC Technical Committee chair, presented the SystemC-AMS standardization status at SystemC Evolution Fika. The slides report preparation for the next IEEE 1666.1 revision and work toward a public regression-test repository. Accellera coordinates this standardization work; it is not an NXP product release. The presentation does not announce a newly issued standard or the first public regression suite: a 2023 presentation already links a regression-test tar archive.", "sources": [ { "title": "SystemC-AMS standardization status: April 2026", "url": "https://workspace.accellera.org/document/dl/14278", "checkedAt": "2026-10-06", "summary": "The status slides identify Barnasconi (NXP), next-revision preparation and ongoing work to make the regression suite available through a public repository.", "status": "available", "archiveUrl": null }, { "title": "SystemC Evolution Fika: April 23, 2026", "url": "https://systemc.org/events/scef202604/", "checkedAt": "2026-10-06", "summary": "The official program dates the standards-status presentation and identifies Barnasconi and his Accellera chair role.", "status": "available", "archiveUrl": null }, { "title": "SystemC-AMS standardization update: November 2023", "url": "https://workspace.accellera.org/document/dl/12193", "checkedAt": "2026-10-06", "summary": "The earlier presentation already lists a released regression suite with more than 700 tests and a public tar download; the 2026 work is not its first public availability.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-04-systemc-ams-standardization-regressions/" }, { "id": "apple-2026-pmu-ams-design-verification-team-hiring", "when": { "start": "2026-04-17", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [ "selcuk-talay" ], "headline": "Selcuk Talay publicly recruits for his Apple PMU AMS design-verification team", "fact": "Apple posted a PMU Analog & Mixed-Signal Design Verification role for Cupertino and Austin covering full-chip mixed-signal verification, analog/RTL co-simulation, verification planning, assertions, coverage, and sign-off. Selcuk Talay publicly shared the role and described it as hiring for \"my AMS design verification team,\" directly connecting him to the recruiting team.", "sources": [ { "title": "PMU Design Verification Engineer: Analog & Mixed Signal Engineer — Cupertino", "url": "https://jobs.apple.com/en-us/details/200658493-0836/pmu-design-verification-engineer-analog-mixed-signal-engineer", "checkedAt": "2026-08-30", "summary": "Official Apple role 200658493 posted April 17, 2026 for Cupertino, with full-chip mixed-signal verification, analog/RTL co-simulation, planning, assertions, coverage, sign-off, and tape-out responsibilities.", "status": "available", "archiveUrl": null }, { "title": "PMU Design Verification Engineer: Analog & Mixed Signal Engineer — Austin", "url": "https://jobs.apple.com/en-us/details/200658493-0157/pmu-design-verification-engineer-analog-mixed-signal-engineer", "checkedAt": "2026-08-30", "summary": "Official Austin location variant of Apple role 200658493, posted April 17, 2026 with the same PMU analog and mixed-signal verification responsibilities.", "status": "available", "archiveUrl": null }, { "title": "Selcuk Talay public Apple PMU AMS-DV hiring post", "url": "https://www.linkedin.com/posts/selcuk-talay-00556417_pmu-design-verification-engineer-analog-activity-7451732739050987520-3lUw", "checkedAt": "2026-08-30", "summary": "Talay's public post says he is hiring in Cupertino and Austin for his AMS design-verification team and links the Apple PMU Analog & Mixed Signal Engineer role.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-pmu-ams-design-verification-team-hiring/" }, { "id": "renesas-2026-04-pmic-ams-dms-hiring", "when": { "start": "2026-04-16", "precision": "day" }, "kind": "organizational", "companies": [ "renesas" ], "people": [], "headline": "Renesas lists AMS/DMS verification roles spanning power ICs, reusable models, UVM and correlation", "fact": "Renesas listed PMIC verification roles for battery chargers, switching regulators and analog power IP. The descriptions cover chip-level AMS and full-chip DMS, SystemVerilog RNM and Verilog-AMS models integrated with RTL and UVM, model correlation to specifications and schematics, coverage closure, sign-off and silicon bench correlation. A later Kodaira staff listing assigns reusable UVM environments, assertions, checkers and coverage, and requests RNM/Verilog-AMS modeling experience for bias networks, regulators, bandgaps, amplifiers, comparators, converters and other mixed-signal blocks. Its requisition carries August 27, while its page's JobPosting datePosted is September 17; it does not establish an August public-posting date.", "sources": [ { "title": "Senior Staff Mixed Signal Verification Engineer", "url": "https://jobs.renesas.com/job/senior-staff-mixed-signal-verification-engineer-in-chandler-arizona-united-states-jid-5987", "checkedAt": "2026-08-30", "summary": "Official Renesas requisition dated April 16, 2026, for PMIC AMS/DMS verification, RNM/VAMS modeling, coverage, sign-off, and schematic and bench correlation.", "status": "available", "archiveUrl": null }, { "title": "Staff AMS Verification Engineer", "url": "https://jobs.renesas.com/job/staff-ams-verification-engineer-in-bengaluru-ka-india-jid-4702", "checkedAt": "2026-08-30", "summary": "Official Renesas requisition dated April 28, 2026, for reusable UVM/RNM PMIC verification from blocks through full-chip and silicon correlation.", "status": "available", "archiveUrl": null }, { "title": "Renesas Careers: Verification Staff Engineer - Analog Mixed-Signal, Kodaira (20031926)", "url": "https://jobs.renesas.com/job/verification-staff-engineer-analog-mixed-signal-in-kodaira-japan-jid-6925", "checkedAt": "2026-10-06", "summary": "Official listing assigns UVM environments, checkers and coverage and requests RNM/Verilog-AMS block-modeling experience. Requisition 20031926_2026-08-27 and JobPosting datePosted 2026-09-17 are distinct date markers; this source extends the existing hiring milestone.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2026-04-pmic-ams-dms-hiring/" }, { "id": "apple-2026-04-ams-modeling-software-platform", "when": { "start": "2026-04-14", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts an Analog Mixed-Signal Modeling Software role", "fact": "Apple posted an Analog Mixed-Signal Modeling Software Engineer role whose description covers multi-simulator platforms, scientific-software and automation frameworks, custom model libraries, simulation frameworks, domain-specific languages, and web interfaces for AMS circuit design.", "sources": [ { "title": "Analog Mixed-Signal Modeling Software Engineer (m/f/d)", "url": "https://jobs.apple.com/en-us/details/200656891-1731/analog-mixed-signal-modeling-software-engineer-m-f-d", "checkedAt": "2026-08-30", "summary": "Official Apple role dated April 14, 2026, for AMS modeling tools, multi-simulator platforms, model libraries, frameworks, domain-specific languages, and designer-facing interfaces.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-04-ams-modeling-software-platform/" }, { "id": "cirrus-logic-2026-top-down-mixed-signal-verification", "when": { "start": "2026-03-31", "precision": "day" }, "kind": "technical", "companies": [ "cirrus-logic" ], "people": [ "gautham-sathyan" ], "headline": "Cirrus Logic engineer describes a top-down flow spanning SystemVerilog RNM, DMS, and chip-level AMS verification", "fact": "A TechWorks presentation by Cirrus Logic engineer Gautham Sathyan describes a top-down mixed-signal verification approach spanning early architectural modeling, analog/digital boundary definition, DMS bring-up, SystemVerilog real-number models for lower-level analog cells, and chip-level AMS simulation. His public event biography identifies him with Cirrus Logic's Newbury Mixed-Signal Modeling and Verification group.", "sources": [ { "title": "Designing the Future: Analogue Mixed Signal (AMS)", "url": "https://techworks.org.uk/event/designing-the-future-analogue-mixed-signal-ams/", "checkedAt": "2026-08-30", "summary": "TechWorks' March 31, 2026 event page lists Sathyan's top-down mixed-signal verification session and identifies his Cirrus Logic Newbury group, architectural-modeling, DMS, SystemVerilog RNM, and chip-level AMS responsibilities.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cirrus-logic-2026-top-down-mixed-signal-verification/" }, { "id": "ensilica-2026-03-beamforming-safety-asic-ams-verification", "when": { "start": "2026-03-31", "precision": "day" }, "kind": "technical", "companies": [ "ensilica" ], "people": [ "konstantinos-glaros" ], "headline": "EnSilica design lead presents AMS/DMS verification for beamforming arrays and safety-critical ASICs", "fact": "The DESN program lists Konstantinos Glaros, also introduced as Kostas Glaros, as EnSilica associate director of analogue IC design. His talk addresses AMS and DMS verification where multiple analog channels operate alongside complex digital signal processing, and traceable requirements compliance in industrial and automotive ASICs. This records a named technical presentation and its published scope; the public abstract does not identify a specific modeling language or quantified verification result.", "sources": [ { "title": "DESN: Designing the Future, Analogue Mixed Signal", "url": "https://desn.org.uk/event/designing-the-future-analogue-mixed-signal-ams/", "checkedAt": "2026-10-19", "summary": "The March 31, 2026 program and speaker abstract name Glaros and EnSilica and explicitly describe AMS/DMS verification of multichannel and safety-critical ASICs.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ensilica-2026-03-beamforming-safety-asic-ams-verification/" }, { "id": "ams-osram-2026-ams-dms-methodology-lead-hiring", "when": { "start": "2026-03-20", "precision": "day" }, "kind": "organizational", "companies": [ "ams-osram" ], "people": [], "headline": "ams OSRAM seeks a leader for distributed AMS/DMS verification methodology and model libraries", "fact": "ams OSRAM posted a Senior Principal Mixed-Signal Verification Engineer role to lead a distributed verification team and own an AMS/DMS methodology roadmap. The mandate covers reusable EEnet/UDN model libraries, DMS-to-Spectre correlation, SystemVerilog/UVM-MS environments, assertions, coverage, regression, sign-off criteria, and Python automation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed across the organization.", "sources": [ { "title": "Senior Principal Mixed-Signal Verification Engineer (d/m/f)", "url": "https://jobs.ams-osram.com/en/job/Senior-Principal-Mixed-Signal-Verification-Engineer-d_m_f-Premstaetten/22937", "checkedAt": "2026-08-31", "status": "unavailable", "summary": "The official ams OSRAM posting identifies job 22937, its March 20, 2026 posting date, distributed-team leadership, and the AMS/DMS modeling, verification, correlation, coverage, regression, sign-off, and automation mandate; the original now reports that the position is no longer available.", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ams-osram-2026-ams-dms-methodology-lead-hiring/" }, { "id": "synopsys-2026-03-photonic-verilog-a-model-generation", "when": { "start": "2026-03-11", "precision": "day" }, "kind": "technical", "companies": [ "synopsys" ], "people": [], "headline": "Synopsys introduces a 2026 R1 photonic Verilog-A model-generation flow", "fact": "Synopsys announced the Ansys 2026 R1 release with a photonic circuit-design flow connecting OptoCompiler and Lumerical. The release notes describe CML Compiler generating photonic Verilog-A models for PrimeSim HSPICE/SPICE from component data including scattering parameters produced by FDTD, MODE and Multiphysics, enabling electro-optical circuit simulation in OptoCompiler. This records the announced circuit-model flow, rather than a device compact model or a later patch release.", "sources": [ { "title": "Synopsys outlines its engineering vision and Ansys 2026 R1 release", "url": "https://news.synopsys.com/2026-03-11-Synopsys-Outlines-Vision-for-Engineering-the-Future", "checkedAt": "2026-10-06", "summary": "The March 11 announcement describes OptoCompiler/Lumerical integration and automated photonic Verilog-A model generation.", "status": "available", "archiveUrl": null }, { "title": "2026 R1 release notes", "url": "https://optics.ansys.com/hc/en-us/articles/49743302311059-2026-R1-Release-Notes", "checkedAt": "2026-10-06", "summary": "CML Compiler generates photonic Verilog-A models for PrimeSim HSPICE/SPICE and OptoCompiler electro-optical simulation. Version labels do not independently establish publication dates.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/synopsys-2026-03-photonic-verilog-a-model-generation/" }, { "id": "micron-2026-ams-verification-ai-assisted-coding-hiring", "when": { "start": "2026-03-04", "precision": "day" }, "kind": "organizational", "companies": [ "micron" ], "people": [], "headline": "Micron job posting combines full-chip AMS verification with AI-assisted coding", "fact": "A Micron careers posting for an AMS verification role describes full-chip analog, digital, and firmware interaction, behavioral models, power-cycle verification, and use of AI-assisted coding to automate design and analysis work. This is evidence of the capabilities requested in a public hiring mandate, not proof that a specific AI-assisted flow was already deployed or measured.", "sources": [ { "title": "Micron Careers requisition JR93301", "url": "https://careers.micron.com/careers/job/40648103", "checkedAt": "2026-08-31", "summary": "Official Micron requisition JR93301, posted March 4, 2026, describes the full-chip AMS, behavioral-model, power-cycle, and required AI-assisted-coding scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/micron-2026-ams-verification-ai-assisted-coding-hiring/" }, { "id": "cadence-2026-metamorphic-testing-rnm", "when": { "start": "2026-03-03", "precision": "day" }, "kind": "technical", "companies": [ "cadence" ], "people": [], "headline": "Cadence author applies metamorphic testing to a SystemVerilog RNM receiver model", "fact": "A Cadence DVCon U.S. 2026 paper applies metamorphic testing to a SystemVerilog real-number model of a receiver baseband, ADC, and automatic-gain-control system where a detailed test oracle is impractical. It defines relations for doubled or halved input, constant ADC magnitude, and plus-or-minus 6 dB RSSI changes and exercises them with randomized stimuli. This is a reported case study, not an AI method or a company-wide deployment claim.", "sources": [ { "title": "Application of Metamorphic Testing to Mixed-Signal Systems with Behavioral Models", "url": "https://dvcon-proceedings.org/document/application-of-metamorphic-testing-to-mixed-signal-systems-with-behavioral-models/", "checkedAt": "2026-08-31", "summary": "The official proceedings record identifies Daniel Cross of Cadence and dates the presentation to March 3, 2026.", "status": "available", "archiveUrl": null }, { "title": "Application of Metamorphic Testing to Mixed-Signal Systems with Behavioral Models — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/submission_23.pdf", "checkedAt": "2026-08-31", "summary": "The paper describes the SystemVerilog RNM receiver case, the four metamorphic relations, randomized stimuli, and reported outcomes.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2026-metamorphic-testing-rnm/" }, { "id": "siemens-eda-2026-02-analogport-symphony-customer", "when": { "start": "2026-02-20", "precision": "day" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [], "headline": "Siemens publishes an AnalogPort mixed-signal die-to-die verification case study", "fact": "A Siemens EDA customer story reports that AnalogPort applied UVM to a 32 Gbps full-duplex die-to-die interface with 16 transmitters and 16 receivers. The story describes using Symphony Pro with Questa digital simulation and Solido SPICE simulation, automated boundary insertion, selective data recording, and MS Visualizer; this is a vendor-published customer report.", "sources": [ { "title": "How Symphony Pro Is Defining the Future of Mixed-Signal Verification for High-Speed Die-to-Die Interfaces: A Case Study by AnalogPort", "url": "https://blogs.sw.siemens.com/cicv/2026/02/20/how-symphony-pro-is-defining-the-future-of-mixed-signal-verification-for-high-speed-die-to-die-interfaces-a-case-study-by-analogport/", "checkedAt": "2026-08-30", "summary": "Siemens EDA's February 2026 customer story on AnalogPort's UVM-based verification of a high-speed die-to-die interface.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2026-02-analogport-symphony-customer/" }, { "id": "eliyan-2026-serdes-rnm-verification-hiring", "when": { "start": "2026-02-16", "precision": "day" }, "kind": "organizational", "companies": [ "eliyan" ], "people": [], "headline": "Eliyan roles establish AMS verification and schematic-derived RNM for chiplet SerDes PHYs", "fact": "Eliyan posted verification roles that pair organization-level AMS methodology with hands-on SerDes model ownership. The director role covers RNM, SV-AMS co-simulation, behavioral-model integration, UCIe and Ethernet PHYs, PLLs, CDRs, and SerDes analog front ends; the staff role develops SystemVerilog RNM directly from schematics and verifies those models with UVM tests and assertions. These are public hiring mandates, not evidence that every flow was already deployed.", "sources": [ { "title": "Eliyan Careers API: Director of Design Verification", "url": "https://api.lever.co/v0/postings/eliyan/7b23f047-2c8e-45db-a2ba-222a67864755", "checkedAt": "2026-08-31", "summary": "The official Lever API record exposes a February 16, 2026 creation timestamp and describes AMS flows, RNM, SV-AMS co-simulation, behavioral-model integration, and PHY verification leadership.", "status": "available", "archiveUrl": null }, { "title": "Eliyan Careers API: Staff Verification Engineer – AMS modeling", "url": "https://api.lever.co/v0/postings/eliyan/dfb7db8a-4849-4e1b-b44e-f2ffa603f3ce", "checkedAt": "2026-08-31", "summary": "The official Lever API record exposes a May 20, 2026 creation timestamp and describes hands-on SerDes SystemVerilog RNM development from schematics, model ownership, UVM tests, and assertions.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/eliyan-2026-serdes-rnm-verification-hiring/" }, { "id": "stmicroelectronics-2026-02-pmic-modeling-verification-student", "when": { "start": "2026-02-16", "precision": "day" }, "kind": "organizational", "companies": [ "stmicroelectronics" ], "people": [], "headline": "STMicroelectronics posts a student role for PMIC top-level verification and analog behavioral models", "fact": "STMicroelectronics posted a Master Thesis / Working Student Mixed-Signal Modelling and Design Verification role in Munich. The Power Management IC Design Verification Team assigns IC top-level verification, verification-flow development and analog behavioral models, with IEEE/Accellera standards and EDA reference flows. The qualifications include Verilog/SystemVerilog, Python, analog circuits and Cadence flows, with Virtuoso SKILL as a plus. The official JobPosting metadata identifies February 16 as datePosted for job 10540; the role does not identify a particular RNM implementation or a completed automation result.", "sources": [ { "title": "STMicroelectronics Careers: Master Thesis / Working Student Mixed-Signal Modelling and Design Verification (10540)", "url": "https://stmicroelectronics.eightfold.ai/careers/job/563637171592738-master-thesis-working-student-mixed-signal-modelling-and-design-verification-muenchen-germany", "checkedAt": "2026-10-06", "summary": "Official job 10540 supplies the PMIC-team mandate and skills. Its public JobPosting JSON-LD has datePosted 2026-02-16T15:03:19, a stronger date anchor than later recruiting-board copies.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/stmicroelectronics-2026-02-pmic-modeling-verification-student/" }, { "id": "renesas-2026-02-ddr5-verification-internship", "when": { "start": "2026-02-09", "precision": "day" }, "kind": "organizational", "companies": [ "renesas" ], "people": [], "headline": "Renesas DDR5 internship assigns analog/digital verification and UVM-based simulation infrastructure", "fact": "A Renesas requisition dated February 9 advertised a Summer 2026 Design Verification Intern role in Morrisville for DDR5 IC development. The student works with analog and digital designers on simulation verification and silicon debugging, develops infrastructure using Verilog, SystemVerilog, UVM, Python and Perl, and maintains verification environments and self-testing testbenches. The advertised work period was May 26 through August 14; this Event uses the date embedded in official requisition 20025372 rather than the internship start date. The official page now marks the vacancy expired.", "sources": [ { "title": "Renesas Careers: Design Verification Intern (20025372)", "url": "https://jobs.renesas.com/job/design-verification-intern-in-morrisville-north-carolina-united-states-jid-4053", "checkedAt": "2026-10-06", "summary": "Official expired Summer 2026 DDR5 internship page. Requisition 20025372_2026-02-09 supplies the Event's date; the page does not establish the original public posting timestamp. Duties include analog/digital verification, UVM infrastructure and testbenches.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2026-02-ddr5-verification-internship/" }, { "id": "nxp-2026-02-ams-digital-integration-co-op", "when": { "start": "2026-02-07", "precision": "day" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP co-op listing assigns AMS and digital integration, wreal views, simulation and silicon bring-up", "fact": "A Discover Technata recruiting listing dated February 7 advertised an NXP Analog Mixed-Signal Design Co-Op for early-career engineers. The role supports analog/digital integration, schematic and netlist views, connectivity checks, Verilog-AMS and wreal view generation, simple RTL wrappers and digital-on-top build checks. It also assigns block- and top-level Spectre/Xcelium/AMS Designer simulations, testbench and model packaging work, and automated lab measurements including power-up sequences. The listing is no longer accepting applications; its date is the recruiting board's posting date.", "sources": [ { "title": "Discover Technata: NXP Analog Mixed-Signal Design Co-Op", "url": "https://jobs.discovertechnata.com/companies/nxp-semiconductors-2/jobs/67107664-analog-mixed-signal-design-co-op", "checkedAt": "2026-10-06", "summary": "Preserved recruiting-board listing dated February 7, 2026, with the employer description of AMS/digital integration, Verilog-AMS/wreal views, simulation and lab work. Applications are closed; the employer's original publication date is not established.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-02-ams-digital-integration-co-op/" }, { "id": "nxp-2026-01-catania-mcu-ams-team-recruitment", "when": { "start": "2026-01-22", "precision": "day" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP recruits for a Catania MCU team and related AMS verification roles", "fact": "Jim Caravella posted a public invitation to join the first phase of a new MCU team using analog/mixed-signal IP, sharing NXP’s Catania MCX recruitment. A related Junior Mixed-Signal Verification Engineer posting assigns SystemVerilog RNM and Verilog-AMS analog models, verification coverage, robustness, test modes and DFT in new full-product teams. An October 2 Catania internship separately names an AMS Verification Team and proposes behavioral models, assertions, debug and coverage; its direct membership in the MCX team is not established. These sources record team-building and hiring, not completed technology deployment or NXP’s first presence in Catania.", "sources": [ { "title": "Jim Caravella: Catania MCU team recruitment", "url": "https://www.linkedin.com/posts/jimcaravella_come-join-the-first-phase-of-building-a-new-activity-7419996036330541056-3wc1", "checkedAt": "2026-11-07", "summary": "Original post metadata gives January 22, 2026 at 06:55:11 UTC. The post describes first-phase MCU/AMS-IP team building and shares NXP MCX/Catania recruitment. It does not establish Caravella’s formal title.", "status": "available", "archiveUrl": null }, { "title": "NXP Careers: Junior Mixed-Signal Verification Engineer (R-10063614)", "url": "https://nxp.wd3.myworkdayjobs.com/en-US/careers/job/Junior-Mixed-Signal-Verification-Engineer_R-10063614", "checkedAt": "2026-11-07", "status": "unavailable", "summary": "Reviewed official recruiting text describes Catania MCU team-building and SV-RNM/Verilog-AMS model assignments. Its first posting date is unconfirmed; a later direct endpoint check returned HTTP 403. It does not change the January recruiting-post date.", "archiveUrl": null }, { "title": "NXP Careers: Catania AMS verification internship (R-10064672)", "url": "https://nxp.wd3.myworkdayjobs.com/careers/job/Catania/Internship-Student-Analog-Mixed-Signal-verification-F-M_R-10064672", "checkedAt": "2026-11-07", "summary": "Official public Workday startDate is October 2, 2026. The full description names the AMS Verification Team and proposed modeling, assertions, debug and coverage duties, but specifies neither an HDL nor a direct MCX-team affiliation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-01-catania-mcu-ams-team-recruitment/" }, { "id": "apple-2026-london-ams-dv-team-hiring", "when": { "start": "2026-01-16", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple job posting describes building a new AMS design-verification team in London", "fact": "An Apple careers posting for an experienced AMS design-verification engineer says the role will help build a new team in London. It lists SystemVerilog and UVM verification, performance and power analysis, early power estimation, and research and innovation; AI and machine-learning experience appears as a desired qualification. This is evidence of a public hiring mandate, not proof that AI/ML or every requested method was already deployed.", "sources": [ { "title": "Apple Careers: Experienced AMS Design Verification Engineer", "url": "https://jobs.apple.com/en-ie/details/200642146-1731/experienced-ams-design-verification-engineer-m-f-d", "checkedAt": "2026-08-31", "summary": "Official Apple role 200642146, posted January 16, 2026, says the position will help build a new London AMS-DV team and lists the verification, power-analysis, research, and desired AI/ML scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2026-london-ams-dv-team-hiring/" }, { "id": "microchip-2026-01-aim-systemverilog-patent", "when": { "start": "2026-01-13", "precision": "day" }, "kind": "technical", "companies": [ "microchip" ], "people": [ "chuck-mcclish" ], "headline": "Microchip AIM patent grant describes SystemVerilog classes for analog information", "fact": "The US12524593B2 grant publication names Charles McClish as inventor and Microchip Technology as assignee. It describes Analog Information Model (AIM) SystemVerilog classes carrying analog properties such as voltage, current and resistance, with connected model instances exchanging and resolving information. This Event dates the grant publication, separate from the earlier AIM paper; it does not establish that AIM was first invented or newly deployed in 2026.", "sources": [ { "title": "US12524593B2: Analog information modeling", "url": "https://patents.google.com/patent/US12524593B2/en", "checkedAt": "2026-10-06", "summary": "The patent record gives January 13, 2026 as grant/publication date and identifies the inventor, assignee and SystemVerilog class-based AIM description. The application and related AIM work predate this grant.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2026-01-aim-systemverilog-patent/" }, { "id": "amd-2026-ai-assisted-mixed-signal-verification-strategy-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "amd" ], "people": [], "headline": "AMD job posting seeks an AI-assisted verification strategy for a mixed-signal IP organization", "fact": "An Indeed-hosted copy of an AMD Fellow-level pre-silicon verification posting describes a mixed-signal IP organization and asks the role to integrate UVM with real-number modeling and AMS co-simulation, modernize regression, debug, and coverage analytics, and define an AI-assisted strategy spanning intelligent test generation, regression triage, and coverage-gap prediction. This is evidence of a public hiring mandate, not proof that these methods were already deployed across AMD.", "sources": [ { "title": "AMD: Fellow – Pre-Silicon Verification – Quality and Methodology", "url": "https://www.indeed.com/viewjob?jk=6d09ad28c81505d5", "checkedAt": "2026-09-02", "summary": "The live Indeed-hosted copy of AMD's posting identifies the mixed-signal IP context, UVM/RNM/AMS architecture scope, and requested AI-assisted test-generation, triage, and coverage-gap strategy; no durable absolute posting date is exposed, so this Event uses year precision.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/amd-2026-ai-assisted-mixed-signal-verification-strategy-hiring/" }, { "id": "broadcom-2026-ams-sdf-macro-verification", "when": { "start": "2026", "precision": "year" }, "kind": "technical", "companies": [ "broadcom" ], "people": [ "jeevan-ramaswamy" ], "headline": "Broadcom presents a unified AMS-SDF approach for high-capacity macro verification", "fact": "Synopsys AMS SIG India 2026 lists a Broadcom user presentation by Jeevan Ramaswamy titled “High-Capacity Macro Verification: A Unified AMS-SDF Approach using VCS PrimeSim AMS.” The public agenda and proceedings establish a Broadcom-authored macro-verification flow combining AMS and SDF in VCS PrimeSim AMS. Because the presentation deck is gated, this Event does not assert implementation details, capacity results, speedup, or deployment scope beyond the published title.", "sources": [ { "title": "Synopsys AMS SIG India 2026 proceedings", "url": "https://www.synopsys.com/events/ams-sig/proceedings-2026.html", "checkedAt": "2026-10-19", "summary": "The official proceedings list Jeevan Ramaswamy of Broadcom and the high-capacity macro-verification presentation using a unified AMS-SDF approach with VCS PrimeSim AMS. The currently retrievable public pages do not establish a day; year precision is retained.", "status": "available", "archiveUrl": null }, { "title": "Synopsys AMS SIG India 2026 agenda", "url": "https://www.synopsys.com/events/ams-sig.html", "checkedAt": "2026-09-21", "summary": "The official event agenda lists the Broadcom talk as a user presentation in the 2026 AMS SIG India program.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/broadcom-2026-ams-sdf-macro-verification/" }, { "id": "google-2026-high-speed-phy-rnm-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "google" ], "people": [], "headline": "Google PHY role links RNM/AMS verification to adaptive-loop convergence and physical channel impairments", "fact": "A Google careers posting for a senior verification engineer in Israel lists ownership of verification for 112G and 224G high-speed PHY signal-processing designs. The role calls for RNM or SystemVerilog-AMS flows across analog-front-end and digital-DSP boundaries, with specialized testbenches for adaptive algorithms such as LMS and Zero-Forcing covering stability, convergence time, and tracking across process-voltage-temperature corners. It also calls for link bring-up, auto-negotiation and error-recovery tests and for channel loss, crosstalk, and reflections to be represented in the DV environment. This is evidence of a public hiring requirement, not proof of a deployed internal methodology.", "sources": [ { "title": "Senior Verification Engineer, Digital Signal Processing, Google Cloud", "url": "https://www.google.com/about/careers/applications/jobs/results/102258000768443078-senior-verification-engineer-digital-signal-processing-google-cloud", "checkedAt": "2026-09-14", "summary": "Google's careers page lists 112G/224G PHY verification, RNM or SystemVerilog-AMS AFE-to-DSP flows, LMS/Zero-Forcing stability, convergence and tracking across PVT, data-center link scenarios, and physical channel loss/crosstalk/reflection in the DV environment.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/google-2026-high-speed-phy-rnm-verification-hiring/" }, { "id": "intel-2026-ai-assisted-ams-bmod-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "intel" ], "people": [], "headline": "Intel job posting seeks AI-assisted development and analysis of AMS behavioral models", "fact": "An Intel AMS Verification Engineer posting describes SystemVerilog behavioral models for SerDes, PMU, and DC-DC circuits, integration with digital functional verification, AMS comparison to the models, and full-chip power-up simulation. It also asks for generative-AI code generation, AI-driven debugging, automated documentation, and AI-based workflows for model development, simulation analysis, and reporting. This is evidence of a public hiring mandate, not proof that every listed AI-assisted method was already deployed or measured.", "sources": [ { "title": "Intel Careers: AMS Verification Engineer (JR0283842)", "url": "https://intel.wd1.myworkdayjobs.com/en-US/External/job/AMS-Verification-Engineer_JR0283842", "checkedAt": "2026-09-02", "status": "unavailable", "summary": "The indexed official Intel requisition described the SystemVerilog BMOD, AMS comparison, full-chip power-up, and AI-assisted code, debug, analysis, documentation, and reporting mandate; the requisition is no longer active.", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/intel-2026-ai-assisted-ams-bmod-hiring/" }, { "id": "intel-2026-pll-fll-mixed-signal-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "intel" ], "people": [], "headline": "Intel job posting seeks mixed-signal verification leadership for PLL and FLL clock IP", "fact": "Intel posted a Senior Pre-Silicon Verification Engineer role describing functional verification of PLL and FLL clock-generator IP, SystemVerilog/UVM environments, tests, assertions and coverage, and leadership of mixed-signal validation using AMS simulations to identify and root-cause schematic bugs. This is evidence of a public hiring mandate for clock-IP verification, not proof of the completion or deployment of a particular verification flow.", "sources": [ { "title": "Intel Careers: Senior Pre-Silicon Verification Engineer (JR0280545)", "url": "https://intel.wd1.myworkdayjobs.com/en-US/External/job/Senior-Pre-Silicon-Verification-Engineer_JR0280545", "checkedAt": "2026-09-02", "status": "unavailable", "summary": "The indexed official Intel requisition described the PLL/FLL, UVM/SystemVerilog, assertion, coverage, AMS-simulation, and schematic-debug mandate; the requisition is no longer active.", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/intel-2026-pll-fll-mixed-signal-verification-hiring/" }, { "id": "microchip-2026-llm-mixed-signal-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "microchip" ], "people": [], "headline": "Microchip job posting combines full-chip mixed-signal verification with LLM-assisted debug and test work", "fact": "Microchip’s Senior Engineer I – Verification posting R1497-26 describes full-chip SoC/mixed-signal verification with SystemVerilog/UVM, analog-IP interactions and coverage closure, plus LLM-assisted code/stimulus generation, root-cause analysis, log/waveform triage and failure clustering. A November 4 Senior Engineer II role R4346-26 names the Chennai WIPD group and adds Verilog-A/AMS and SV-RNM models, SPICE and applicable silicon correlation for ADCs/DACs, PLLs, LDOs, bandgaps and clocking circuits, alongside AI-assisted verification, modeling and debug methodology. The related mandates are grouped without assuming a shared team or completed AI deployment; the later posting does not change this Event’s original year-only date.", "sources": [ { "title": "Microchip Careers: Senior Engineer I – Verification (R1497-26)", "url": "https://microchiphr.wd5.myworkdayjobs.com/en-US/External/job/Senior-Engineer-I---Verification_R1497-26-9", "checkedAt": "2026-09-02", "summary": "The official Microchip requisition describes the full-chip AMS scope, RNM preference, and LLM-assisted stimulus, debug, waveform-triage, failure-clustering, experimentation, and EDA-integration mandate; it exposes only relative posting age, so this Event uses year precision.", "status": "available", "archiveUrl": null }, { "title": "Microchip Careers: Senior Engineer II – AMS Verification (R4346-26)", "url": "https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/India---Chennai/Senior-Engineer-II---AMS-Verification_R4346-26-7", "checkedAt": "2026-11-07", "summary": "Official public Workday startDate is November 4, 2026. Full duties name WIPD in Chennai, HDL behavioral models, SPICE/applicable silicon correlation and AI-assisted verification/modeling/debug workflows. A shared direct team with R1497-26 is not established.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2026-llm-mixed-signal-verification-hiring/" }, { "id": "monolithic-power-systems-2026-mixed-signal-verification-framework-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "monolithic-power-systems" ], "people": [], "headline": "MPS lists a lead role to define its mixed-signal design and verification framework", "fact": "Monolithic Power Systems lists a Mixed-Signal Design & Verification Engineer Lead role to define and lead framework and infrastructure development for complex digital and mixed-signal ICs. The position covers behavioral modeling, analog and mixed-signal IP integration and verification, mixed-mode simulation, analog-digital interface definition, and post-silicon validation across power, sensing, motor-control, display, and audio products. This is evidence of a current hiring mandate, not proof of completed deployment.", "sources": [ { "title": "MPS Careers: Mixed-Signal Design & Verification Engineer Lead", "url": "https://www.monolithicpower.com/about-mps/careers/job-listings.html", "checkedAt": "2026-08-31", "summary": "The official MPS job board lists the Barcelona or Portugal lead role and its framework, behavioral-modeling, IP-verification, mixed-mode-simulation, and validation responsibilities.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/monolithic-power-systems-2026-mixed-signal-verification-framework-hiring/" }, { "id": "neurophos-2026-photonic-ai-ams-model-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "neurophos" ], "people": [], "headline": "Neurophos verification-lead role includes AMS model development for a photonic AI SoC", "fact": "Neurophos posted a Lead Verification Engineer role for its silicon-photonic AI platform. The position owns SoC verification strategy, UVM and constrained-random environments, SystemC model integration, regression automation, FPGA acceleration, gate-level sign-off, and development and verification of AMS and SystemVerilog models for in-house analog designs; AMS verification and RNM experience are also named as preferred skills. This is evidence of a hiring mandate, not proof of completed silicon or methodology deployment.", "sources": [ { "title": "Neurophos Careers: Lead Verification Engineer", "url": "https://jobs.ashbyhq.com/neurophos/fec687b1-8609-40a1-b670-6e2be5a34aaf", "checkedAt": "2026-08-31", "summary": "The official Ashby posting describes the photonic-AI SoC verification lead role, including AMS/SystemVerilog model development, UVM, SystemC integration, automation, FPGA acceleration, and RNM experience; no stable absolute posting date is exposed, so the Event uses year precision.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/neurophos-2026-photonic-ai-ams-model-verification-hiring/" }, { "id": "nxp-2026-advanced-power-ams-verification-lead-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP job posting seeks an AMS verification leader for its Milan advanced-power team", "fact": "An NXP Careers posting for a Senior AMS Verification leader in Milan describes ownership of verification strategies, plans, environments, regressions, coverage, behavioural models, checkers, assertions, and reusable components for the Advanced Power System team, including top-level mixed-signal verification and methodology improvement. The requested experience includes Verilog, SystemVerilog, UVM, SVA, Verilog-AMS, SystemC, WREAL/RNM, and mixed-signal EDA tools. This is evidence of a public hiring mandate, not proof that every listed method is already deployed. A related Chandler PMIC leadership listing checked on October 5 adds explicit power-sequencing and fault-management checks using reusable AMS/UVM/RNM environments.", "sources": [ { "title": "NXP Careers: Senior AMS Verification leader", "url": "https://nxp.wd3.myworkdayjobs.com/en-US/careers/job/Senior-AMS-Verification-leader_R-10065738", "checkedAt": "2026-08-30", "summary": "Official NXP Careers requisition R-10065738 identifies the Milan Advanced Power System role and describes its AMS verification leadership scope, deliverables, methodologies, languages, and tools.", "status": "available", "archiveUrl": null }, { "title": "NXP Careers: Principal AMS verification engineer, Chandler (R-10065974)", "url": "https://nxp.wd3.myworkdayjobs.com/en-US/careers/job/Senior-Analog-Mixed-Signal-Verification-Engineer_R-10065974-1", "checkedAt": "2026-10-05", "summary": "Related official PMIC leadership listing checked October 5, 2026; first publication is not established. It assigns reusable Verilog-AMS/SystemVerilog/UVM/RNM models and components, power sequencing, fault handling, coverage and sign-off. Grouped with the existing advanced-power mandate.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-advanced-power-ams-verification-lead-hiring/" }, { "id": "nxp-2026-serdes-ams-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "nxp" ], "people": [], "headline": "NXP seeks end-to-end AMS verification ownership for high-speed SerDes IP", "fact": "NXP posted a Principal AMS Verification Engineer role to own SerDes verification from concept through sign-off. The description covers UVM and UVM-AMS environments, RNM and Verilog-AMS model development and validation, PLL and CDR behavior, link training and adaptation, jitter and noise analysis, assertions and coverage, PVT and stress verification, and correlation among MATLAB or Python, behavioral models, and transistor-level simulation. This is evidence of a hiring mandate, not proof of project completion.", "sources": [ { "title": "NXP Careers: Principal AMS Verification Engineer (R-10063362)", "url": "https://nxp.wd3.myworkdayjobs.com/en-US/careers/job/Bangalore/Principal-AMS-Verification-Engineer_R-10063362", "checkedAt": "2026-08-31", "summary": "The official NXP Workday record describes the Bangalore SerDes verification role and its UVM/UVM-AMS, RNM/VAMS, PLL/CDR, robustness, coverage, and cross-abstraction correlation scope; it exposes only a mutable relative posting age, so the Event uses year precision.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2026-serdes-ams-verification-hiring/" }, { "id": "olix-2026-high-speed-io-ams-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "olix" ], "people": [], "headline": "OLIX seeks AMS verification ownership for high-speed I/O in an AI accelerator", "fact": "OLIX posted a Senior Mixed-Signal Verification Engineer role to own verification of high-speed I/O receive and transmit chains in its AI accelerator, including CDRs, phase interpolators, clock generation, equalization, samplers, slicers, deserializers, and digital control loops. The role defines fidelity tiers across RNM, Verilog-AMS, and transistor co-simulation, owns self-checking testbenches, coverage and sign-off, builds regression automation, and correlates models with silicon. This is evidence of a public hiring mandate, not proof of completed deployment.", "sources": [ { "title": "OLIX Careers: AMS Engineer", "url": "https://jobs.ashbyhq.com/olix/66692826-8dc2-4239-b775-d91c828e8346", "checkedAt": "2026-08-31", "summary": "The official Ashby posting describes ownership of high-speed-I/O AMS verification, RNM/VAMS/transistor fidelity choices, self-checking environments, coverage, regressions, sign-off, and silicon correlation; no stable absolute posting date is exposed, so the Event uses year precision.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/olix-2026-high-speed-io-ams-verification-hiring/" }, { "id": "semtech-2026-mixed-signal-ic-verification-hiring", "when": { "start": "2026", "precision": "year" }, "kind": "organizational", "companies": [ "semtech" ], "people": [], "headline": "Semtech lists cross-site roles for block-to-chip mixed-signal IC verification", "fact": "Semtech posted related senior verification roles in San Diego and Hyderabad covering verification plans for mixed-signal IP, subsystems, and full ICs; SystemVerilog and UVM testbenches; RTL, gate-level, and AMS simulation; constrained-random stimulus; assertions, functional and code coverage; continuous integration and regression automation; and desired SV-RNM or Verilog behavioral modeling. The San Diego role is tied to low-power sensing ICs with ADCs. These postings evidence a hiring mandate, not completed deployment.", "sources": [ { "title": "Semtech Careers: Sr. Verification Engineer – Mixed-Signal ICs (REQ2930)", "url": "https://semtech.wd1.myworkdayjobs.com/en-US/SemtechCareers/job/Sr-Verification-Engineer---Mixed-Signal-ICs_REQ2930", "checkedAt": "2026-08-31", "summary": "The official Workday record describes a San Diego sensing-IC role spanning block/chip AMS, UVM, coverage, CI/regressions, and desired SV-RNM or behavioral modeling; it shows only a mutable relative posting age.", "status": "available", "archiveUrl": null }, { "title": "Semtech Careers: Sr. Staff Verification Engineer (REQ2988)", "url": "https://semtech.wd1.myworkdayjobs.com/en-US/SemtechCareers/job/Sr-Staff-Verification-Engineer_REQ2988", "checkedAt": "2026-08-31", "summary": "The official Workday record describes the corresponding Hyderabad mandate for mixed-signal IP-through-chip verification, UVM, AMS simulation, coverage, automation, and desired analog behavioral modeling.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/semtech-2026-mixed-signal-ic-verification-hiring/" }, { "id": "cirrus-logic-2025-mixed-signal-modeling-verification-hiring", "when": { "start": "2025-12-23", "precision": "day" }, "kind": "organizational", "companies": [ "cirrus-logic" ], "people": [], "headline": "Cirrus Logic role covers mixed-signal verification strategy, reusable testbenches, and RNM models", "fact": "Cirrus Logic posted a Mixed Signal Modelling and Verification Engineer role to lead verification activities and help evolve company methodology for complex mixed-signal ICs. The position covers verification strategy, reusable testbenches, real-number modeling, SystemVerilog user-defined types and Verilog-AMS, hands-on modeling and simulation, and desired experience in UVM, assertions, functional and code coverage, and CPF or UPF power-aware verification. This is evidence of a hiring mandate, not proof that every listed practice is deployed in every project.", "sources": [ { "title": "Cirrus Logic Careers API: Mixed Signal Modelling and Verification Engineer", "url": "https://api.eu.lever.co/v0/postings/cirrus/28ee0c19-03d5-454f-90e5-7aad2d91a638", "checkedAt": "2026-08-31", "summary": "The official Lever API record exposes a December 23, 2025 creation timestamp and details the verification-strategy, reusable-testbench, RNM/UDT/VAMS, coverage, assertion, and power-aware scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cirrus-logic-2025-mixed-signal-modeling-verification-hiring/" }, { "id": "nxp-2025-12-uwb-systemc-ams-verification-presentation", "when": { "start": "2025-12-04", "precision": "day" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "carna-zivkovic" ], "headline": "Carna Zivkovic presents NXP-related SystemC-AMS UWB verification and process-variation modeling", "fact": "Carna Zivkovic presents a SystemC/SystemC-AMS model of a UWB transmitter, channel and receiver, comparing behavior with MATLAB and hardware measurements and examining how receiver gain/noise variations affect packet errors and sensitivity. The cover identifies her as an external contractor, not an NXP employee appointment. The slides credit Shrief Rizkalla as the main author of earlier work and Zivkovic as presenter. This Event records the December presentation and its statistical-model extension, not first publication of the underlying UWB research.", "sources": [ { "title": "NXP-related UWB system simulation presentation", "url": "https://coseda-tech.com/customers-partners", "checkedAt": "2026-10-19", "summary": "The public customer archive links COSEDA_UGM_2025__C.Zivkovic_NXP.pdf. The linked slides were reviewed: The cover states External contractor; pages 17-19 describe statistical behavior, earlier research and distinct main-author/presenter roles.", "status": "available", "archiveUrl": null }, { "title": "COSEDA User Group Meeting 2025: program", "url": "https://coseda-tech.com/news-reader/coseda-user-group-meeting-2025", "checkedAt": "2026-10-19", "summary": "The event page links the official December 3-4, 2025 agenda, which places this presentation on December 4.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2025-12-uwb-systemc-ams-verification-presentation/" }, { "id": "bosch-sensortec-2025-12-systemc-ams-project-reuse", "when": { "start": "2025-12-03", "precision": "day" }, "kind": "technical", "companies": [ "bosch-sensortec" ], "people": [ "alexandra-kuester" ], "headline": "Bosch Sensortec presents automated setup and maintenance of reusable SystemC-AMS virtual prototypes", "fact": "Alexandra Küster of Bosch Sensortec presents a COSIDE scripting flow for heterogeneous sensor virtual prototypes combining MEMS, analog, digital and firmware models. The slides contrast manual project copying and backporting with common templates, versioned building blocks, automated updates and a working top-level/testbench scaffold. Python copier, CMake and continuous integration support model reuse and maintenance. Automated test creation remains a next step. This is a reported modeling workflow, not an AI circuit-generation claim.", "sources": [ { "title": "Bosch Sensortec: Automated Project Setup using COSIDE Scripting", "url": "https://coseda-tech.com/customers-partners", "checkedAt": "2026-10-19", "summary": "The public customer archive links COSEDA_UGM_2025__A.Kuester_Bosch-Sensortec.pdf. The linked slides were reviewed: Küster and Bosch Sensortec appear on the cover; pages 7-8 describe reuse and setup, while page 13 identifies test creation as future work.", "status": "available", "archiveUrl": null }, { "title": "COSEDA User Group Meeting 2025: program", "url": "https://coseda-tech.com/news-reader/coseda-user-group-meeting-2025", "checkedAt": "2026-10-19", "summary": "The event page links the official December 3-4, 2025 agenda, which places this presentation on December 3.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-sensortec-2025-12-systemc-ams-project-reuse/" }, { "id": "infineon-2025-12-gate-driver-systemc-ams-rf-models", "when": { "start": "2025-12-03", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "guillermo-conde" ], "headline": "Infineon presents mixed RF and SystemC-AMS models for isolated gate-driver integration verification", "fact": "Guillermo Conde of Infineon presents SystemC-AMS/COSIDE models for smart gate drivers using coreless-transformer isolation. The flow combines discrete-event, timed-data-flow and electrical models with selectable RF baseband/passband abstractions. The integration example connects the RF isolation path to SPICE-level surrounding circuits for AMS verification. December 3 is the scheduled presentation date; November 27 on internal slide footers is not treated as the public presentation date. The slides describe a modeling approach, not company-wide deployment.", "sources": [ { "title": "Infineon: Bridging Power and RF", "url": "https://coseda-tech.com/customers-partners", "checkedAt": "2026-10-19", "summary": "The public customer archive links COSEDA_UGM_2025__G.Conde_Infineon.pdf. The linked slides were reviewed: The cover names Conde and December 3; pages 12-15 show the isolated gate-driver architecture, mixed RF abstractions and SPICE integration.", "status": "available", "archiveUrl": null }, { "title": "COSEDA User Group Meeting 2025: program", "url": "https://coseda-tech.com/news-reader/coseda-user-group-meeting-2025", "checkedAt": "2026-10-19", "summary": "The event page links the official December 3-4, 2025 agenda, which places this presentation on December 3.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2025-12-gate-driver-systemc-ams-rf-models/" }, { "id": "nvidia-2025-11-heart-hierarchical-ams-design-agents", "when": { "start": "2025-11-24", "precision": "day" }, "kind": "technical", "companies": [ "nvidia" ], "people": [ "souradip-poddar", "chia-tung-ho" ], "headline": "NVIDIA and university authors publish HeaRT for hierarchy-aware AMS circuit design exploration", "fact": "Souradip Poddar, Chia-Tung Ho and coauthors present HeaRT, an agentic AMS design framework that organizes circuit hierarchy, functional roles and feedback relationships to guide design changes. The work includes topology exploration as well as parameter refinement. The authors list NVIDIA, UT Austin and George Washington University affiliations. This records a research publication, not NVIDIA production deployment. The Event retains the November 24, 2025 initial-publication date; the March 26, 2026 revision is supporting evidence for the same research milestone.", "sources": [ { "title": "HeaRT: arXiv version history", "url": "https://arxiv.org/abs/2511.19669", "checkedAt": "2026-10-19", "summary": "The public record dates v1 to November 24, 2025 and v2 to March 26, 2026.", "status": "available", "archiveUrl": null }, { "title": "HeaRT v1 manuscript", "url": "https://arxiv.org/html/2511.19669v1", "checkedAt": "2026-10-19", "summary": "The original manuscript describes hierarchical circuit reasoning and topology exploration, with NVIDIA and university author affiliations.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nvidia-2025-11-heart-hierarchical-ams-design-agents/" }, { "id": "apple-2025-11-wireless-radio-verification-hiring", "when": { "start": "2025-11-17", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts a Wireless Radio Verification role spanning digital and RF-modeled subsystems", "fact": "Apple posted a Wireless Radio Verification Engineer role whose description covers radio digital controllers and Digital+RF subsystems spanning PLL, DAC and ADC data paths, power management, and coexistence. The hiring mandate includes UVM environments, constrained-random tests, coverage and assertions, and digital-plus-mixed-signal co-simulation integrating SystemVerilog behavioral and DMS models.", "sources": [ { "title": "Wireless Radio Verification Engineer", "url": "https://jobs.apple.com/en-us/details/200632358-3956/wireless-radio-verification-engineer", "checkedAt": "2026-09-02", "summary": "Official Apple posting dated November 17, 2025, describing verification of radio digital controllers and Digital+RF subsystems with UVM, constrained random testing, coverage, assertions, and mixed-signal co-simulation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2025-11-wireless-radio-verification-hiring/" }, { "id": "microchip-2025-11-ams-coverage-checkpoint-case-studies", "when": { "start": "2025-11-07", "precision": "day" }, "kind": "technical", "companies": [ "microchip", "siemens-eda" ], "people": [], "headline": "Siemens reports Microchip AMS coverage and checkpoint-debug case studies", "fact": "A Siemens forum recap reports two Microchip posters: mixed-signal code-coverage analysis of a temperature/voltage sensor exposed RTL bugs missed by standalone digital verification; a battery-backed SRAM case used Symphony Get Analog Value and checkpoint save/restore for analog visibility and debug. The date records publication of the vendor recap.", "sources": [ { "title": "Siemens recap of mixed-signal customer presentations", "url": "https://blogs.sw.siemens.com/cicv/2025/11/07/mixed-signal-verification-symphony-customer-success-stories-across-the-siemens-eda-and-solido-custom-ic-forums/", "checkedAt": "2026-09-07", "summary": "November 7 vendor report distinguishes Microchip's sensor coverage study from its separate SRAM visibility and checkpoint study.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2025-11-ams-coverage-checkpoint-case-studies/" }, { "id": "toppan-2025-cis-full-chip-mixed-signal-verification", "when": { "start": "2025-11-07", "precision": "day" }, "kind": "technical", "companies": [ "toppan", "siemens-eda" ], "people": [ "takaomi-nakabe" ], "headline": "Siemens reports TOPPAN cut full-chip CMOS image-sensor mixed-signal verification time by more than 50%", "fact": "A Siemens EDA customer-story recap reports that TOPPAN presented a full-chip mixed-signal verification workflow for a complex CMOS image sensor integrating a microcontroller with analog blocks including LDO, PLL, and temperature sensors. Siemens reports that Symphony reduced TOPPAN's mixed-signal verification time by more than 50% without compromising accuracy; this is a vendor-published customer report.", "sources": [ { "title": "Mixed-Signal Verification: Symphony Customer Success Stories across the Siemens EDA and Solido Custom IC Forums", "url": "https://blogs.sw.siemens.com/cicv/2025/11/07/mixed-signal-verification-symphony-customer-success-stories-across-the-siemens-eda-and-solido-custom-ic-forums/", "checkedAt": "2026-10-19", "summary": "Siemens EDA's vendor-published customer-story recap of TOPPAN's full-chip CMOS image-sensor verification workflow and reported verification-time reduction. The article caption identifies Takaomi Nakabe as the TOPPAN presenter. November 7 is the recap publication date, not a verified customer presentation date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/toppan-2025-cis-full-chip-mixed-signal-verification/" }, { "id": "mythic-2025-analog-compute-rnm-verification-hiring", "when": { "start": "2025-10-30", "precision": "day" }, "kind": "organizational", "companies": [ "mythic" ], "people": [], "headline": "Mythic role assigns RNM creation and mixed-signal verification for an analog-compute core", "fact": "Mythic posted a Senior Digital & Mixed-Signal Verification Engineer role responsible for making its analog flash-compute core accurately and thoroughly verifiable in digital and mixed-signal flows. The position spans RNM creation and verification, UVM, top-level algorithm verification, mixed-signal interfaces and specifications, and controller and FSM verification for data converters, PLLs, and power converters. This is evidence of a public hiring mandate, not proof of verification completion or product deployment.", "sources": [ { "title": "Mythic Careers API: Senior Digital & Mixed-Signal Verification Engineer", "url": "https://api.lever.co/v0/postings/mythic-ai.com/f9faeb06-60f1-4b04-9775-cd6854eca636", "checkedAt": "2026-08-31", "summary": "The official Lever API record exposes an October 30, 2025 creation timestamp and describes RNM creation, analog-compute-core verification, UVM, top-level algorithms, and mixed-signal controller verification.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/mythic-2025-analog-compute-rnm-verification-hiring/" }, { "id": "ams-osram-2025-early-power-dms-modeling", "when": { "start": "2025-10-15", "precision": "day" }, "kind": "technical", "companies": [ "ams-osram" ], "people": [], "headline": "ams OSRAM authors report a DMS flow for early full-chip power estimation", "fact": "An ams OSRAM DVCon Europe 2025 paper reports using digital mixed-signal simulation for early full-chip power estimation. Analog-model states map to quiescent-current values inside a central UVM testbench spanning multiple rails and IP blocks. The authors present the method as an early-estimation aid alongside detailed verification, not as a replacement for analog sign-off.", "sources": [ { "title": "Early Power Estimation of Mixed-Signal ICs Using Digital Mixed-Signal Simulation", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_110.pdf", "checkedAt": "2026-08-31", "summary": "The full DVCon Europe 2025 paper describes the analog-state-to-quiescent-current model, central UVM testbench, multi-rail application, and its bounded early-estimation role.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2025 proceedings program", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-Europe-2025_Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings program dates the ams OSRAM presentation to October 15, 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ams-osram-2025-early-power-dms-modeling/" }, { "id": "bosch-2025-cross-level-mixed-signal-verification", "when": { "start": "2025-10-15", "precision": "day" }, "kind": "technical", "companies": [ "bosch" ], "people": [], "headline": "Bosch authors report cross-level verification across virtual, RTL, and mixed-signal representations", "fact": "Robert Bosch authors report a cross-level verification flow that applies the same use-case scenarios across system specifications, virtual prototypes, RTL and mixed-signal design representations, and production software. The paper describes automated signal mapping and trace comparison and presents an automotive ASIC case study intended to expose inconsistencies among parallel representations and exercise mixed-signal hardware with real-field software scenarios.", "sources": [ { "title": "Automated Flow to Maintaining Consistency in Parallel Design Representations Using Cross-Level Verification", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_151.pdf", "checkedAt": "2026-08-31", "summary": "The Bosch-authored paper describes the cross-level flow, its specification, virtual-prototype, RTL/mixed-signal, and production-software scope, and the automotive ASIC case study.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2025 proceedings", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-Europe-2025_Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings identify Javier Castillo, Mohammad Badawi, and Jan-Hendrik Oetjens as the presenters and date the session to October 15, 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-2025-cross-level-mixed-signal-verification/" }, { "id": "nxp-2025-10-variation-aware-pll-systemc-ams", "when": { "start": "2025-10-15", "precision": "day" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "neha-chavan", "carna-zivkovic" ], "headline": "NXP authors preserve shared block variations in a SystemC-AMS PLL performance model", "fact": "NXP and RPTU authors presented variation-aware PLL performance evaluation at DVCon Europe 2025. Public slides integrate statistical performance kernels into SystemC-AMS charge-pump and loop-filter models, preserving 23 shared variations between the blocks. They evaluate PLL lock-time distributions across 2,000 runs and compare approaches with independently modeled block distributions. Related NXP work appeared in 2023; this event records the 2025 evaluation rather than the methodology's first introduction.", "sources": [ { "title": "Performance Evaluation of a Phase-Locked Loop using Variation-Aware Behavioral Models — slides", "url": "https://dvcon-proceedings.org/wp-content/uploads/Performance-Evaluation-of-a-Phase-Locked-Loop-using-Variation-Aware-Behavioral-Models.pdf", "checkedAt": "2026-10-09", "summary": "Public slides by Neha Chavan, Jan Rödel, Carna Zivkovic and Christoph Grimm show shared CP/filter variation parameters, SystemC-AMS integration and lock-time distribution comparisons. The full paper was not reviewed.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2025 official program: session 5C, paper 154", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-Europe-2025_Proceedings.pdf", "checkedAt": "2026-10-09", "summary": "The official program places this presentation in session 5C on October 15, 2025.", "status": "available", "archiveUrl": null }, { "title": "Variation-Aware Performance Verification of Analog Mixed-Signal Systems — 2023 publisher abstract", "url": "https://www.vde-verlag.de/proceedings-de/566205001.html", "checkedAt": "2026-10-09", "summary": "Publisher abstract identifies earlier NXP work using a compact linear kernel and SystemC-AMS charge-pump PLL analysis in 2023. The predecessor full text was not reviewed; it establishes prior work, not the detailed difference between the two publications.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2025-10-variation-aware-pll-systemc-ams/" }, { "id": "nxp-2025-gyroscope-uvm-ms-modeling", "when": { "start": "2025-10-15", "precision": "day" }, "kind": "technical", "companies": [ "nxp" ], "people": [], "headline": "NXP authors report UVM-MS modeling and verification of an automotive gyroscope", "fact": "An NXP DVCon Europe 2025 paper reports a gyroscope verification flow using UVM-MS, custom user-defined nets for voltage, current, resistance, and capacitance, Python through DPI, and safety-mechanism checks. In one capacitor-model comparison, the paper reports 24 seconds for a custom enet implementation, 129 seconds for EEnet, and 256 seconds for Verilog-AMS. Those timings apply only to that example and simulator setup.", "sources": [ { "title": "UVM-MS Based Verification of an Automotive Gyroscope", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_104.pdf", "checkedAt": "2026-08-31", "summary": "The full paper describes the custom UDNs, Python/DPI and UVM-MS flow, safety checks, time-step considerations, and the bounded capacitor-model timing comparison.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2025 proceedings program", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-Europe-2025_Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings program dates the NXP presentation to October 15, 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2025-gyroscope-uvm-ms-modeling/" }, { "id": "stmicroelectronics-2025-upf-rnm-sram-verification", "when": { "start": "2025-10-15", "precision": "day" }, "kind": "technical", "companies": [ "stmicroelectronics" ], "people": [], "headline": "ST authors report voltage-aware RNM and UPF verification of an SRAM subsystem", "fact": "An STMicroelectronics DVCon Europe 2025 paper reports a voltage-aware SRAM verification flow using SystemVerilog real-valued supply modeling and UPF supply-net types for retention memory and bias-generator behavior. For the presented case, the paper contrasts roughly two to three hours of SPICE simulation with 10 to 12 seconds in the digital flow. It also states limitations including PVT representation and simulator-specific UPF behavior.", "sources": [ { "title": "Voltage-Aware Functional Verification of SRAM Subsystems Using UPF and Real-Number Models", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_131.pdf", "checkedAt": "2026-08-31", "summary": "The full paper describes the SystemVerilog-real and UPF modeling, retention-memory and bias-generator cases, reported runtime comparison, and stated limitations.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2025 proceedings program", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-Europe-2025_Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings program dates the ST presentation to October 15, 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/stmicroelectronics-2025-upf-rnm-sram-verification/" }, { "id": "apple-2025-10-aeon-modeling-intern", "when": { "start": "2025-10-01", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple's Aeon internships describe AMS models, LLM workflows and SPICE-based accuracy checks", "fact": "Apple posted an Aeon Modeling Intern role in Munich on October 1, 2025 for AMS interface models, circuit/measurement comparison, automation and LLM-assisted development. Related role 200690119, posted October 19, 2026, assigns Python/C++ models for SerDes, PLLs, memory interfaces and converters; ML surrogate models trained on circuit simulations and silicon measurements; LLM/agent workflows for specification-to-model generation, code translation, tests and documentation; and automated accuracy checks against SPICE and measurements. It also proposes GPU/parallel acceleration and model-order reduction, with documented accuracy bounds and engineer ownership of correctness. The later recruitment is grouped with the existing Aeon mandate, without changing its original date or asserting completed AI-modeling results.", "sources": [ { "title": "Aeon Modeling Intern (m/f/d)", "url": "https://jobs.apple.com/en-gb/details/200623839-1731/aeon-modeling-intern-m-f-d?team=STDNT", "checkedAt": "2026-08-30", "status": "unavailable", "summary": "Original Apple role dated October 1, 2025, describing AMS interface models, circuit and measurement comparison, methodology, automation, accuracy-performance tradeoffs, and LLM-assisted development; the page is no longer available at the last check.", "archiveUrl": null }, { "title": "Apple Careers: Aeon Modeling Software Intern (200690119)", "url": "https://jobs.apple.com/en-us/details/200690119-1731/aeon-modeling-software-intern", "checkedAt": "2026-10-25", "summary": "Official page hydration data gives October 19, 2026. Full assigned work explicitly covers ML surrogates, LLM/agent model/test generation, SPICE/measurement accuracy checks and accuracy bounds. This related role strengthens the earlier Aeon Event; it is not a newly verified release or deployment.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2025-10-aeon-modeling-intern/" }, { "id": "kioxia-2025-flash-memory-ams-cosim-verification", "when": { "start": "2025-09-19", "precision": "day" }, "kind": "technical", "companies": [ "kioxia" ], "people": [], "headline": "KIOXIA reports AMS co-simulation in flash-memory SPICE verification", "fact": "A KIOXIA SNUG Japan presentation reports that flash-memory control uses many analog circuits and is repeatedly verified with SPICE simulation including AMS co-simulation. It describes applying PrimeSim HT and a VC Execution Manager utility in product development to reduce verification time and optimize simulation-job execution within limited computing resources.", "sources": [ { "title": "SNUG Japan 2025 Session Timetable", "url": "https://www.event-entry.net/snugjapan2025/timetable.php", "checkedAt": "2026-08-30", "summary": "Official session abstract on KIOXIA's product-development use of SPICE with AMS co-simulation, PrimeSim HT, and VC Execution Manager for flash-memory verification.", "status": "available", "archiveUrl": null }, { "title": "SNUG Japan 2025", "url": "https://www.zuken.co.jp/news/snug2025/", "checkedAt": "2026-08-30", "summary": "Zuken's event notice identifies September 19, 2025 as the SNUG Japan 2025 conference date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/kioxia-2025-flash-memory-ams-cosim-verification/" }, { "id": "siemens-eda-2025-09-apll-rnm-functional-verification", "when": { "start": "2025-09-12", "precision": "day" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [ "mariam-maurice" ], "headline": "Siemens and Ain Shams authors report UVM functional verification of an analog PLL RNM", "fact": "Mariam Maurice, Rich Edelman, Mohamed Dessouky, and Ashraf Salem published an Integration paper applying constrained-random stimulus, functional coverage, assertions, and a UVM testbench to an analog PLL real-number model. The paper varies loop-filter parameters, charge-pump current, and VCO gain, and compares modeled outputs with a reference model. Its first-online date is September 12, 2025, although the journal volume is dated 2026; the reported DUT is an RNM model.", "sources": [ { "title": "A-PLL functional verification paper: author-uploaded full text", "url": "https://www.researchgate.net/publication/395444153_Enhanced_functional_verification_models_that_ensure_the_full_functionality_of_an_A-PLL_device", "checkedAt": "2026-09-07", "summary": "Full text uploaded by Mariam Maurice identifies Siemens and Ain Shams affiliations, DOI 10.1016/j.vlsi.2025.102520, the first-online date, and the PLL-RNM verification methods and experiments.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2025-09-apll-rnm-functional-verification/" }, { "id": "infineon-2025-ai-sv-rnm-modeling", "when": { "start": "2025-09-11", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon authors present AI-based mixed-signal modeling with SystemVerilog RNM", "fact": "The official DVCon India 2025 agenda lists an Infineon presentation titled 'Scalable and cost-effective mixed signal modelling using AI with SV-RNM' by Sathyanarayana Ramamoorthy, Rutvikkumar Patel, Anand Rahul, Kranthi Kiran, and Hareesh Perumal. The public agenda establishes the presentation and its stated topic; without a retained paper, this Event does not assert a specific model-generation method, result, or deployment scope.", "sources": [ { "title": "DVCon India 2025 agenda", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCON_India_2025_Agenda.pdf", "checkedAt": "2026-08-31", "summary": "The official agenda dates the Infineon-authored presentation to September 11, 2025 and identifies its title, authors, affiliation, and SystemVerilog RNM and AI topic.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2025-ai-sv-rnm-modeling/" }, { "id": "coseda-2025-systemc-ams-assertion-library", "when": { "start": "2025-08-20", "precision": "day" }, "kind": "technical", "companies": [ "coseda-technologies" ], "people": [ "thilo-voertler" ], "headline": "COSEDA authors present a C++ assertion library for SystemC AMS verification", "fact": "A DVCon Japan 2025 presentation by COSEDA Technologies authors describes a pure-C++ assertion library for SystemC AMS using templates and operator overloading to provide SVA-like expression of temporal properties, including support for timed-data-flow models. This records a presented library and its stated capabilities, not a semiconductor-customer deployment.", "sources": [ { "title": "DVCon Japan 2025 program", "url": "https://sd050c3c4da464d85.jimcontent.com/download/version/1755625126/module/14890744927/name/2025-ProgramGrid.pdf", "checkedAt": "2026-08-31", "summary": "The official program identifies the COSEDA SystemC AMS assertion-library presentation and dates it to August 20, 2025.", "status": "available", "archiveUrl": null }, { "title": "DVCon Japan 2025 proceedings", "url": "https://www.dvcon-jpn.org/app/download/14898192527/DVCon-JP-2025-Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings identify Thilo Vörtler with COSEDA Technologies and describe the pure-C++ library, template and operator-overloading implementation, SVA-like expression, and timed-data-flow support.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/coseda-2025-systemc-ams-assertion-library/" }, { "id": "texas-instruments-2025-08-intern-rnm-verification-report", "when": { "start": "2025-08-03", "precision": "day" }, "kind": "organizational", "companies": [ "texas-instruments" ], "people": [], "headline": "TI intern reports SV-RNM testbench work during a Bangalore placement", "fact": "Yashaswini Mudda publicly reported completing a two-month Analog Design Verification internship at Texas Instruments in Bangalore. Her account describes SystemVerilog verification and testbench-flow automation, UVM exposure, work involving RC/LC and glitch filters and analog multiplexers, and SV-RNM logic for handling multiple testbench drivers without contention. She names Balaji Ammineni as manager and Mrinav Saxena as mentor. This is a participant’s report of a completed placement, not an independently measured result or company-wide methodology claim; the date is the post’s publication, not a reconstructed internship start or end.", "sources": [ { "title": "Yashaswini Mudda: Texas Instruments Analog Design Verification internship report", "url": "https://www.linkedin.com/posts/yashaswinimudda_im-thrilled-to-share-that-ive-recently-activity-7357844373608288259-fQoE", "checkedAt": "2026-11-07", "summary": "Original public post metadata gives August 3, 2025 at 18:46:40 UTC. The author describes the two-month completed internship, SV-RNM multidriver work, UVM and testbench automation, and identifies her manager and mentor. Exact placement dates and the organizational unit are not stated.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2025-08-intern-rnm-verification-report/" }, { "id": "sitime-2025-07-sv-rnm-verification-hiring", "when": { "start": "2025-07-18", "precision": "day" }, "kind": "organizational", "companies": [ "sitime" ], "people": [], "headline": "SiTime lists SV-RNM verification roles spanning UVM, assertions, coverage, and digital-top sign-off", "fact": "SiTime posted a verification role whose responsibilities included developing SystemVerilog real-number models, a digital-top SystemVerilog verification plan, UVM scoreboards, monitors, and sequencers, SVA, functional coverage, simulation debug, and tape-out sign-off. The listing named wreal/V-AMS, UVM-AMS, and formal property verification as relevant experience. A Munich listing checked in September 2026 repeats this responsibility and qualification pattern.", "sources": [ { "title": "SiTime Sr. Engineer, Verifications — official application", "url": "https://workforcenow.adp.com/mascsr/default/mdf/recruitment/recruitment.html?ccId=19000101_000001&cid=555e77b2-029a-4357-8712-1dd910b41621&jobId=575717&lang=en_US", "checkedAt": "2026-08-30", "summary": "Official SiTime ADP application for job 575717 in the mixed-signal verification role family.", "status": "available", "archiveUrl": null }, { "title": "Sr. Engineer, Verifications — recovered posting", "url": "https://jobs.spacecapital.com/companies/sitime/jobs/54672927-sr-engineer-verifications", "checkedAt": "2026-08-30", "summary": "Secondary recovery copy dated July 18, 2025, preserving the role's SV-RNM, UVM, SVA, coverage, digital-top, and sign-off responsibilities.", "status": "available", "archiveUrl": null }, { "title": "SiTime: Sr. Engineer, Verifications — Munich (1747)", "url": "https://workforcenow.adp.com/mascsr/default/mdf/recruitment/recruitment.html?ccId=19000101_000001&cid=555e77b2-029a-4357-8712-1dd910b41621&jobId=589338&lang=en_US", "checkedAt": "2026-09-09", "summary": "The official Munich listing repeats the SV-RNM, UVM, digital-top, SVA, coverage, sign-off, wreal/V-AMS, UVM-AMS, and formal-property scope. It exposes only a relative posting age; this source records its September 2026 visibility without assigning it the original 2025 role's date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sitime-2025-07-sv-rnm-verification-hiring/" }, { "id": "renesas-2025-07-uvm-ms-dac-verification-component", "when": { "start": "2025-07-01", "precision": "day" }, "kind": "technical", "companies": [ "renesas" ], "people": [ "steven-holloway" ], "headline": "Renesas engineer presents a concrete UVM-MS DAC verification component", "fact": "At Verification Futures UK 2025, Renesas engineer Steve Holloway presented a concrete example of creating a DAC verification component using the new UVM-MS methodology. The published session description identifies the verification-component architecture and code snippets as key content. This is a public UVM-MS implementation example from a Renesas engineer, not evidence of company-wide or product-wide deployment.", "sources": [ { "title": "UVM-MS: A Concrete Example using a DAC", "url": "https://www.tessolve.com/verification-futures/vf2025-uk/uvm-ms-a-concrete-example-using-a-dac/", "checkedAt": "2026-09-02", "summary": "Tessolve's session page identifies Steve Holloway and describes creation of a DAC verification component using UVM-MS, including verification-component architecture and code snippets.", "status": "available", "archiveUrl": null }, { "title": "Verification Futures Conference 2025 UK", "url": "https://www.tessolve.com/verification-futures/vf2025-uk/", "checkedAt": "2026-09-02", "summary": "Tessolve's official conference programme dates the UK event to July 1, 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2025-07-uvm-ms-dac-verification-component/" }, { "id": "texas-instruments-2025-analog-assertion-coverage-toolbox", "when": { "start": "2025-06-25", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "aadhar-sharma" ], "headline": "TI authors present an analog assertion and coverage toolbox for SPICE and behavioral models", "fact": "A Texas Instruments DAC 2025 presentation describes an Analog Assertion and Coverage Toolbox that checks range, frequency, ramp, and glitch behavior and identifies stimulus gaps across SPICE and behavioral-model verification. The record supports the presented checker and coverage workflow; it does not establish use on every TI program.", "sources": [ { "title": "AACT: Automated Analog Coverage Tool for Mixed Signal Verification", "url": "https://62dac.conference-program.com/presentation/?id=ENGPRES330&sess=sess217", "checkedAt": "2026-08-31", "summary": "The official DAC 2025 record identifies the TI presentation and describes range, frequency, ramp, and glitch checking plus stimulus-gap detection across SPICE and behavioral models.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2025-analog-assertion-coverage-toolbox/" }, { "id": "texas-instruments-2025-eenet-analog-test-bus", "when": { "start": "2025-06-23", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments", "cadence" ], "people": [ "aadhar-sharma" ], "headline": "TI and Cadence authors report an EEnet analog test-bus verification method", "fact": "A Texas Instruments and Cadence DAC 2025 presentation reports an EEnet-based analog test-bus method for checking voltage, current, loading, and coupling behavior. The authors describe using the real-number abstraction to reduce reliance on AMS simulation for the presented verification tasks. This is a reported customer/vendor method, not a claim that EEnet replaces circuit-level verification.", "sources": [ { "title": "Revolutionising SOC Verification through System Verilog EEnet-Enhanced Behavioural Model for Precision in Analog IP Characterisation", "url": "https://62dac.conference-program.com/presentation/?id=ENGPOST319&sess=sess263", "checkedAt": "2026-08-31", "summary": "The official DAC 2025 record identifies TI and Cadence authors and describes EEnet-based voltage, current, loading, and coupling checks with reduced AMS-simulation dependence for the presented tasks.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2025-eenet-analog-test-bus/" }, { "id": "renesas-2025-top-down-ams-verification-automation-hiring", "when": { "start": "2025-06-20", "precision": "day" }, "kind": "organizational", "companies": [ "renesas" ], "people": [], "headline": "Renesas role combines top-down AMS verification with CAD and flow automation for full-custom ASICs", "fact": "Renesas posted a senior staff AMS verification role to support top-down design and full-custom ASIC verification. The position covers Verilog-AMS and SystemVerilog behavioral models, real-number modeling, self-checking mixed-signal simulation, verification planning and regressions, chip-level integration, and Python and Cadence SKILL automation for project and verification flows. This is evidence of a public hiring mandate, not proof that every listed method was deployed across Renesas.", "sources": [ { "title": "Renesas Careers: Sr Staff AMS Verification Engineer (JID 3223)", "url": "https://jobs.renesas.com/job/sr-staff-ams-verification-engineer-in-paris-idf-france-jid-3223", "checkedAt": "2026-08-31", "summary": "The retained official expired requisition exposes June 20, 2025 in its requisition ID and describes top-down modeling, RNM, full-custom ASIC verification, self-checking regressions, and CAD and flow automation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2025-top-down-ams-verification-automation-hiring/" }, { "id": "apple-2025-06-mixed-signal-model-verification", "when": { "start": "2025-06-18", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple lists dedicated Mixed-Signal Model Verification roles", "fact": "Apple listed Mixed-Signal Model Verification Engineer roles whose description includes self-checking SystemVerilog testbenches that compare behavioral models with source circuits, functional checks against specifications, assertions, formal logical equivalence, lint and timing checks, and flow automation across mixed-signal design teams.", "sources": [ { "title": "Apple Analog and Digital Design search results (historical)", "url": "https://jobs.apple.com/en-us/search?location=United-States-USA&team=Analog-and-Digital-Design-HRDWR-ADD", "checkedAt": "2026-08-30", "status": "unavailable", "summary": "Apple's historical search results dated Cupertino and Austin variants of the role to June 18, 2025; those results are no longer present at the last check.", "archiveUrl": null }, { "title": "Mixed-Signal Model Verification Engineer — Jobaaj mirror", "url": "https://www.jobaaj.com/job/apple-mixed-signal-model-verification-engineer-austin-texas-united-states-3-to-5-years-1091696", "checkedAt": "2026-08-30", "summary": "Recovery copy of the Apple role describing circuit comparison, functional tests, assertions, formal equivalence, lint, timing checks, and automation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2025-06-mixed-signal-model-verification/" }, { "id": "bosch-sensortec-2025-05-sv-delta-sigma-modeling", "when": { "start": "2025-05-16", "precision": "day" }, "kind": "technical", "companies": [ "bosch-sensortec" ], "people": [], "headline": "Bosch Sensortec thesis develops a non-ideal SystemVerilog delta-sigma modulator model", "fact": "Elias Väänänen’s University of Oulu thesis reports work conducted at Robert Bosch Oy within Bosch Sensortec to improve discrete-time delta-sigma modulator design and mixed-signal verification. It develops SystemVerilog and Simulink behavioral models with nonlinearity and noise, selecting an impulse-invariant approach after comparison with EEnet modeling. The work reports simulation studies, but explicitly leaves transistor-level performance matching, including SNDR, and incremental reset operation untested. It therefore does not establish silicon correlation or sign-off accuracy. The date is the repository’s public-availability date, following its May 15 issue date.", "sources": [ { "title": "University of Oulu: thesis metadata", "url": "https://oulurepo.oulu.fi/handle/10024/56084?show=full", "checkedAt": "2026-11-07", "status": "unavailable", "summary": "Metadata reviewed November 7 gives issue date May 15, 2025 and availability/accession May 16 at 20:09:02 UTC. A later direct check returned HTTP 403. The May 2 foreword is not treated as publication.", "archiveUrl": null }, { "title": "Behavioural Modelling of a Discrete-Time Delta-Sigma Modulator Using SystemVerilog and Simulink", "url": "https://oulurepo.oulu.fi/bitstream/handle/10024/56084/nbnfioulu-202505163594.pdf?isAllowed=y&sequence=1", "checkedAt": "2026-11-07", "summary": "Page 6 explicitly locates the work in Robert Bosch Oy’s Bosch Sensortec business unit. Chapters 3–5 describe the HDL modeling and simulation studies; page 67 states that transistor-level performance matching and incremental reset operation were not tested.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-sensortec-2025-05-sv-delta-sigma-modeling/" }, { "id": "texas-instruments-2025-patent-ml-rnm-generation", "when": { "start": "2025-04-10", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "venkateswaran-padmanabhan", "guha-lakshmanan" ], "headline": "A TI patent publication describes machine-learning-assisted generation of real-number models", "fact": "U.S. patent application US20250117560A1, assigned to Texas Instruments, describes obtaining analog-simulation logs, training a neural network, deriving a mathematical transfer function, and producing a SystemVerilog-compatible simulation kernel for real-number modeling. This Event records a published patent disclosure; publication does not establish product implementation, internal deployment, or the scope of any deployed flow.", "sources": [ { "title": "US20250117560A1 — Automated generation of real-number models", "url": "https://patents.google.com/patent/US20250117560A1/en", "checkedAt": "2026-08-31", "summary": "The patent record identifies Texas Instruments as assignee, Venkateswaran Padmanabhan and Guha Lakshmanan among the inventors, the April 10, 2025 publication date, and the neural-network-to-SystemVerilog RNM disclosure.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2025-patent-ml-rnm-generation/" }, { "id": "silicon-labs-2025-rnm-ams-verification-hiring", "when": { "start": "2025-04-09", "precision": "day" }, "kind": "organizational", "companies": [ "silicon-labs" ], "people": [], "headline": "Silicon Labs posts AMS verification role for RNM-based IP and SoC sign-off", "fact": "Silicon Labs posted a Staff or Senior Staff AMS Verification role whose description covers functional, performance, and power sign-off for next-generation IP and SoCs using RNM models. The role includes Verilog-D, Verilog-A or Verilog-AMS behavioral modeling, block- and chip-level verification, self-checking regressions, model validation, silicon correlation, and SystemVerilog/UVM experience. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.", "sources": [ { "title": "Silicon Labs Careers: Staff/Senior Staff Engineer — AMS Verification (19905)", "url": "https://silabs.wd1.myworkdayjobs.com/en-US/SiliconLabsCareers/job/Hyderabad/Lead-Engineer---IC-Design_19905", "checkedAt": "2026-08-31", "summary": "The official Silicon Labs Workday record exposes an April 9, 2025 start date and describes its RNM, behavioral-modeling, IP/SoC sign-off, regression, model-validation, and silicon-correlation scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/silicon-labs-2025-rnm-ams-verification-hiring/" }, { "id": "cadence-2025-03-photonet-mixed-signal-verification", "when": { "start": "2025-03-27", "precision": "day" }, "kind": "technical", "companies": [ "cadence" ], "people": [ "paul-graykowski" ], "headline": "Cadence author describes PhotoNet and EEnet models for integrated photonic/electrical/digital verification", "fact": "Paul Graykowski, identified as a Cadence product-marketing director, describes SystemVerilog real-number modeling of photonic components with PhotoNet and electrical circuits with EEnet in Xcelium. The sponsored technical article targets verification of multi-chip systems containing photonics, analog electronics and digital controllers, and references associated models and adoption examples. March 27 is the article publication date, not a verified initial library release date. It does not identify a customer deployment or establish that the author implemented the libraries.", "sources": [ { "title": "High-Speed High-Capacity Mixed-Signal Simulation of Silicon Photonics", "url": "https://semiengineering.com/high-speed-high-capacity-mixed-signal-simulation-of-silicon-photonics/", "checkedAt": "2026-10-19", "summary": "The page is dated March 27, 2025, labels the article Sponsor Blog, identifies Graykowski and Cadence, and describes PhotoNet/EEnet mixed-signal verification.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2025-03-photonet-mixed-signal-verification/" }, { "id": "betasoft-2025-02-ldo-spike-xmodel-sva-verification", "when": { "start": "2025-02-26", "precision": "day" }, "kind": "technical", "companies": [ "betasoft" ], "people": [ "charles-dancak" ], "headline": "Charles Dančak presents XMODEL-assisted SVA/PSL checks for voltage spikes in an LDO bias line", "fact": "Charles Dančak of Betasoft Consulting presents an AMS assertion method for the op-amp bias line of the LDO regulator studied in his earlier UVM testbench paper. XMODEL represents the analog signal as piecewise mathematical expressions; meas_max and meas_min compute extrema over measurement intervals, which SVA/PSL properties can check for spikes missed by point sampling. Assertion evaluation remains clocked and detection depends on the model and measurement setup. This is a presented verification technique, not a general guarantee for arbitrary physical waveforms.", "sources": [ { "title": "DVCon U.S. 2025 program: session 12", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-U.S.-2025-Proceedings.pdf", "checkedAt": "2026-10-25", "summary": "Program page 32 places paper 1128 and Charles Dancak of Betasoft on February 26, 2025.", "status": "available", "archiveUrl": null }, { "title": "Catching the Elusive Voltage Spike with Analog/Mixed-Signal SVA/PSL Assertions", "url": "https://dvcon-proceedings.org/wp-content/uploads/1128.pdf", "checkedAt": "2026-10-25", "summary": "The sole author is affiliated with Betasoft. The paper explicitly refers to the earlier LDO UVM work, then adds analytic-extrema instrumentation and SVA/PSL checks for injected bias-line spikes; XMODEL use does not establish Scientific Analog coauthorship.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/betasoft-2025-02-ldo-spike-xmodel-sva-verification/" }, { "id": "cirrus-logic-2025-system-model-reuse-mixed-signal-verification", "when": { "start": "2025-02-26", "precision": "day" }, "kind": "technical", "companies": [ "cirrus-logic", "mathworks" ], "people": [ "bahaa-osman", "suhas-belgal" ], "headline": "Cirrus Logic and MathWorks authors report reusing system models in mixed-signal verification", "fact": "A DVCon U.S. 2025 paper by Cirrus Logic and MathWorks authors describes generating SystemVerilog DPI-C components from system-level models for reuse in mixed-signal verification. A reported test ran in 30 seconds with DPI-C versus 51 seconds with a user-defined nettype and 54 seconds with Verilog-AMS. The paper also contrasts two projects whose closed-loop verification began 18 and 43 weeks after RTL availability; those project timings are not presented as a controlled comparison.", "sources": [ { "title": "DVCon U.S. 2025 official program: session 12", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-U.S.-2025-Proceedings.pdf", "checkedAt": "2026-10-19", "summary": "Program page 32 dates paper 1057 to February 26, 2025 and identifies the Cirrus Logic/MathWorks authors, including presenter Bahaa Osman and Suhas Belgal. The paper and technical article remain separate supporting sources.", "status": "available", "archiveUrl": null }, { "title": "Reuse of System-Level Circuit Models in Mixed-Signal Verification — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1057.pdf", "checkedAt": "2026-08-30", "summary": "The paper details generated DPI-C reuse, the reported runtime comparison, and the distinct project timelines.", "status": "available", "archiveUrl": null }, { "title": "Reuse of System-Level Circuit Models in Mixed-Signal Verification", "url": "https://www.mathworks.com/company/technical-articles/reuse-of-system-level-circuit-models-in-mixed-signal-verification.html", "checkedAt": "2026-08-30", "summary": "MathWorks' technical article presents the Cirrus Logic collaboration and summarizes the model-generation and reuse workflow.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cirrus-logic-2025-system-model-reuse-mixed-signal-verification/" }, { "id": "ulkasemi-2025-amsv-uvm-utility", "when": { "start": "2025-02-26", "precision": "day" }, "kind": "technical", "companies": [ "ulkasemi", "designers-guide-consulting" ], "people": [ "simul-barua", "henry-chang" ], "headline": "Ulkasemi and Designer's Guide authors report an AMSV utility for UVM mixed-signal verification", "fact": "A DVCon U.S. 2025 paper by Ulkasemi and Designer's Guide Consulting authors reports an object-oriented UVM utility for mixed-signal verification that manages temperature, model parameters, fault injection, and reporting. The paper demonstrates PLL and temperature-sensor use cases and reports a roughly two-minute simulation for the presented setup. Although the paper discusses broader automation trends, it does not establish an AI-based implementation.", "sources": [ { "title": "A Reusable AMSV Utility for UVM-Based Mixed-Signal Verification", "url": "https://dvcon-proceedings.org/wp-content/uploads/1060.pdf", "checkedAt": "2026-08-31", "summary": "The full paper identifies Simul Barua with Ulkasemi and Henry Chang with Designer's Guide Consulting, and describes the UVM/OOP utility, parameter and fault controls, use cases, and bounded runtime result.", "status": "available", "archiveUrl": null }, { "title": "DVCon U.S. 2025 proceedings program", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-U.S.-2025-Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings program dates the presentation to February 26, 2025.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ulkasemi-2025-amsv-uvm-utility/" }, { "id": "samsung-2025-02-configurable-afe-channel-uvm", "when": { "start": "2025-02-25", "precision": "day" }, "kind": "technical", "companies": [ "samsung" ], "people": [], "headline": "Samsung authors report configurable AFE/channel models for PCIe receiver-logic verification", "fact": "Samsung authors present a configurable analog front-end behavioral and channel model in a UVM testbench for 16.0-GT/s PCIe receiver digital logic. Randomizable offsets and FIR channel coefficients exercise eye monitoring, offset calibration, DFE adaptation and margin logic, including deliberately out-of-range conditions that expose retry and timeout bugs. For the reported regression, time to 100% digital code coverage falls from 54.26 to 16.13 hours. The conventional comparison uses an XMODEL analog behavioral model; this does not establish Scientific Analog coauthorship or collaboration. The authors retain conventional circuit-reflecting models for verification requiring actual AFE/channel behavior.", "sources": [ { "title": "An Effective Digital Logic Verification Methodology of High Speed Interface IP Using a Configurable AFE Behavioral and Channel Model — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1035-2.pdf", "checkedAt": "2026-10-25", "summary": "The eight-page paper identifies Samsung-only authors, the 16.0-GT/s application, deliberately extended stimulus ranges and the Table 2 comparison; XMODEL is used in the conventional baseline.", "status": "available", "archiveUrl": null }, { "title": "DVCon U.S. 2025 program: poster 1035", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-U.S.-2025-Proceedings.pdf", "checkedAt": "2026-10-25", "summary": "The February 25 poster session lists paper 1035 and Samsung authors; this is the presentation date, rather than the PDF upload date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2025-02-configurable-afe-channel-uvm/" }, { "id": "ecosystem-2025-02-uvm-ms-1-standard", "when": { "start": "2025-02-04", "precision": "day" }, "kind": "technical", "companies": [ "cadence", "intel", "siemens-eda", "synopsys", "nxp", "qualcomm", "renesas" ], "people": [ "peter-grove" ], "headline": "Accellera releases UVM-MS 1.0 with participation from seven tracked companies", "fact": "On February 4, 2025, Accellera released UVM-MS 1.0, defining mixed-signal bridge and proxy components for driving and monitoring mixed-signal nets. The standard's participant list names active contributors from Cadence, Intel, Siemens EDA, Synopsys, NXP, Qualcomm, and Renesas; participation in the standard does not by itself establish deployment at those companies.", "sources": [ { "title": "Accellera Board Approves UVM-MS 1.0 Standard for Release", "url": "https://www.accellera.org/news/press-releases/408-accellera-board-approves-universal-verification-methodology-for-mixed-signal-uvm-ms-1-0-standard-for-release", "checkedAt": "2026-09-02", "summary": "Accellera's February 4, 2025 release announcement for UVM-MS 1.0 and its mixed-signal bridge and proxy framework.", "status": "available", "archiveUrl": null }, { "title": "Universal Verification Methodology for Mixed-Signal 1.0", "url": "https://www.accellera.org/images/downloads/standards/uvm-ms/UVM-MS_1.0.pdf", "checkedAt": "2026-09-02", "summary": "The released standard defines the framework and lists active participants from the seven tracked companies linked to this event, including Intel contributors omitted from the previous record.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ecosystem-2025-02-uvm-ms-1-standard/" }, { "id": "scientific-analog-2025-01-silicon-photonics-systemverilog", "when": { "start": "2025-01-21", "precision": "day" }, "kind": "technical", "companies": [ "scientific-analog" ], "people": [ "jaeha-kim" ], "headline": "Jaeha Kim presents SystemVerilog/XMODEL models of three-channel silicon-photonic WDM links", "fact": "At ASP-DAC 2025, Jaeha Kim, affiliated with Seoul National University and Scientific Analog, presents an invited paper on SystemVerilog/XMODEL simulation of silicon-photonic systems. The conference abstract describes mapping photonic elements to equivalent multi-port transmission lines and event-driven simulation of 5-Gb/s, three-channel WDM links using micro-ring, Mach-Zehnder and electro-absorption modulators. It reports 4.2, 8.3 and 8.3 simulated symbols per second for those examples. These are model-simulation results, not measured link throughput or demonstrated silicon correlation. January 21 is the scheduled presentation date; the publisher proceedings date is later.", "sources": [ { "title": "ASP-DAC 2025 official technical program and abstract: 1F-3", "url": "https://www.aspdac.com/aspdac2025/archive/program/program_abst.html", "checkedAt": "2026-10-25", "summary": "Session 1F-3 on January 21, 10:55–11:20, supplies the exact title, dual affiliation, model method, link conditions and simulation speeds.", "status": "available", "archiveUrl": null }, { "title": "Invited paper: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODEL — SNU publication record", "url": "https://snu.elsevierpure.com/en/publications/invited-paper-modeling-and-simulation-of-silicon-photonics-system/", "checkedAt": "2026-10-25", "summary": "University metadata identifies pages 141–146 and DOI 10.1145/3658617.3703934; its March 4 publication date is distinguished from the January conference presentation.", "status": "available", "archiveUrl": null }, { "title": "Introduction to Silicon Photonics Systems and Their Modeling with XMODEL — earlier tutorial record", "url": "https://www.scianalog.com/webinars/w20201109/", "checkedAt": "2026-10-25", "summary": "The November 9, 2020 tutorial already introduces combined photonic/electronic WDM modeling with the same modulator families. It supplies earlier methodological context, not evidence that the later quantitative results existed in 2020; it is not indexed as a second research milestone.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2025-01-silicon-photonics-systemverilog/" }, { "id": "ams-osram-2025-ams-dms-functional-coverage", "when": { "start": "2025", "precision": "year" }, "kind": "technical", "companies": [ "ams-osram" ], "people": [], "headline": "ams OSRAM authors report shared functional coverage across DMS and AMS verification of analog IP", "fact": "A DVCon Europe 2025 paper by ams OSRAM authors describes collecting analog-IP functional coverage from the same UVM top-level testbench for real-number models and transistor-level schematics. A common real-valued reference and mixed-signal sampler supported both modes; the authors report that AMS runs exposed effects such as glitch filtering that the real-number model did not reproduce.", "sources": [ { "title": "Implementing Functional Coverage for Analog IPs in Mixed-Signal Verification Environments", "url": "https://dvcon-proceedings.org/document/implementing-functional-coverage-for-analog-ips-in-mixed-signal-verification-environments-2/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the ams OSRAM functional-coverage paper.", "status": "available", "archiveUrl": null }, { "title": "Implementing Functional Coverage for Analog IPs in Mixed-Signal Verification Environments — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVConEU_2025_paper_102.pdf", "checkedAt": "2026-08-30", "summary": "The paper documents the shared UVM coverage approach across DMS and AMS modes and the analog effects observed only in schematic runs.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ams-osram-2025-ams-dms-functional-coverage/" }, { "id": "apple-2024-12-mixed-signal-behavioral-modeling", "when": { "start": "2024-12-03", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts a Mixed-Signal Behavioral Modeling Engineer role", "fact": "Apple posted a Mixed-Signal Behavioral Modeling Engineer role whose description includes SystemVerilog models that capture functional and non-ideal behavior, circuit-simulation and formal-equivalence checks, reusable modeling methodology, functional coverage, and automation for PLL/DLL, SerDes, sensor, and data-converter circuits.", "sources": [ { "title": "Mixed-Signal Behavioral Modeling Engineer", "url": "https://jobs.apple.com/en-sa/details/200581671/mixed-signal-behavioral-modeling-engineer", "checkedAt": "2026-08-30", "summary": "Official Apple role dated December 3, 2024, covering non-ideal SystemVerilog models, circuit and formal-equivalence checks, modeling methodology, coverage, and automation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2024-12-mixed-signal-behavioral-modeling/" }, { "id": "infineon-2024-analog-verification-automation-hiring", "when": { "start": "2024-12-01", "precision": "day" }, "kind": "organizational", "companies": [ "infineon" ], "people": [], "headline": "Infineon role targets centralized automation of analog and mixed-signal verification", "fact": "An Infineon job record for its central design-flow department in Dresden describes developing and integrating methods and software extensions for analog and mixed-signal verification automation, including SPICE simulation, reliability, optimization, and regression tooling. The role also lists AI/ML knowledge as an advantage. This is evidence of a public hiring mandate, not proof that a specific automated or AI-assisted flow was already deployed.", "sources": [ { "title": "Infineon: Staff Engineer Analog Verification Software (HRC0958244)", "url": "https://www.infineon.com/cms/pdflink/en/36335d6f-c1c6-11e6-9920-40f2e90e8d04/HRC0958244-Staff-Engineer-Analog-Verification-Software-f-m-div.pdf", "checkedAt": "2026-08-31", "summary": "The official Infineon requisition lists a December 1, 2024 start date and describes the central design-flow role's verification-automation, tool, methodology, design-flow-integration, and AI/ML scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2024-analog-verification-automation-hiring/" }, { "id": "infineon-2024-ams-rnm-verification-hiring", "when": { "start": "2024-11-15", "precision": "day" }, "kind": "organizational", "companies": [ "infineon" ], "people": [], "headline": "Infineon verification role lists SV-RNM behavioral modeling and AMS verification for SoCs and IP", "fact": "An Infineon job record for a Senior Engineer Verification role lists Verilog, wreal, or SV-RNM behavioral modeling; AMS verification for SoCs or IPs; test planning and debug; and independent mixed-signal-verification project and methodology-improvement responsibilities. It also names Verilog-AMS, SystemVerilog/UVM, and Cadence, Synopsys, and Mentor AMS tools. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.", "sources": [ { "title": "Infineon: Senior Engineer Verification (HRC0968540)", "url": "https://www.infineon.com/cms/pdflink/zh_CN/36335d6f-c1c6-11e6-9920-40f2e90e8d04/HRC0968540-Senior-Engineer-Verification.pdf", "checkedAt": "2026-08-31", "summary": "The official Infineon requisition lists a November 15, 2024 start date and describes its behavioral-modeling, SoC/IP AMS-verification, planning, debug, methodology, language, and simulator scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2024-ams-rnm-verification-hiring/" }, { "id": "sony-semiconductor-solutions-2024-automotive-cis-analog-fault-verification", "when": { "start": "2024-09-20", "precision": "day" }, "kind": "technical", "companies": [ "sony-semiconductor-solutions" ], "people": [], "headline": "Sony reports analog fault-injection verification for automotive mixed-signal image sensors", "fact": "A Sony Semiconductor Solutions SNUG Japan presentation describes applying PrimeSim Custom Fault to analog circuits in automotive image sensors, which the session abstract identifies as mixed-signal ICs. It reports deriving fault-detection rates from the fault-injection verification and feeding the results back into the design to improve the detection rate.", "sources": [ { "title": "SNUG Japan 2024 Session Timetable", "url": "https://www.event-entry.net/snugjapan2024/timetable.php", "checkedAt": "2026-08-30", "status": "unavailable", "summary": "Official session abstract describing Sony's PrimeSim Custom Fault verification of automotive mixed-signal image-sensor analog circuits, fault-detection-rate derivation, and design feedback.", "archiveUrl": "https://web.archive.org/web/20240820082850id_/https://www.event-entry.net/snugjapan2024/timetable.php" }, { "title": "SNUG Japan 2024", "url": "https://www.zuken.co.jp/news/snug2024/", "checkedAt": "2026-08-30", "summary": "Zuken's event notice identifies September 20, 2024 as the SNUG Japan 2024 conference date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sony-semiconductor-solutions-2024-automotive-cis-analog-fault-verification/" }, { "id": "texas-instruments-2024-adaptive-ams-glitch-checkers", "when": { "start": "2024-09", "precision": "month" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "aadhar-sharma" ], "headline": "TI authors report adaptive Verilog-AMS glitch checkers for earlier silicon-bug detection", "fact": "A Texas Instruments DVCon India 2024 paper reports a compact Verilog-AMS checker and assertion library for adaptive detection of kickback and frequency glitches across SPICE and behavioral-model verification. The paper describes automated checker insertion and execution-flow optimization. The word intelligent appears in the paper title, but the supported implementation is an adaptive checker flow rather than a demonstrated generative-AI system.", "sources": [ { "title": "Accelerating Silicon Bug Detection and Optimizing Execution Flow through Intelligent Adaptive Glitch Detectors in AMS Verification", "url": "https://dvcon-proceedings.org/wp-content/uploads/4A1-DVCon_India_2024_Final_Paper_0639.pdf", "checkedAt": "2026-08-31", "summary": "The full paper identifies Aadhar Sharma with Texas Instruments and describes the Verilog-AMS checker library, automated insertion, kickback and frequency cases, and SPICE/behavioral-model scope.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2024-adaptive-ams-glitch-checkers/" }, { "id": "samsung-2024-sv-udt-eenet-pmic-verification", "when": { "start": "2024-06-24", "precision": "day" }, "kind": "technical", "companies": [ "samsung" ], "people": [ "vijay-kumar" ], "headline": "Samsung authors present SystemVerilog EEnet models for PMIC loading verification", "fact": "At DAC 2024, Samsung authors presented a digital mixed-signal verification approach that combines lower-level behavioral models with a SystemVerilog user-defined EEnet to represent electrical loading in power-management IC verification. The presentation describes extending the DMS verification checklist to performance and loading behaviors beyond voltage-only interfaces.", "sources": [ { "title": "Accelerating PMIC Verification Using Digital Mixed Signal Methodology", "url": "https://61dac.conference-program.com/presentation/?id=ETPOST217&sess=sess232", "checkedAt": "2026-08-30", "summary": "The official DAC 2024 schedule identifies Samsung authors including Vijay Kumar, dates the presentation to June 24, and describes its SystemVerilog UDT/EEnet PMIC focus.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2024-sv-udt-eenet-pmic-verification/" }, { "id": "sitime-2024-afs-symphony-solido-oscillator-verification", "when": { "start": "2024-04-04", "precision": "day" }, "kind": "technical", "companies": [ "sitime", "siemens-eda" ], "people": [], "headline": "SiTime customer session reports AFS, Symphony, and Solido use for MEMS oscillator SoC verification", "fact": "At Siemens User2User North America 2024, a customer-presented SiTime session described using Analog FastSPICE, Symphony, and Solido Design Environment to integrate analog and digital components and accelerate verification of high-precision MEMS-based oscillator SoCs.", "sources": [ { "title": "U2U24 Custom IC Verification Track Sessions", "url": "https://www.siemens.com/en-gb/products/ic/solido/cicv-u2u-2024/", "checkedAt": "2026-09-25", "summary": "Siemens identifies the 2024 Custom IC Verification track as customer-presented sessions and lists SiTime verification acceleration with AFS, Symphony, and Solido for high-precision MEMS-based oscillator SoCs.", "status": "available", "archiveUrl": null }, { "title": "Solido Simulation Suite resources", "url": "https://www.siemens.com/en-us/products/ic/solido/simulationsuite/resources/", "checkedAt": "2026-09-25", "summary": "The current Siemens resource library identifies Vikram Vangapally of SiTime and repeats the Analog FastSPICE, Symphony, Solido Design Environment, analog/digital integration, and MEMS oscillator SoC verification scope.", "status": "available", "archiveUrl": null }, { "title": "User2User North America 2024", "url": "https://event-new.sw.siemens.com/website/65649/home/", "checkedAt": "2026-09-25", "summary": "The official event page dates the User2User North America 2024 main conference in Santa Clara to April 4, 2024.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sitime-2024-afs-symphony-solido-oscillator-verification/" }, { "id": "innophase-2024-uvm-testbench-automation-ams", "when": { "start": "2024-03-06", "precision": "day" }, "kind": "technical", "companies": [ "innophase", "designers-guide-consulting" ], "people": [ "henry-chang" ], "headline": "InnoPhase and Designer's Guide authors report Python-generated UVM testbench infrastructure for AMS designs", "fact": "A DVCon U.S. 2024 paper by InnoPhase and Designer's Guide Consulting authors reports a Python and Jinja flow that generates UVM testbench infrastructure from a DUT port list, including analog interfaces and agents plus register-abstraction integration. The paper presents deterministic template-based automation; it does not describe an AI-generated testbench flow.", "sources": [ { "title": "UVM Testbench Automation for AMS Designs", "url": "https://dvcon-proceedings.org/document/uvm-testbench-automation-for-ams-designs/", "checkedAt": "2026-08-31", "summary": "The official proceedings record identifies J. B. David with InnoPhase, Henry Chang with Designer's Guide Consulting, and the March 6, 2024 presentation.", "status": "available", "archiveUrl": null }, { "title": "UVM Testbench Automation for AMS Designs — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1137.pdf", "checkedAt": "2026-08-31", "summary": "The paper describes Python/Jinja generation from DUT ports, including analog interfaces, agents, and register-abstraction infrastructure.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/innophase-2024-uvm-testbench-automation-ams/" }, { "id": "meta-2024-dv-uvm-ams-co-simulation", "when": { "start": "2024-03-06", "precision": "day" }, "kind": "technical", "companies": [ "meta" ], "people": [], "headline": "Meta author presents a UVM-based AMS co-simulation methodology with dynamic model switching", "fact": "At DVCon U.S. 2024, Meta Reality Labs' Sandeep Sharma presented a UVM-based AMS co-simulation methodology that dynamically switches between real-number and SPICE representations while reusing digital mixed-signal checks, assertions, and random stimulus. The paper reports a nightly flow in which one AMS/SPICE test verified seven ADC configurations over a week.", "sources": [ { "title": "DV/UVM Based AMS Co-Simulation and Verification Methodology for Mixed-Signal Designs — session", "url": "https://dvcon.org/technical-session/1160-dv-uvm-based-ams-co-simulation-and-verification-methodology-for-mixed-signal-designs", "checkedAt": "2026-08-30", "summary": "The official DVCon session record dates the presentation to March 6, 2024 and identifies Sandeep Sharma of Meta.", "status": "available", "archiveUrl": null }, { "title": "DV/UVM Based AMS Co-Simulation and Verification Methodology for Mixed-Signal Designs", "url": "https://dvcon-proceedings.org/document/dv-uvm-based-ams-co-simulation-and-verification-methodology-for-mixed-signal-designs/", "checkedAt": "2026-08-30", "summary": "DVCon's proceedings record identifies the Meta Reality Labs co-simulation paper.", "status": "available", "archiveUrl": null }, { "title": "DV/UVM Based AMS Co-Simulation and Verification Methodology — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1160.pdf", "checkedAt": "2026-08-30", "summary": "The paper describes dynamic RNM/SPICE switching, reusable DMS verification assets, and the reported ADC regression cadence.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/meta-2024-dv-uvm-ams-co-simulation/" }, { "id": "siemens-eda-2024-03-adc-dac-rnm-functional-verification", "when": { "start": "2024-03-06", "precision": "day" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [ "mariam-maurice" ], "headline": "Mariam Maurice presents UVM, assertions, and coverage for ADC/DAC real-number models", "fact": "At DVCon U.S., Siemens EDA's Mariam Maurice presented methods for verifying ADC and DAC real-number models with randomized stimulus, functional coverage, assertions, and UVM. The paper includes constrained variation of reference and supply voltages and coverage of real-valued signal ranges. Its verification targets are modeled analog devices and their specified behavior.", "sources": [ { "title": "DVCon U.S. session 1049: Functional Verification of Analog Devices modeled using SV-RNM", "url": "https://dvcon.org/technical-session/1049-functional-verification-of-analog-devices-modeled-using-svrnm", "checkedAt": "2026-09-09", "summary": "The official session record identifies Mariam Maurice, Siemens EDA, and the March 6, 2024 presentation.", "status": "available", "archiveUrl": null }, { "title": "Functional Verification of Analog Devices modeled using SV-RNM — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1049.pdf", "checkedAt": "2026-09-09", "summary": "The conference paper details ADC/DAC RNM verification with constrained random stimulus, voltage-range coverage, assertions, and UVM, including reference and supply variation examples.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2024-03-adc-dac-rnm-functional-verification/" }, { "id": "ulkasemi-2024-full-chip-uvm-analog-verification", "when": { "start": "2024-03-06", "precision": "day" }, "kind": "technical", "companies": [ "ulkasemi", "designers-guide-consulting" ], "people": [ "simul-barua", "henry-chang" ], "headline": "Ulkasemi and Designer's Guide authors report a UVM full-chip flow with analog behavioral models", "fact": "A DVCon U.S. 2024 paper by Ulkasemi and Designer's Guide Consulting authors describes validating analog behavioral models against schematics and then integrating them into a full-chip UVM environment. The paper discusses complementary AMS and digital mixed-signal tradeoffs and presents the method as a reusable verification architecture, not as proof that behavioral abstraction replaces circuit-level verification.", "sources": [ { "title": "Advanced UVM-Based Chip Verification Methodologies with Full Analog Functionality", "url": "https://dvcon-proceedings.org/document/advanced-uvm-based-chip-verification-methodologies-with-full-analog-functionality/", "checkedAt": "2026-08-31", "summary": "The official proceedings record identifies Simul Barua with Ulkasemi, Henry Chang with Designer's Guide Consulting, and the March 6, 2024 presentation.", "status": "available", "archiveUrl": null }, { "title": "Advanced UVM-Based Chip Verification Methodologies with Full Analog Functionality — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1112.pdf", "checkedAt": "2026-08-31", "summary": "The paper describes schematic validation of analog behavioral models and their integration into a full-chip UVM verification environment.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ulkasemi-2024-full-chip-uvm-analog-verification/" }, { "id": "betasoft-2024-03-ldo-directed-random-uvm", "when": { "start": "2024-03-05", "precision": "day" }, "kind": "technical", "companies": [ "betasoft" ], "people": [ "charles-dancak" ], "headline": "Charles Dančak presents directed and randomly sequenced UVM tests for an LDO regulator", "fact": "Charles Dančak of Betasoft Consulting presents a UVM testbench for a programmable 45-nm CMOS LDO. MODELZEN extracts a SystemVerilog/XMODEL model from its Virtuoso schematic. Eight directed tests cover regulation, transients, operating modes and supply rejection; a randsequence alternates line and load transients while carrying circuit conditions between tests. A UVM event pool coordinates stimulus and measurements. One Xcelium run with seed 3947 reports four failing transient tests out of ten, including a 279-mV overshoot. These are modeled testbench results, not measured silicon or a universal coverage guarantee. This is the regulator-testbench work referenced by the later voltage-spike assertion paper.", "sources": [ { "title": "A UVM SystemVerilog Testbench for Directed and Random Testing of an AMS Low-Dropout Voltage Regulator — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1141-1.pdf", "checkedAt": "2026-10-25", "summary": "Pages 1–2 establish the Betasoft author, LDO model extraction and eight tests; Section VII identifies seed 3947 and the particular failing transient run.", "status": "available", "archiveUrl": null }, { "title": "DVCon U.S. 2024 official program: poster 1141", "url": "https://confcats-siteplex.s3.us-east-1.amazonaws.com/dvconus/dvconus24_program_v2_7854c7d723.pdf", "checkedAt": "2026-10-25", "summary": "The March 5 poster session lists paper 1141 and Charles Dancak of Betasoft; the paper title spells out Low-Dropout, while slides abbreviate LDO.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/betasoft-2024-03-ldo-directed-random-uvm/" }, { "id": "ecosystem-2024-03-verilog-ams-2023-standard", "when": { "start": "2024-03-04", "precision": "day" }, "kind": "technical", "companies": [ "analog-devices", "cadence", "nxp", "qualcomm", "renesas", "siemens-eda", "synopsys", "texas-instruments" ], "people": [ "peter-grove" ], "headline": "Accellera releases Verilog-AMS 2023 under working-group chair Peter Grove of Renesas", "fact": "Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.", "sources": [ { "title": "Accellera Approves Verilog-AMS 2023 Standard for Release", "url": "https://www.accellera.org/news/press-releases/393-accellera-approves-verilog-ams-2023-standard-for-release", "checkedAt": "2026-08-30", "summary": "Official March 4, 2024, release announcement identifying Peter Grove as working-group chair and summarizing the standard's updates.", "status": "available", "archiveUrl": null }, { "title": "Verilog-AMS Language Reference Manual, Version 2.5", "url": "https://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2023.pdf", "checkedAt": "2026-08-30", "summary": "Released Verilog-AMS 2023 standard, including the participant list used to associate the tracked companies with this shared event.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ecosystem-2024-03-verilog-ams-2023-standard/" }, { "id": "ecosystem-2024-02-systemverilog-msi-working-group", "when": { "start": "2024-02-07", "precision": "day" }, "kind": "technical", "companies": [], "people": [ "peter-grove" ], "headline": "Accellera forms the SystemVerilog Mixed-Signal Interface Types Working Group", "fact": "Accellera formed the SystemVerilog Mixed-Signal Interface Types Working Group to define SystemVerilog-compatible interconnect, conversion and resolution among dissimilar net types, including bidirectional connections between logic or user-defined nets and analog, electrical or real signals. Accellera said work in the UVM-MS and SystemVerilog-AMS groups had exposed a fundamental need for this capability within IEEE 1800 and that earlier approaches outside IEEE 1800, such as Verilog-AMS connect modules, had not met the complexity and usability requirements of typical SoCs. Peter Grove was named co-chair of the new working group.", "sources": [ { "title": "Accellera Forms SystemVerilog Mixed-Signal Interface Types Working Group", "url": "https://www.accellera.org/news/press-releases/389-accellera-forms-systemverilog-mixed-signal-interface-types-working-group", "checkedAt": "2026-09-02", "summary": "Accellera's February 7, 2024 formation announcement defines the bidirectional mixed-net scope, links the need to UVM-MS and SystemVerilog-AMS work, describes limitations of prior connect-module approaches, and names Peter Grove as co-chair.", "status": "available", "archiveUrl": null }, { "title": "SystemVerilog Mixed-Signal Interface Types Working Group", "url": "https://www.accellera.org/activities/systemverilog-mixed-signal-interface-types", "checkedAt": "2026-09-02", "summary": "The current Accellera working-group page preserves the charter and scope for uni- and bidirectional connections among logic, UDN, analog, electrical and real signals.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ecosystem-2024-02-systemverilog-msi-working-group/" }, { "id": "nvidia-2024-02-taiwan-serdes-modeling-hiring", "when": { "start": "2024-02-01", "precision": "day" }, "kind": "organizational", "companies": [ "nvidia" ], "people": [], "headline": "NVIDIA Taiwan recruitment describes SystemVerilog modeling within its high-speed I/O SerDes group", "fact": "A public NVIDIA recruiting post by Yvonne Chen advertised a Taiwan Senior Mixed-Signal Design Engineer role in the high-speed I/O SerDes group. The role works with analog designers on SystemVerilog models of closed-loop PLLs, receive CTLEs, SAR ADCs and optical components, and with system architects and digital designers on architecture specifications and adaptation algorithms. The post also assigns reusable scripting and silicon bring-up work. It establishes a recruiting mandate, not deployed modeling results; the recruiter is not identified as a technical team lead.", "sources": [ { "title": "Yvonne Chen: NVIDIA Taiwan Senior Mixed-Signal Design Engineer recruitment", "url": "https://www.linkedin.com/posts/yvonne-chen-6610949_senior-mixed-signal-design-engineer-activity-7158773119782907904-L4Db", "checkedAt": "2026-11-07", "summary": "Original post metadata gives February 1, 2024 at 10:48:35 UTC. Its full text names the SerDes group, circuit models and cross-functional assignments. This date anchors the public post, not an independently verified first careers publication or current vacancy.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nvidia-2024-02-taiwan-serdes-modeling-hiring/" }, { "id": "amd-2024-mixed-signal-sdf-gatesim-automation", "when": { "start": "2024", "precision": "year" }, "kind": "technical", "companies": [ "amd" ], "people": [], "headline": "AMD authors automate analog-boundary delay annotation for mixed-signal gate simulations", "fact": "AMD authors report a flow that reads a Standard Delay Format file, generates a SystemVerilog specify block for analog-boundary IOPATH delays, and instantiates it in an analog behavioral model for back-annotated mixed-signal gate simulation. In two reported IP cases with about 40 analog-interface signals, the automated approach reduced manual effort and annotated all paths; the paper also reports uncovering a constraint issue in one project after complete delay annotation.", "sources": [ { "title": "Methodology for SDF back annotated Gatesims for a Mixed signal IP", "url": "https://dvcon-proceedings.org/wp-content/uploads/P4-DVCon_India_2024_Final_Paper_2432.pdf", "checkedAt": "2026-08-31", "summary": "The AMD-authored DVCon India paper describes specify-block generation from SDF, analog/digital boundary timing, the two approximately 40-signal cases, reduced manual effort, and the reported constraint issue.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/amd-2024-mixed-signal-sdf-gatesim-automation/" }, { "id": "analog-devices-2024-ai-assisted-ams-verification", "when": { "start": "2024", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices and university authors evaluate an AI-generated SystemVerilog model in an AMS workflow", "fact": "A DVCon Europe 2024 paper by University College Cork and Analog Devices authors evaluates an experimental workflow that learns from analog simulation data and generates a SystemVerilog inference model. For an RC demonstration, the paper reports 16 seconds for analog simulation, 15 seconds for a non-AI SystemVerilog model, and 14 seconds for the AI model, and says the approach was evaluated at ADI with promising results. It does not establish production deployment.", "sources": [ { "title": "A New Approach to Integrating AI into Analog/Mixed-Signal Verification Workflow", "url": "https://dvcon-proceedings.org/document/a-new-approach-to-integrated-ai-into-analog-mixed-signal-verification-workflow/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the University College Cork and Analog Devices experimental AI-assisted AMS verification paper.", "status": "available", "archiveUrl": null }, { "title": "A New Approach to Integrating AI into Analog/Mixed-Signal Verification Workflow — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/164-A-new-approach-to-integrated-AI-into-analogmixed-signal-verification-workflow.pdf", "checkedAt": "2026-08-30", "summary": "The paper describes the learned SystemVerilog model, RC timing comparison, and experimental evaluation wording.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2024-ai-assisted-ams-verification/" }, { "id": "infineon-2024-svreal-fixed-point-fpga-debug", "when": { "start": "2024", "precision": "year" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "gabriel-rutsch" ], "headline": "Infineon authors extend svreal checks and FPGA debug for fixed-point mixed-signal models", "fact": "A DVCon Europe paper by Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker describes svreal extensions that detect range violations and precision loss in simulation by comparing fixed-point calculations with a shadow SystemVerilog real representation. Its Integrated Fixedpoint Analyzer interprets fixed-point signal values during FPGA debug. A buck-converter model illustrates the flow between host simulation and FPGA emulation.", "sources": [ { "title": "Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework", "url": "https://dvcon-proceedings.org/document/addressing-fixed-point-format-issues-in-fpga-prototyping-with-an-open-source-framework/", "checkedAt": "2026-09-09", "summary": "The official DVCon archive identifies the authors and the 2024 Europe conference year.", "status": "available", "archiveUrl": null }, { "title": "svreal fixed-point checks and FPGA debug — DVCon Europe paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/167-Addressing-Fixed-Point-Format-Issues-in-FPGA-Prototyping-with-an-Open-Source-Framework.pdf", "checkedAt": "2026-09-09", "summary": "The paper describes simulation checks for range and precision, a shadow real representation, ILA/VIO-based fixed-point interpretation, and the buck-converter example. Ordinary SystemVerilog real is used in host simulation; the FPGA uses a synthesizable representation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2024-svreal-fixed-point-fpga-debug/" }, { "id": "nxp-2024-pre-post-silicon-test-reuse", "when": { "start": "2024", "precision": "year" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "marcel-oosterhuis" ], "headline": "NXP authors report reusing AMS verification tests in post-silicon validation", "fact": "An NXP-authored paper reports reusing pre-silicon AMS functional tests in post-silicon validation with matching stimulus timing and side-by-side waveform visualization. The methodology uses Jupyter and Python around a reusable environment for product variants; the authors report deployment across multiple projects and products and one-day silicon bring-up.", "sources": [ { "title": "Analog Mixed Signal Verification and Validation Methodology: Bridging Pre- and Post-Silicon", "url": "https://dvcon-proceedings.org/document/analog-mixed-signal-verification-and-validationvv-methodology-bridging-the-gap-between-pre-silicon-verification-and-post-silicon-validation/", "checkedAt": "2026-08-30", "summary": "2024 NXP paper on reusable AMS tests, Python/Jupyter orchestration, product variants, and pre- to post-silicon correlation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2024-pre-post-silicon-test-reuse/" }, { "id": "samsung-2024-display-pmic-uvm-ams-spice-verification", "when": { "start": "2024", "precision": "year" }, "kind": "technical", "companies": [ "samsung" ], "people": [], "headline": "Samsung authors report reusing a UVM environment with SPICE for display-PMIC AMS verification", "fact": "A DVCon Europe 2024 paper by Samsung authors describes reusing a configurable digital mixed-signal UVM environment for a selected set of analog/mixed-signal tests coupled to a SPICE simulator. In the display-PMIC case, the authors report finding critical schematic issues before tapeout and correlating verification results with silicon measurements.", "sources": [ { "title": "A Configurable Re-Usable UVM Environment Coupled with an Advanced SPICE Simulator for AMS Verification of a Display PMIC", "url": "https://dvcon-proceedings.org/document/a-configurable-re-usable-uvm-environment-coupled-with-advanced-spice-simulator-for-analog-and-mixed-signal-verification-of-a-display-pmic/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Samsung display-PMIC UVM and SPICE verification paper.", "status": "available", "archiveUrl": null }, { "title": "A Configurable Re-Usable UVM Environment Coupled with an Advanced SPICE Simulator — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1013.pdf", "checkedAt": "2026-08-30", "summary": "The paper describes UVM-environment reuse for AMS/SPICE tests, reported pre-tapeout schematic findings, and silicon correlation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2024-display-pmic-uvm-ams-spice-verification/" }, { "id": "samsung-2024-mram-variation-aware-systemverilog-modeling", "when": { "start": "2024", "precision": "year" }, "kind": "technical", "companies": [ "samsung" ], "people": [], "headline": "Samsung Foundry authors add write-time and write-voltage variation to an MRAM SystemVerilog model", "fact": "Samsung Foundry authors report a SystemVerilog embedded-MRAM behavior model that incorporates write-time and write-voltage variation into bit-cell test behavior. The reported simulations exercise random write time and voltage-dependent intended write failures, and the authors state that the variation-aware operation was verified with the Digital Nonvolatile-memory Assist IP used to control the MRAM for IP validation.", "sources": [ { "title": "Variation-Aware Modeling Method for MRAM Behavior Model using System-Verilog", "url": "https://dvcon-proceedings.org/wp-content/uploads/1091.pdf", "checkedAt": "2026-08-31", "summary": "The Samsung Foundry paper describes the variation-aware SystemVerilog MRAM model, its write-time and write-voltage modes, and verification with the DNA IP for pre-silicon validation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2024-mram-variation-aware-systemverilog-modeling/" }, { "id": "texas-instruments-2023-ml-circuit-verification-debugging-patents", "when": { "start": "2023-12-21", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "venkateswaran-padmanabhan", "guha-lakshmanan" ], "headline": "TI patent publications disclose machine-learning methods for circuit verification and debug", "fact": "Two U.S. patent applications assigned to Texas Instruments disclose complementary machine-learning techniques for analog or hybrid analog/digital integrated circuits. US20230409789A1 describes learning from simulated signal values and comparing predicted outputs with actual IC outputs for validation; US20230409790A1 describes inverse models that infer inaccessible internal signals or state-machine states from top-level inputs and outputs for debug. The documents also describe simulation-test selection using coverage metrics. These are patent disclosures, not evidence of product implementation or a deployed verification service.", "sources": [ { "title": "US20230409789A1 — Machine learning techniques for circuit design verification", "url": "https://patents.google.com/patent/US20230409789A1/en", "checkedAt": "2026-09-02", "summary": "The patent record identifies the December 21, 2023 publication, Texas Instruments assignee, inventors, and the disclosed ML prediction and circuit-validation method.", "status": "available", "archiveUrl": null }, { "title": "US20230409790A1 — Machine learning techniques for circuit design debugging", "url": "https://patents.google.com/patent/US20230409790A1/en", "checkedAt": "2026-09-02", "summary": "The related patent record identifies the same publication date and TI assignee and describes inverse ML models for predicting internal signals and states for circuit debug.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2023-ml-circuit-verification-debugging-patents/" }, { "id": "renesas-2023-sv-udn-rnm-power-switched-capacitor-modeling", "when": { "start": "2023-11-15", "precision": "day" }, "kind": "technical", "companies": [ "renesas" ], "people": [], "headline": "Renesas presents SystemVerilog UDN RNM techniques for power and switched-capacitor models", "fact": "Two Renesas-authored papers presented in one DVCon Europe session report SystemVerilog UDN techniques for real-number modeling. One says Renesas had used Voltage-Current-Resistance UDNs for current-limited LDOs, smart chargers, and DCDC converters, then introduces a Voltage-Charge-Capacitance form for a switched-capacitor crystal oscillator and reports a 90,000x simulation-speed boost benefiting block design and chip-level integration verification. The companion paper models an LDO with current limiting and load capacitance using a self-triggering VIR-UDN mechanism and reports 84x fewer events for similar behavior, or about 778x at a coarser voltage step.", "sources": [ { "title": "SV VQC UDN for Modeling Switch-Capacitor-based Circuits", "url": "https://dvcon-proceedings.org/wp-content/uploads/91186.pdf", "checkedAt": "2026-08-30", "summary": "Renesas-authored paper defining the VQC UDN form, applying it to a 40 MHz switched-capacitor crystal oscillator, and reporting the 90,000x simulation-speed result.", "status": "available", "archiveUrl": null }, { "title": "Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor", "url": "https://dvcon-proceedings.org/wp-content/uploads/91829.pdf", "checkedAt": "2026-08-30", "summary": "Renesas-authored companion paper on a self-triggering VIR-UDN LDO model with current limiting, load capacitance, and reduced event counts.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2023 program grid", "url": "https://archive.dvcon-europe.org/2023-program-grid/", "checkedAt": "2026-08-30", "summary": "Official archived program placing both Renesas papers together in second-day session P2.1 on November 15, 2023.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2023-sv-udn-rnm-power-switched-capacitor-modeling/" }, { "id": "solidvue-2023-11-spad-tof-systemverilog-modeling", "when": { "start": "2023-11", "precision": "month" }, "kind": "technical", "companies": [ "solidvue", "scientific-analog" ], "people": [], "headline": "SolidVue and Scientific Analog authors model a SPAD-to-histogram sensor in SystemVerilog", "fact": "A DVCon Europe 2023 paper by SolidVue and Sungkyunkwan University authors with Scientific Analog coauthor Jaemin Park reports a SystemVerilog/XMODEL simulation platform for a SPAD-based time-of-flight sensor. Poisson-based photon and dark-count models include detection probability and dead time, and connect 64 SPADs and analog front ends to a TDC, histogram counter and timing controller. The paper shows histogram responses under varied sensor and illumination parameters and reports approximately 4.6 minutes for a 1.5-m proximity-sensor simulation. The testbench uses a 600-MHz eight-phase PLL clock with 6-ps RMS jitter. These are system-model results; measured-silicon correlation was not demonstrated.", "sources": [ { "title": "System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/91857.pdf", "checkedAt": "2026-10-25", "summary": "The eight-page paper explicitly affiliates Jaemin Park with Scientific Analog, rather than inferring company authorship from tool use. Sections IV–V specify clock/jitter conditions and 4,095 TOF measurements, not histogram bins.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2023 official program: P2.2", "url": "https://archive.dvcon-europe.org/2023-program-grid/", "checkedAt": "2026-10-25", "summary": "Official November 2023 conference program includes the paper in P2.2. The Event retains month precision rather than asserting an unverified first-publication day.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/solidvue-2023-11-spad-tof-systemverilog-modeling/" }, { "id": "synopsys-2023-power-aware-rnm-patent", "when": { "start": "2023-10-24", "precision": "day" }, "kind": "technical", "companies": [ "synopsys" ], "people": [], "headline": "A Synopsys patent discloses power-aware RNM synchronization across UPF and HDL descriptions", "fact": "U.S. patent US11797742B1, assigned to Synopsys, describes power-aware real-number modeling for dynamic mixed-signal verification. The disclosure detects mismatches between power-supply network and RTL HDL descriptions, generates runtime value converters for RNM analog boundaries, and can insert assertions to detect inconsistent supply values. This Event records a patent disclosure; publication does not establish customer use or product deployment.", "sources": [ { "title": "US11797742B1 — Power aware real number modeling in dynamic verification of mixed-signal integrated circuit design", "url": "https://patents.google.com/patent/US11797742B1/en", "checkedAt": "2026-08-31", "summary": "The patent record identifies Synopsys as assignee, names the inventors, dates publication to October 24, 2023, and describes UPF/HDL power synchronization, runtime value conversion, and mismatch assertions at RNM boundaries.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/synopsys-2023-power-aware-rnm-patent/" }, { "id": "siemens-eda-2023-07-pll-rnm-modeling-correlation", "when": { "start": "2023-07-26", "precision": "day" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [ "mariam-maurice" ], "headline": "Siemens and Ain Shams authors compare a SystemVerilog PLL model with transistor-level outputs", "fact": "Mariam Maurice, Mohamed Dessouky, and Ashraf Salem published an IEEE Access paper on analog PLL modeling in an event-driven simulator. It uses piecewise-linear value/slope representations with SystemVerilog user-defined types and nets for higher-order loop filters, models fractional division and phase noise, and represents output loading with resolved nets. The paper compares modeled PLL outputs with transistor-level simulation.", "sources": [ { "title": "Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator — full text", "url": "https://www.researchgate.net/publication/372674108_Increasing_the_Modelling_Accuracy_of_an_Analog_PLL_Device_executed_with_an_Event-Driven_Simulator", "checkedAt": "2026-09-09", "summary": "The public full text identifies Siemens and Ain Shams affiliations, DOI 10.1109/ACCESS.2023.3299227, the PLL modeling and comparison methods, and a July 26, 2023 publication date. The paper's dated first page takes precedence over the page's generic January 2023 label.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2023-07-pll-rnm-modeling-correlation/" }, { "id": "sitime-2023-keiichi-kajino-japan-verification-manager", "when": { "start": "2023-07", "precision": "month" }, "kind": "organizational", "companies": [ "sitime" ], "people": [ "keiichi-kajino" ], "headline": "Keiichi Kajino's profile dates his SiTime verification-manager role to July 2023", "fact": "Keiichi Kajino's public professional profile dates the start of his SiTime Manager of Verification role to July 2023 and identifies him as Manager, Japan Verification. His profile separately describes mixed-signal verification experience including mixed-mode simulation, analog and digital assertions, Verilog-A/Verilog-AMS, SystemVerilog RNM, and UVM-based mixed-signal testbenches.", "sources": [ { "title": "Keiichi Kajino — LinkedIn", "url": "https://jp.linkedin.com/in/keiichi-kajino-91378810b", "checkedAt": "2026-08-30", "summary": "Kajino's public profile dates his SiTime verification-management role to July 2023 and separately describes his career-level mixed-signal verification experience.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sitime-2023-keiichi-kajino-japan-verification-manager/" }, { "id": "scientific-analog-2023-06-ucie-phy-systemverilog", "when": { "start": "2023-06-29", "precision": "day" }, "kind": "technical", "companies": [ "scientific-analog" ], "people": [ "jaeha-kim" ], "headline": "Jaeha Kim presents interacting electrical and logical UCIe PHY models in SystemVerilog", "fact": "Scientific Analog hosts Jaeha Kim’s UCIe PHY Modeling and Simulation with XMODEL webinar. The resource page describes SystemVerilog models of PLL, DLL, duty-cycle correction, phase interpolation and transmitter/receiver circuits interacting with logical-layer FSMs. Training examples adjust reference voltages, clock/data timing, lane skew and link data rate using pseudo-random data; FSM coverage can be inspected in SystemVerilog. The materials include a recording, slides and a model package. The stated 4–32-GT/s range concerns model/design requirements, not a measured silicon implementation or UCIe compliance certification.", "sources": [ { "title": "UCIe PHY Modeling and Simulation with XMODEL — webinar and resource record", "url": "https://www.scianalog.com/webinars/w20230629/", "checkedAt": "2026-10-25", "summary": "The June 29, 2023 webinar record identifies Kim and both PHY layers, enumerates modeled blocks and training functions, and lists the recording and model-package resources.", "status": "available", "archiveUrl": null }, { "title": "Scientific Analog webinar announcement, June 2, 2023", "url": "https://www.scianalog.com/news/webinar-05/", "checkedAt": "2026-10-25", "summary": "The announcement schedules the webinar for June 29 and identifies Kim as Scientific Analog CEO/founder; June 2 is the news date, not the event date.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2023-06-ucie-phy-systemverilog/" }, { "id": "renesas-2023-uvm-ms-bridge-contribution", "when": { "start": "2023-06-22", "precision": "day" }, "kind": "technical", "companies": [ "renesas" ], "people": [ "peter-grove", "steven-holloway" ], "headline": "Renesas engineers present an MS Bridge submission to the Accellera UVM-AMS Working Group", "fact": "At Verification Futures UK 2023, Renesas engineers Peter Grove and Steven Holloway presented a submission to the Accellera UVM-AMS Working Group showing how an MS Bridge module could apply UVM to both AMS and DMS verification. The presentation covered simulator initialization and synchronization, stimulus and monitoring differences, a known limitation and possible solutions, and application to a mixed-signal block. The speakers said the presentation and example code had been shared with the EDA community to feed into a working-group white paper and cautioned that the implementation was not final before an official UVM-AMS release.", "sources": [ { "title": "Renesas’s Submission to the UVM-(A)MS working group", "url": "https://www.tessolve.com/?p=24204", "checkedAt": "2026-09-02", "summary": "Tessolve's presentation page identifies Peter Grove and Steven Holloway of Renesas and describes the MS Bridge proposal, mixed-signal-block application, known limitation, example-code sharing, and pre-standard status.", "status": "available", "archiveUrl": null }, { "title": "Verification Futures Conference", "url": "https://www.tessolve.com/verification-futures/", "checkedAt": "2026-09-02", "summary": "Tessolve's conference index dates Verification Futures 2023 Europe (UK) to June 22, 2023.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2023-uvm-ms-bridge-contribution/" }, { "id": "apple-2023-05-cellular-rf-dms-verification", "when": { "start": "2023-05-17", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple posts a cellular RF Digital-Mixed-Signal Verification role", "fact": "Apple posted a Digital-Mixed-Signal Verification Engineer role for cellular RF work whose description covers SystemVerilog behavioral models for LNA, PLL, ADC, DAC, and mixer blocks at multiple abstraction levels, matching models to schematic specifications, assertions, and UVM-based sub-system and system verification.", "sources": [ { "title": "Digital-Mixed-Signal Verification Engineer (original Apple role)", "url": "https://jobs.apple.com/en-us/details/200480187/digital-mixed-signal-verification-engineer-m-f-d", "checkedAt": "2026-08-30", "status": "unavailable", "summary": "Original Apple URL for role 200480187; the posting is no longer available on Apple at the last check.", "archiveUrl": null }, { "title": "Digital-Mixed-Signal Verification Engineer — LinkedIn mirror", "url": "https://at.linkedin.com/jobs/view/digital-mixed-signal-verification-engineer-m-f-d-at-apple-3605182756", "checkedAt": "2026-08-30", "summary": "Mirror of Apple's role 200480187 describing SystemVerilog analog models, schematic matching, assertions, and sub-system and system verification.", "status": "available", "archiveUrl": null }, { "title": "Digital-Mixed-Signal Verification Engineer — RapidJob mirror", "url": "https://www.rapidjob.de/job/7jjk4bu/", "checkedAt": "2026-08-30", "summary": "Mirror of the Apple role with a May 17, 2023 posting date and cellular RF transceiver context.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2023-05-cellular-rf-dms-verification/" }, { "id": "sony-semiconductor-solutions-2023-lidar-analog-model-system-simulation", "when": { "start": "2023-05-09", "precision": "day" }, "kind": "technical", "companies": [ "sony-semiconductor-solutions" ], "people": [], "headline": "Sony profile documents analog models and system simulators for automotive LiDAR sensor verification", "fact": "A Sony Semiconductor Solutions feature profiles an Automotive Business Division engineer whose work included developing analog models and system simulators to test SPAD ToF depth-sensor circuit and signal-processing designs. The profile says she designed and verified an analog sensor circuit in 2022 and moved into sensor-circuit evaluation in 2023.", "sources": [ { "title": "Driving toward a world free of road accidents: a story behind our original SPAD ToF Depth Sensor for Automotive LiDAR Applications", "url": "https://www.sony-semicon.com/en/feature/2023050901.html", "checkedAt": "2026-08-31", "summary": "Sony Semiconductor Solutions' May 9, 2023 feature identifies the engineer, her Automotive Business Division affiliation, and the analog-model, system-simulator, circuit-verification, and sensor-evaluation work.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sony-semiconductor-solutions-2023-lidar-analog-model-system-simulation/" }, { "id": "texas-instruments-2023-ml-waveform-prediction", "when": { "start": "2023-04-06", "precision": "day" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "venkateswaran-padmanabhan", "guha-lakshmanan" ], "headline": "TI authors evaluate machine-learning techniques for analog waveform prediction", "fact": "A Texas Instruments ISQED 2023 paper evaluates a machine-learning behavioral-model method for time-domain waveform prediction using feature extraction, waveform segmentation, and circuit partitioning. In an operational-amplifier proof of concept, the authors report an average output-prediction signal-to-noise ratio of 32 dB. The result is an evaluated proof of concept, not evidence of production deployment.", "sources": [ { "title": "ISQED 2023 program", "url": "https://www.isqed.org/English/Archives/2023/ISQED2023-Program-Rev2.pdf", "checkedAt": "2026-08-31", "summary": "The official program identifies the TI authors and dates the waveform-prediction paper to April 6, 2023.", "status": "available", "archiveUrl": null }, { "title": "Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal IC Verification", "url": "https://doi.org/10.1109/ISQED57927.2023.10129327", "checkedAt": "2026-08-31", "summary": "The IEEE record describes the ML behavioral-model method, operational-amplifier proof of concept, and reported 32 dB average output-prediction SNR.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2023-ml-waveform-prediction/" }, { "id": "analog-devices-2023-sip-connectivity-test-automation", "when": { "start": "2023-02-28", "precision": "day" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "ADI authors report automated SystemVerilog connectivity-test generation for a mixed-signal SiP", "fact": "Analog Devices authors report a Python flow that generates SystemVerilog connectivity tests from a human-readable spreadsheet for system-in-package analog/mixed-signal verification. On the reported Pin Driver ATE project, it generated checkers for more than 2,000 interface pins and completed almost 600 checks; the authors report reducing test creation from days to minutes while retaining reusable, hierarchy-aware checks.", "sources": [ { "title": "Automated Connectivity Test Creation for System-in-Package Analog Mixed-Signal Verification", "url": "https://dvcon-proceedings.org/wp-content/uploads/1043-Automated-Connectivity-Test-Creation-for-System-in-Package-Analog-Mixed-Signal-Verification.pdf", "checkedAt": "2026-08-31", "summary": "The Analog Devices-authored paper describes the spreadsheet-to-SystemVerilog flow and reports its application to the SiP Pin Driver ATE project, more than 2,000 interface pins, almost 600 checks, and the reduced generation time.", "status": "available", "archiveUrl": null }, { "title": "DVCon U.S. 2023 proceedings", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-US-2023_Proceedings.pdf", "checkedAt": "2026-08-31", "summary": "The official proceedings identify Samantha Pandez and Christopher Geen of Analog Devices and place the poster presentation on February 28, 2023.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2023-sip-connectivity-test-automation/" }, { "id": "scientific-analog-2023-02-receiver-jitter-tolerance-uvm", "when": { "start": "2023-02-28", "precision": "day" }, "kind": "technical", "companies": [ "scientific-analog" ], "people": [ "jaeha-kim" ], "headline": "Jaeha Kim presents reactive UVM measurement of modeled receiver jitter tolerance", "fact": "Jaeha Kim presents a reactive UVM testbench for high-speed wireline receiver jitter tolerance at DVCon U.S. 2023. The slides identify Seoul National University and Scientific Analog affiliations and place the SystemVerilog/XMODEL transceiver, jitter stimulus and statistical BER instrumentation inside a fixture. Standard UVM components use prior BER results to select the next sinusoidal-jitter amplitude, with linear and binary searches for the pass/fail boundary. The example reports 106 trials at 20 jitter frequencies in 41 minutes for a target BER below 10^-12. The BER comes from statistical model instrumentation, not a measured silicon run or counting 10^12 received bits.", "sources": [ { "title": "A UVM Reactive Testbench for Jitter Tolerance Measurement of High-Speed Wireline Receivers — slides", "url": "https://dvcon-proceedings.org/wp-content/uploads/1113-A-UVM-Reactive-Testbench-for-Jitter-Tolerance-Measurement-of-High-Speed-Wireline-Receivers-1.pdf", "checkedAt": "2026-10-25", "summary": "Slides 1, 8 and 11–14 identify dual affiliation, statistical BER, reactive search and the stated trial/frequency/runtime example.", "status": "available", "archiveUrl": null }, { "title": "DVCon U.S. 2023 official program: poster 2", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-US-2023_Proceedings.pdf", "checkedAt": "2026-10-25", "summary": "The February 28 poster session lists the receiver jitter-tolerance presentation and SNU author. Later tutorials and uploaded recordings are not separate research Events.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2023-02-receiver-jitter-tolerance-uvm/" }, { "id": "siemens-eda-2023-digital-centric-ams-methodology", "when": { "start": "2023-02-27", "precision": "day" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [], "headline": "Siemens EDA presents a digital-centric mixed-signal verification workshop", "fact": "At DVCon U.S. on February 27, 2023, Siemens EDA presented a workshop describing digital-centric mixed-signal verification methods. Its program covers real-number modeling, constrained-random verification, assertions, functional coverage, formal techniques, low-power verification, and automated debug; the evidence documents vendor methodology advocacy rather than customer adoption.", "sources": [ { "title": "Democratizing Digital-Centric Mixed-Signal Verification Methodologies", "url": "https://dvcon-proceedings.org/document/democratizing-digital-centric-mixed-signal-verification-methodologies/", "checkedAt": "2026-08-30", "summary": "Siemens EDA's DVCon U.S. 2023 workshop materials on digital-centric mixed-signal verification methods.", "status": "available", "archiveUrl": null }, { "title": "DVCon U.S. 2023 Proceedings", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-US-2023_Proceedings.pdf", "checkedAt": "2026-08-30", "summary": "The conference program dates the Siemens EDA workshop to February 27, 2023.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2023-digital-centric-ams-methodology/" }, { "id": "microchip-2023-analog-information-model", "when": { "start": "2023", "precision": "year" }, "kind": "technical", "companies": [ "microchip" ], "people": [ "chuck-mcclish" ], "headline": "Microchip author introduces an Analog Information Model abstraction for SystemVerilog RNM", "fact": "A Microchip-authored paper introduces an Analog Information Model that separates real-number model functionality from the SystemVerilog mechanism used to transport analog information. The proposed nodes and connectors provide a common interface across user-defined nets, UPF-based nets, and wreal, allowing stimulus and checking components to be reused while the underlying transport representation changes.", "sources": [ { "title": "Take AIM: Introducing the Analog Information Model", "url": "https://dvcon-proceedings.org/wp-content/uploads/1002-Take-AIM-Introducing-the-Analog-Information-Model.pdf", "checkedAt": "2026-08-30", "summary": "2023 Microchip paper defining an Analog Information Model abstraction over UDN, UPF, and wreal transport mechanisms.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2023-analog-information-model/" }, { "id": "renesas-2023-automated-pll-model-testbench", "when": { "start": "2023", "precision": "year" }, "kind": "technical", "companies": [ "renesas" ], "people": [ "jun-yan" ], "headline": "Renesas authors report automated model-versus-schematic testbenches across four PLL abstractions", "fact": "A Renesas-authored paper compares AMS, open-loop RNM, closed-loop RNM without EEnet, and closed-loop RNM with EEnet representations of a PLL. It reports generating model testbenches from spreadsheet and symbol data with SKILL, a two-DUT mode for model-versus-schematic or model-versus-model comparison, and SystemVerilog stimulus and checkers alongside a Verilog-AMS hardware module.", "sources": [ { "title": "Automated Modeling Testbench Methodology Tested with Four Types of PLL Models", "url": "https://dvcon-proceedings.org/document/automated-modeling-testbench-methodology-tested-with-four-types-of-pll-models/", "checkedAt": "2026-08-30", "summary": "2023 Renesas paper on automated PLL model testbenches, four abstraction choices, and model-to-schematic comparison.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2023-automated-pll-model-testbench/" }, { "id": "samsung-2023-oled-pmic-uvm-mixed-signal-verification", "when": { "start": "2023", "precision": "year" }, "kind": "technical", "companies": [ "samsung" ], "people": [ "vijay-kumar" ], "headline": "Samsung authors report UVM-based mixed-signal verification of an OLED display PMIC", "fact": "A DVCon Europe 2023 paper by Samsung authors reports a UVM-based mixed-signal verification environment for an OLED display power-management IC. The authors describe 45 validated wreal models, 142 tests, assertions and automated checks, a fifteen-week turnaround, resolution of multiple port-direction issues, and pin-connectivity checks designed to guard against mismatches.", "sources": [ { "title": "UVM-Based Mixed-Signal Verification of a Display PMIC Designed for OLED Display Applications", "url": "https://dvcon-proceedings.org/document/uvm-based-mixed-signal-verification-of-a-display-pmic-designed-for-oled-display-applications/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Samsung OLED display PMIC UVM mixed-signal verification paper.", "status": "available", "archiveUrl": null }, { "title": "UVM-Based Mixed-Signal Verification of an OLED Display PMIC — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/1091-UVM-Based-Mixed-Signal-Verification-of-a-Display-PMIC-Designed-for-OLED-Display-Applications.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the model and test counts, validation, checks, assertions, turnaround, reported port-direction issues, and pin-connectivity checks.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2023-oled-pmic-uvm-mixed-signal-verification/" }, { "id": "sony-semiconductor-solutions-2023-pixel-analog-timing-assertions", "when": { "start": "2023", "precision": "year" }, "kind": "technical", "companies": [ "sony-semiconductor-solutions" ], "people": [], "headline": "Sony interview describes timing assertions for exhaustive pixel and analog-control verification", "fact": "A Sony Semiconductor Solutions recruiting interview describes building an H timing-assertion mechanism to exhaustively design-verify operating conditions for signals controlling image-sensor pixels and analog circuitry. The engineer presents the mechanism as a response to control signals that the prior design approach made difficult to verify.", "sources": [ { "title": "先輩社員インタビュー — 垣根を超えて、感動をつくる。専門性不問コース", "url": "https://www.sony-semicon.com/ja/jobs/ctf/interview.html", "checkedAt": "2026-08-31", "summary": "The official SSS recruiting interview, published on the site's 2023 edition, describes the H timing-assertion mechanism and its exhaustive verification of signals controlling pixels and analog circuits.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sony-semiconductor-solutions-2023-pixel-analog-timing-assertions/" }, { "id": "synopsys-2022-rnm-ams-emulation", "when": { "start": "2022-11-21", "precision": "day" }, "kind": "technical", "companies": [ "synopsys" ], "people": [], "headline": "Synopsys reports real-number-model support in an AMS emulation prototype", "fact": "A Synopsys publication reports that four years of DARPA POSH work produced an AMS emulation prototype capable of running digital logic, real-number analog models, and software together. It reports a 97-fold speedup over simulation on one customer design and says commercialization was planned for 2023; it does not establish that the planned product release occurred.", "sources": [ { "title": "What Is AMS Verification?", "url": "https://www.synopsys.com/blogs/chip-design/what-is-ams-verification.html", "checkedAt": "2026-08-30", "summary": "Synopsys's November 2022 account of DARPA POSH work on RNM-capable AMS emulation, a reported customer benchmark, and a planned 2023 commercialization.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/synopsys-2022-rnm-ams-emulation/" }, { "id": "apple-2022-munich-dms-verification-hiring", "when": { "start": "2022-10-21", "precision": "day" }, "kind": "organizational", "companies": [ "apple" ], "people": [], "headline": "Apple Cellular and Connectivity team member advertises a Munich Digital Mixed-Signal Design/Verification role", "fact": "An Apple Cellular and Connectivity team member publicly advertised a Digital Mixed-Signal Design/Verification Engineer role in Munich, one of four analog and mixed-signal design, validation, and verification openings in the hiring notice.", "sources": [ { "title": "Careers at Apple: Join us. Be you.", "url": "https://www.linkedin.com/posts/vahid-majidzadeh-b2121518_careers-at-apple-join-us-be-you-activity-6989132878399881216--TgC", "checkedAt": "2026-09-02", "summary": "Public post dated October 21, 2022, by an Apple Cellular and Connectivity team member listing role 200436589 as a Digital Mixed-Signal Design/Verification Engineer opening in Munich.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/apple-2022-munich-dms-verification-hiring/" }, { "id": "sony-semiconductor-solutions-2022-cis-rnm-spec-verification", "when": { "start": "2022-06-23", "precision": "day" }, "kind": "technical", "companies": [ "sony-semiconductor-solutions" ], "people": [], "headline": "Sony reports SystemVerilog RNM verification for CIS analog/digital specification consistency", "fact": "A Sony Semiconductor Solutions DVCon Japan presentation reports a CIS verification flow that models analog circuits as SystemVerilog Real Number Models to check analog/digital specification consistency early. The presentation reports a 3000x speedup compared with conventional SPICE and logic-simulator co-simulation.", "sources": [ { "title": "DVCon Japan 2022 Conference Proceedings", "url": "https://dvcon-proceedings.org/wp-content/uploads/DVCon-JP-2022-Proceedings.pdf", "checkedAt": "2026-08-30", "summary": "Official proceedings for the June 23, 2022 conference, including Sony's CIS SystemVerilog RNM flow and its reported 3000x speedup over SPICE and logic-simulator co-simulation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sony-semiconductor-solutions-2022-cis-rnm-spec-verification/" }, { "id": "scientific-analog-2022-01-accellera-membership", "when": { "start": "2022-01-15", "precision": "day" }, "kind": "organizational", "companies": [ "scientific-analog" ], "people": [], "headline": "Scientific Analog joins Accellera Systems Initiative", "fact": "Scientific Analog announces that it joined Accellera Systems Initiative as of January 15, 2022. Its January 18 announcement connects participation to its SystemVerilog analog-verification products and interoperability goals. Accellera’s August 2022 newsletter independently welcomes Scientific Analog among new members. Membership alone does not establish a particular working-group contribution, standard release, or customer adoption.", "sources": [ { "title": "Scientific Analog Joins Accellera", "url": "https://www.scianalog.com/news/accellera/", "checkedAt": "2026-10-25", "summary": "The January 18 announcement explicitly gives January 15, 2022 as the membership effective date.", "status": "available", "archiveUrl": null }, { "title": "Accellera Community Newsletter: August 2022", "url": "https://www.accellera.org/news/newsletters/2022-august", "checkedAt": "2026-10-25", "summary": "Accellera welcomes Scientific Analog among its newest members; it does not identify specific technical contributions.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2022-01-accellera-membership/" }, { "id": "analog-devices-2022-ams-dms-complementary-verification", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices authors report complementary AMS and DMS verification under UVM", "fact": "An Analog Devices-authored paper reports using DMS for full-chip functional verification and AMS for performance and detailed analog verification under a UVM-based approach. The paper states that model availability and quality determine partitioning between the flows and analyzes the coverage and bug classes each flow contributed.", "sources": [ { "title": "Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS", "url": "https://dvcon-proceedings.org/document/mixed-signal-design-verification-leveraging-the-best-of-ams-and-dms/", "checkedAt": "2026-08-30", "summary": "2022 Analog Devices paper comparing complementary UVM-based AMS and DMS roles, coverage, and bug findings.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2022-ams-dms-complementary-verification/" }, { "id": "betasoft-2022-analog-filter-uvm-testbench", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "betasoft" ], "people": [ "charles-dancak" ], "headline": "Charles Dančak reports a UVM/SystemVerilog testbench for a programmable analog filter", "fact": "A DVCon U.S. paper by Charles Dančak of Betasoft Consulting extends an object-oriented testbench into UVM for a digitally programmable analog bandpass filter. A fixture encapsulates the DUT and XMODEL stimulus/measurement primitives, while UVM components randomize frequencies and modes, compare transfer gain with HSPICE reference tables and collect functional coverage. SystemVerilog assertions check supply current and bias voltage during power-down. The paper reports agreement within 2% of HSPICE for the illustrated filter example; this is not a general analog-model error bound. The official proceedings archive assigns the work to 2022; conflicting secondary citations to 2021 are not used to backdate the Event.", "sources": [ { "title": "A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/A-UVM-SystemVerilog-Testbench-for-AnalogMixed-Signal-Verification-A-Digitally-Programmable-Analog-Filter-Example.pdf", "checkedAt": "2026-10-25", "summary": "The paper identifies the Betasoft author, UVM fixture architecture, filter tests and the example-specific HSPICE comparison.", "status": "available", "archiveUrl": null }, { "title": "DVCon official proceedings record: analog-filter paper", "url": "https://dvcon-proceedings.org/document/a-uvm-systemverilog-testbench-for-analog-mixed-signal-verification-a-digitally-programmable-analog-filter-example/", "checkedAt": "2026-10-25", "summary": "The official archive identifies the author, title and year 2022. The year differs from some later bibliographies; no unverified 2021 presentation date is asserted.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/betasoft-2022-analog-filter-uvm-testbench/" }, { "id": "coseda-2022-systemc-ams-abv-library", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "coseda-technologies" ], "people": [ "thilo-voertler" ], "headline": "COSEDA and research authors present a cross-domain assertion library for SystemC AMS models", "fact": "A 2022 DVCon Europe paper by COSEDA Technologies and research-institute authors presents a heterogeneous assertion-based-verification library for mixed-signal virtual prototypes in SystemC AMS. The work-in-progress prototype targets interactions across software, transaction-level, digital, and analog domains. This records the published library and examples, not evidence of deployment by a semiconductor customer.", "sources": [ { "title": "A Cross-Domain Heterogeneous ABV Library for Mixed-Signal Virtual Prototypes in SystemC AMS", "url": "https://dvcon-proceedings.org/document/a-cross-domain-heterogeneous-abv-library-for-mixed-signal-virtual-prototypes-in-systemc-ams/", "checkedAt": "2026-08-31", "summary": "The official proceedings record identifies Thilo Vörtler with COSEDA Technologies and describes the cross-domain SystemC AMS assertion library.", "status": "available", "archiveUrl": null }, { "title": "A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/75414.pdf", "checkedAt": "2026-08-31", "summary": "The paper gives the COSEDA and research affiliations, cross-domain library design and case study, and identifies the library as a work-in-progress prototype with a subset of SVA operators.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/coseda-2022-systemc-ams-abv-library/" }, { "id": "rohm-2022-model-based-mixed-signal-ic-verification", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "rohm" ], "people": [], "headline": "ROHM authors report SystemVerilog DPI-C model reuse in model-based mixed-signal IC verification", "fact": "ROHM authors report using Model-Based Design for mixed-signal IC development and early specification verification. For MEMS and sensor IC work, they describe generating a SystemVerilog DPI-C model from a Simulink MEMS model and using it in the Cadence environment to validate an IC containing analog amplifiers, ADCs, and digital processing logic before sign-off. The article also describes an internal Model-Based Design Group that maintains reusable modeling assets and guidance.", "sources": [ { "title": "Improving the Efficiency of IC Development with Model-Based Design", "url": "https://www.mathworks.com/company/technical-articles/improving-the-efficiency-of-ic-development-with-model-based-design.html", "checkedAt": "2026-08-30", "summary": "ROHM-authored 2022 technical article on its mixed-signal Model-Based Design flow, SystemVerilog DPI-C reuse, pre-sign-off IC validation, and internal enablement group.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/rohm-2022-model-based-mixed-signal-ic-verification/" }, { "id": "samsung-2022-embedded-nvm-esp-verification", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "samsung" ], "people": [], "headline": "Samsung Foundry authors report symbolic mixed-signal verification for embedded nonvolatile memories", "fact": "Samsung Foundry authors report a mixed-signal IP verification method using netlist extraction, module conversion, custom testbenches, and Synopsys ESP symbolic simulation. The paper applies the method to eMRAM, eFLASH, and OTP memories to compare behavioral simulation models with schematic-derived implementations and describes the flow as extending symbolic verification to mixed-signal memory structures not natively covered by the tool.", "sources": [ { "title": "Mixed-Signal Functional Verification Methodology for Embedded Non-Volatile Memory Using ESP Simulation", "url": "https://dvcon-proceedings.org/wp-content/uploads/Mixed-signal-Functional-Verification-Methodology-for-embedded-Non-volatile-Memory-using-ESP-simulation-1.pdf", "checkedAt": "2026-08-31", "summary": "The Samsung Foundry paper describes the netlist-extraction, module-conversion, custom-testbench, and ESP symbolic-simulation method and its eMRAM, eFLASH, and OTP cases.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2022-embedded-nvm-esp-verification/" }, { "id": "samsung-2022-ssd-pmic-sv-rnm-verification", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "samsung" ], "people": [ "vijay-kumar" ], "headline": "Samsung authors report SystemVerilog RNM verification of an SSD power-management IC", "fact": "A DVCon Europe 2022 paper by Samsung authors describes SystemVerilog real-number modeling for verification of a complex SSD power-management IC. The flow combined 25 models, randomized I2C programming, Python-based register checks, and 68 tests; the authors report a six-week implementation effort and simulation speedups of 100x to 1,000x over the referenced schematic simulations.", "sources": [ { "title": "Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex SSD PMIC", "url": "https://dvcon-proceedings.org/document/harnessing-sv-rnm-based-modelling-and-simulation-methodology-for-verifying-a-complex-pmic-designed-for-ssd-applications-2/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Samsung SSD PMIC real-number-modeling case study.", "status": "available", "archiveUrl": null }, { "title": "Harnessing SV-RNM Based Modelling and Simulation Methodology for Verifying a Complex SSD PMIC — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/Harnessing-SV-RNM-Based-Modelling-and-Simulation-Methodology-for-Verifying-a-Complex-PMIC-designed-for-SSD-Applications.pdf", "checkedAt": "2026-08-30", "summary": "The paper documents the RNM models, randomized I2C and Python checks, test count, effort, and reported speed range.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2022-ssd-pmic-sv-rnm-verification/" }, { "id": "siemens-eda-2022-sv-rnm-resolved-net-modeling", "when": { "start": "2022", "precision": "year" }, "kind": "technical", "companies": [ "siemens-eda" ], "people": [ "mariam-maurice" ], "headline": "Siemens author demonstrates capacitance-aware resolved nets and SV-RNM model debugging", "fact": "A DVCon U.S. 2022 paper by Siemens EDA's Mariam Maurice describes a SystemVerilog resolved-net model carrying voltage, previous voltage, current, capacitance, and resistance. It illustrates loading and filtering effects, real/logic boundary conversion, and interconnect debugging, with ADC, DAC, LDO, and image-sensor examples. The paper identifies UVM, assertions, and functional coverage as future verification work.", "sources": [ { "title": "DVCon archive record for Mariam Maurice's SV-RNM paper", "url": "https://dvcon-proceedings.org/document/modeling-analog-devices-using-sv-rnm-2/", "checkedAt": "2026-09-07", "summary": "Official proceedings index identifies the author, U.S. conference, 2022 year, and paper publication type.", "status": "available", "archiveUrl": null }, { "title": "Modeling Analog Devices using SV-RNM", "url": "https://dvcon-proceedings.org/wp-content/uploads/Modeling-Analog-Devices-using-SV-RNM-1.pdf", "checkedAt": "2026-09-07", "summary": "Paper identifies the Siemens affiliation and documents the capacitance-aware resolution function, boundary/interconnect inspection, device examples, and future verification work.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/siemens-eda-2022-sv-rnm-resolved-net-modeling/" }, { "id": "toshiba-2021-accu-rom-automotive-verification", "when": { "start": "2021-09-21", "precision": "day" }, "kind": "technical", "companies": [ "toshiba-electronic-devices-storage" ], "people": [], "headline": "Toshiba reports a reduced-order mixed-signal model for automotive heat and electromagnetic-interference verification", "fact": "Toshiba Electronic Devices & Storage published an automotive verification case using its Accu-ROM reduced-order modeling method to derive a VHDL-AMS model from SPICE behavior for an electric-power-steering system. Toshiba reports reducing the reference simulation from 32 hours 51 minutes to 3 hours 27 minutes while reproducing the compared motor-current, temperature, and electromagnetic-interference behavior.", "sources": [ { "title": "Toshiba Develops Mixed-Signal Simulation Technology for Automotive Semiconductors", "url": "https://toshiba.semicon-storage.com/jp/company/news/news-topics/2021/09/automotive-20210921-1.html", "checkedAt": "2026-08-30", "summary": "Toshiba's September 2021 announcement describes its Accu-ROM mixed-signal simulation technology and automotive application.", "status": "available", "archiveUrl": null }, { "title": "Fast Mixed-Signal Simulation Technology Using Reduced-Order Modeling", "url": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss-v3/master/en/company/technical-review/pdf/76-05_F02_E_r.pdf", "checkedAt": "2026-08-30", "summary": "Toshiba's technical review documents the VHDL-AMS reduced-order model, electric-power-steering case, timing comparison, and correlated behaviors.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/toshiba-2021-accu-rom-automotive-verification/" }, { "id": "scientific-analog-2021-09-pipelined-adc-model-generation", "when": { "start": "2021-09-15", "precision": "day" }, "kind": "technical", "companies": [ "scientific-analog" ], "people": [ "jaeha-kim" ], "headline": "Jaeha Kim explains structural and functional SystemVerilog model generation using a pipelined ADC", "fact": "In an IEEE Silicon Valley SSCS-sponsored webinar, Jaeha Kim explains automatic SystemVerilog model extraction using a pipelined ADC example. Structural modeling maps circuit devices and connectivity into models, retaining a low abstraction level that limits speed improvement. Functional modeling maps selected circuit regions to predefined templates and requires manual input. The resource record lists a recording and slides. This is a demonstrated modeling workflow, not evidence of fully automatic abstraction of arbitrary analog circuits or deployment at a named customer.", "sources": [ { "title": "Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example — webinar record", "url": "https://www.scianalog.com/webinars/w20210915/", "checkedAt": "2026-10-25", "summary": "The September 15 record describes both approaches, their abstraction/manual-input tradeoffs and recording resources.", "status": "available", "archiveUrl": null }, { "title": "Scientific Analog announcement of the IEEE SSCS webinar", "url": "https://www.scianalog.com/news/webinar-02/", "checkedAt": "2026-10-25", "summary": "The September 3 announcement names IEEE Silicon Valley SSCS sponsorship and the September 15 event time, distinguishing news from presentation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2021-09-pipelined-adc-model-generation/" }, { "id": "infineon-stanford-2021-open-source-ams-fpga-framework", "when": { "start": "2021-08-04", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "gabriel-rutsch" ], "headline": "Stanford and Infineon authors publish an open-source framework for mixed-signal FPGA emulation", "fact": "Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, and Mark Horowitz published a framework combining msdsl model generation, svreal synthesizable fixed- and floating-point representations, and anasymod FPGA build and control automation. The paper demonstrates a DragonPHY receiver, a firmware-controlled flyback converter, and an NFC-powered chip. Stanford dates publication to August 4, 2021; the TCAD journal issue is dated July 2022.", "sources": [ { "title": "Stanford AHA: Improved Validation publications", "url": "https://aha.stanford.edu/publications/improved-validation", "checkedAt": "2026-09-09", "summary": "Stanford's project bibliography dates this paper, DOI 10.1109/TCAD.2021.3102516, to August 4, 2021.", "status": "available", "archiveUrl": null }, { "title": "An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs — IEEE CEDA", "url": "https://ieee-ceda.org/media/open-source-framework-fpga-emulation-analogmixed-signal-integrated-circuit-designs", "checkedAt": "2026-09-09", "summary": "The publisher's society page describes msdsl, svreal, anasymod, the three applications, and the July 2022 TCAD issue. svreal supplies synthesizable numerical representations, not direct synthesis of ordinary SystemVerilog real variables.", "status": "available", "archiveUrl": null }, { "title": "Framework publication — Technical University of Munich research record", "url": "https://portal.fis.tum.de/en/publications/an-open-source-framework-for-fpga-emulation-of-analogmixed-signal/", "checkedAt": "2026-09-09", "summary": "The institutional publication record identifies the authors, Stanford and Infineon affiliations, DOI, and July 2022 journal issue.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-stanford-2021-open-source-ams-fpga-framework/" }, { "id": "research-2021-02-pll-metamorphic-verification-dead-zone", "when": { "start": "2021-02-04", "precision": "day" }, "kind": "technical", "companies": [], "people": [], "headline": "DATE authors use metamorphic relations to expose a PFD bug in a SystemC-AMS PLL model", "fact": "A DATE 2021 paper reports metamorphic testing of an industrial partner's SystemC-AMS PLL model. A relation between scaled reference and divided-feedback frequencies exposed a PFD dead-zone bug missed by existing tests: changing the reference from 1 MHz to 1.01 MHz produced 50 kHz feedback. The authors report restoring the relation after adding delay in the PFD reset path. This concerns a system-level model rather than a demonstrated silicon defect; the industrial partner is unnamed.", "sources": [ { "title": "System Level Verification of Phase-Locked Loop using Metamorphic Relations — DATE 2021 paper", "url": "https://past.date-conference.com/proceedings-archive/2021/pdf/1933.pdf", "checkedAt": "2026-10-09", "summary": "Full paper by Muhammad Hassan, Daniel Große and Rolf Drechsler describes SystemC-AMS, eight metamorphic relations, the frequency-scaling failure and the PFD reset-delay correction. It does not identify the industrial partner.", "status": "available", "archiveUrl": null }, { "title": "DATE 2021 official program: IP8_1.2", "url": "https://past.date-conference.com/proceedings-archive/2021/html/toc.html", "checkedAt": "2026-10-09", "summary": "Official program lists the presentation on February 4, 2021. This is the verified presentation date; the PDF first-upload date is not established.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/research-2021-02-pll-metamorphic-verification-dead-zone/" }, { "id": "analog-devices-2021-upf-dms-low-power-verification", "when": { "start": "2021", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices authors report UPF-based low-power verification in a digital mixed-signal flow", "fact": "A DVCon 2021 paper by Analog Devices authors describes combining SystemVerilog real-number models, RTL, and Unified Power Format for low-power digital mixed-signal verification. The environment checked supplies, isolation, level shifting, and power sequencing, and the authors report that it exposed a power-domain defect involving memory built-in self-test and a test-data register.", "sources": [ { "title": "Digital Mixed-Signal Low-Power Verification with Unified Power Format (UPF)", "url": "https://dvcon-proceedings.org/document/digital-mixed-signal-low-power-verification-with-unified-power-format-upf/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Analog Devices paper on combining digital mixed-signal verification with UPF.", "status": "available", "archiveUrl": null }, { "title": "Digital Mixed-Signal Low-Power Verification with Unified Power Format — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/digital-mixed-signal-low-power-verification-with-unified-power-format-upf.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the SV-RNM, RTL, and UPF environment, low-power checks, and reported power-domain defect.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2021-upf-dms-low-power-verification/" }, { "id": "microchip-2021-uvm-udn-upf-agents", "when": { "start": "2021", "precision": "year" }, "kind": "technical", "companies": [ "microchip" ], "people": [ "chuck-mcclish" ], "headline": "Microchip author reports reusable UVM agents for UDN and UPF analog stimulus", "fact": "A Microchip-authored paper reports bidirectional UVM agents for SystemVerilog user-defined nettypes and UPF supply-net pins. The agents generate static and time-varying analog stimulus, monitor values, and are configured through reusable objects; the paper reports using the approach with the three largest simulators and discusses portability differences among them.", "sources": [ { "title": "Bi-Directional UVM Agents and Complex Stimulus Generation for UDN and UPF Pins", "url": "https://dvcon-proceedings.org/wp-content/uploads/bi-directional-uvm-agents-and-complex-stimulus-generation-for-udn-and-upf-pins.pdf", "checkedAt": "2026-08-30", "summary": "2021 Microchip paper describing reusable UVM agents, analog waveform generation, monitoring, configuration, and simulator portability for UDN and UPF pins.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/microchip-2021-uvm-udn-upf-agents/" }, { "id": "samsung-2021-ddr4-3ds-channel-model-verification", "when": { "start": "2021", "precision": "year" }, "kind": "technical", "companies": [ "samsung" ], "people": [], "headline": "Samsung authors report a configurable channel model for DDR4-3DS PHY verification", "fact": "Samsung Semiconductor India authors report an in-house parameterized channel model integrated into a DDR-PHY verification environment for DDR4-3DS memory. The model injects routing and board delays, skew, crosstalk distortion, duty-cycle variation, setup and hold stress, and glitches; the paper says it enabled RTL-level training-algorithm checks and led to RTL and specification updates in reported cases.", "sources": [ { "title": "Robust Physical Layer IP Verification for DDR4-3DS Memory by Channel Modelling", "url": "https://dvcon-proceedings.org/wp-content/uploads/robust-physical-layer-ip-verification-for-ddr4-3ds-memory-by-channel-modelling.pdf", "checkedAt": "2026-08-31", "summary": "The Samsung-authored DVCon paper describes the in-house DDR channel model, its configurable electrical and timing stress features, integration with functional checks and coverage, and reported RTL and specification updates.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-2021-ddr4-3ds-channel-model-verification/" }, { "id": "texas-instruments-2021-ate-analog-fault-simulation", "when": { "start": "2021", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "jun-yan" ], "headline": "TI presenter runs an actual C++ ATE program in analog fault simulation", "fact": "A CadenceLIVE presentation by TI's Jun Yan describes running C++ automatic-test-equipment test logic in analog fault simulation through the SystemVerilog DPI-C interface. The flow runs faults at sub-block level, parses simulation logs, presents pass-or-fail results in the Cadence environment, and is described as a joint effort among design verification, ATE, and design teams.", "sources": [ { "title": "Check Analog Fault Simulation with Actual ATE Program", "url": "https://www.cadence.com/ko_KR/home/cadence-live/2021/korea/repository.html", "checkedAt": "2026-08-30", "summary": "CadenceLIVE 2021 program entry and abstract for Jun Yan's TI presentation on connecting an actual C++ ATE program to analog fault simulation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2021-ate-analog-fault-simulation/" }, { "id": "texas-instruments-2021-eenet-charge-pump-modeling", "when": { "start": "2021", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [], "headline": "TI authors report an EEnet charge-pump regulator model checked against schematic load steps", "fact": "Texas Instruments authors present a SystemVerilog EEnet model of a charge-pump regulator that represents voltage, current, and resistance and includes analog impedance interactions. The poster reports matching the schematic at 1 mA, 2 mA, 3 mA, and 4 mA load-current steps, a model runtime of 10.36 seconds, and a tenfold speedup over the schematic simulation used for comparison.", "sources": [ { "title": "Accurate Charge-pump Regulator Modeling using SV EEnet", "url": "https://dvcon-proceedings.org/wp-content/uploads/NO_002-accurate-charge-pump-regulator-modeling-using-sv-eenet.pdf", "checkedAt": "2026-08-31", "summary": "The TI-authored DVCon poster describes the EEnet charge-pump model and reports the four schematic load-step checks, 10.36-second model runtime, and 10x speedup.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2021-eenet-charge-pump-modeling/" }, { "id": "samsung-snu-2020-09-nand-sensing-xmodel-announcement", "when": { "start": "2020-09-01", "precision": "day" }, "kind": "technical", "companies": [ "samsung" ], "people": [], "headline": "Scientific Analog announces an SNU/Samsung NAND-sensing SystemVerilog modeling paper", "fact": "Scientific Analog announces acceptance at ICCAD 2020 of Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations, identifying researchers affiliated with Seoul National University and Samsung. The announcement describes SystemVerilog/XMODEL models tracking cell threshold voltages while exercising read, program and erase algorithms. It reports a 40-microsecond incremental-step-pulse-programming simulation of a 12-Kb single-level-cell block in under two minutes, without specifying the host setup. September 1 is the announcement date; a November 3 conference presentation was planned. Full paper access was unavailable in this check, so author details, silicon correlation and broader performance are not asserted. Scientific Analog is the announcing tool vendor, not an identified research-author affiliation.", "sources": [ { "title": "Seoul National University and Samsung Electronics to Present XMODEL-based Verification Framework for NAND Flash Memory Sensing Systems at ICCAD 2020", "url": "https://www.scianalog.com/news/iccad-2020/", "checkedAt": "2026-10-25", "summary": "The September 1 company announcement identifies the research institutions, accepted title, planned November 3 presentation and bounded 12-Kb/40-microsecond runtime claim. Full paper and host conditions were not available for review.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/samsung-snu-2020-09-nand-sensing-xmodel-announcement/" }, { "id": "dialog-semiconductor-2020-chip-level-analog-regressions", "when": { "start": "2020", "precision": "year" }, "kind": "technical", "companies": [ "renesas" ], "people": [], "headline": "Dialog Semiconductor author reports production chip-level analog regressions", "fact": "A 2020 CadenceLIVE paper by Dialog Semiconductor's Yi Wang describes a programmable Verilog-AMS testbench with SystemVerilog Assertions and an asynchronous state machine for chip-level analog regressions. The paper reports more than 30 scenarios and 156 runs completing in 9.5 hours for daily signoff; Cadence's conference repository says the simulated results were subsequently supported by silicon measurements.", "sources": [ { "title": "CadenceLIVE Europe 2020 Proceedings", "url": "https://www.cadence.com/en_US/home/cadence-live/2020/europe/repository.html", "checkedAt": "2026-08-30", "summary": "Cadence's conference repository lists Yi Wang of Dialog Semiconductor and summarizes the chip-level analog-regression work and silicon-measurement follow-up.", "status": "available", "archiveUrl": null }, { "title": "Chip-Level Analog Regressions in Production", "url": "https://dvcon-proceedings.org/wp-content/uploads/chiplevel-analog-regressions-in-production-paper.pdf", "checkedAt": "2026-08-30", "summary": "The Dialog paper documents the programmable testbench, assertions, scenario count, regression volume, and reported runtime.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/dialog-semiconductor-2020-chip-level-analog-regressions/" }, { "id": "dialog-semiconductor-2020-unified-rtl-dms-ams-testbench", "when": { "start": "2020", "precision": "year" }, "kind": "technical", "companies": [ "renesas", "cadence" ], "people": [ "peter-grove" ], "headline": "Dialog Semiconductor and Cadence report a unified RTL, DMS, and AMS testbench flow", "fact": "At CadenceLIVE Europe 2020, Dialog Semiconductor's Peter Grove described work with Cadence R&D on a unified testbench and an LRM-compliant SystemVerilog netlister spanning RTL, digital mixed-signal, and analog/mixed-signal simulation. This is a dated Dialog Semiconductor record and does not imply methodology transfer to Grove's later affiliations.", "sources": [ { "title": "CadenceLIVE Europe 2020 Proceedings", "url": "https://www.cadence.com/en_US/home/cadence-live/2020/europe/repository.html", "checkedAt": "2026-08-30", "summary": "Cadence's conference repository lists Peter Grove of Dialog Semiconductor and the unified RTL, DMS, and AMS testbench presentation.", "status": "available", "archiveUrl": null }, { "title": "A Mixed-Signal Universal Testbench for RTL/DMS/AMS (UTB)", "url": "https://www.tessolve.com/a-mixed-signal-universal-testbench-for-rtl-dms-ams-utb/", "checkedAt": "2026-08-30", "summary": "Grove's later technical article describes the unified testbench, Cadence R&D collaboration, SystemVerilog netlister, and common RTL/DMS/AMS flow.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/dialog-semiconductor-2020-unified-rtl-dms-ams-testbench/" }, { "id": "infineon-2020-mixed-signal-fpga-prototyping", "when": { "start": "2020", "precision": "year" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "gabriel-rutsch" ], "headline": "Infineon and Stanford authors report FPGA prototypes for mixed-signal magnetic sensors", "fact": "A DVCon Europe paper led by Gabriel Rutsch reports two FPGA prototypes for automotive magnetic sensors, using msdsl to generate synthesizable analog functional models and anasymod for FPGA build and control. One prototype supports real-time hardware-in-the-loop and customer integration; the other accelerates regression testing. The paper describes their use across product definition, verification, and design-in.", "sources": [ { "title": "Boosting Mixed-Signal Design Productivity with FPGA-Based Methods throughout the Chip Design Process", "url": "https://dvcon-proceedings.org/document/boosting-mixed-signal-design-productivity-with-fpga-based-methods-throughout-the-chip-design-process/", "checkedAt": "2026-09-09", "summary": "The official DVCon archive identifies the paper, its authors, and the 2020 Europe conference year.", "status": "available", "archiveUrl": null }, { "title": "Mixed-signal FPGA prototyping — DVCon Europe paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/boosting-mixed-signal-design-productivity-with-fpga-based-methods-throughout-the-chip-design-process.pdf", "checkedAt": "2026-09-09", "summary": "The Infineon and Stanford paper describes the magnetic-sensor prototypes, msdsl/anasymod flow, real-time integration and regression use cases, and synthesizable numerical models.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2020-mixed-signal-fpga-prototyping/" }, { "id": "ecosystem-2019-11-uvm-ams-working-group", "when": { "start": "2019-11-19", "precision": "day" }, "kind": "technical", "companies": [], "people": [ "patrick-lynch" ], "headline": "Accellera forms the UVM-AMS Working Group to standardize mixed-signal UVM extensions", "fact": "Accellera formed the UVM-AMS Working Group on November 19, 2019 after a proposed-working-group phase that began with a May 2019 meeting in Munich, naming Patrick Lynch as chair. The charter targeted a unified UVM-based analog/mixed-signal verification methodology, including standardized driving and monitoring of mixed-signal nets, stimulus, scoreboarding and analysis, plus a framework for reusable analog/mixed-signal verification components derived from digital-centric verification IP. Accellera said the planned standard was intended to support ready-to-use analog/mixed-signal verification IP from tool and IP providers.", "sources": [ { "title": "UVM-AMS Working Group Formed to Standardize UVM Analog/Mixed-Signal Extensions", "url": "https://www.accellera.org/news/press-releases/286-uvm-ams-working-group-formed-to-standardize-uvm-analog-mixed-signal-extensions", "checkedAt": "2026-09-02", "summary": "Accellera's November 19, 2019 announcement names Patrick Lynch as UVM-AMS Working Group chair, defines the charter, describes its May 2019 proposed-working-group precursor, and states the goal of reusable AMS verification components and ready-to-use AMS verification IP.", "status": "available", "archiveUrl": null }, { "title": "UVM-AMS: a UVM-Based Analog Verification Standard", "url": "https://2021.dvcon.org/presentation/workshop/uvm-ams-uvm-based-analog-verification-standard.html", "checkedAt": "2026-09-02", "summary": "The official DVCon U.S. 2021 workshop record identifies Patrick Lynch of Xilinx among the key Accellera UVM-AMS Working Group members, corroborating the public identity linked to the 2019 chair role.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ecosystem-2019-11-uvm-ams-working-group/" }, { "id": "infineon-2019-virtual-ate-pre-silicon-test-program", "when": { "start": "2019-07-15", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon case study runs the same test program on virtual and physical ATE before first silicon", "fact": "A JKU/Infineon paper presented a virtual ATE flow that executes production-style test programs against a SystemC/SystemC-AMS virtual DUT before first silicon. In an Infineon ASIC case study, the same test program was run on the virtual ATE and later on a Teradyne UltraFLEX system, exposing the same register-test error; the authors report that this enabled test-program checks months earlier than the conventional flow.", "sources": [ { "title": "Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows", "url": "https://www.cda.cit.tum.de/files/eda/2019_isvlsi_virtual_test_for_industrial_design_flows.pdf", "checkedAt": "2026-09-02", "summary": "Full paper describing a SystemC/SystemC-AMS virtual ATE methodology and an Infineon ASIC case using the same test program on virtual and Teradyne UltraFLEX targets.", "status": "available", "archiveUrl": null }, { "title": "Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows", "url": "https://portal.fis.tum.de/en/publications/test-your-test-programs-pre-silicon-a-virtual-test-methodology-fo-2/", "checkedAt": "2026-09-02", "summary": "TUM publication record for the ISVLSI 2019 paper and conference dates.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2019-virtual-ate-pre-silicon-test-program/" }, { "id": "stmicroelectronics-2019-05-tdp-intern-ldo-verification", "when": { "start": "2019-05-30", "precision": "day" }, "kind": "technical", "companies": [ "stmicroelectronics" ], "people": [], "headline": "STMicroelectronics intern reports SV-UVM LDO verification from its Greater Noida TDP team", "fact": "A paper by Subhranshu Shekhar Padhee and Thapar’s Anil Arora reports LDO functional verification with a self-checking SystemVerilog/UVM testbench, Cadence Incisive and Synopsys VCS, including code, functional and cross coverage. The author biography identifies Padhee as an intern in STMicroelectronics’ Greater Noida Technology Designing Platform team working on analog and mixed-signal IP verification. This records the published internship-related technical work and contemporaneous company affiliation, not a current organization chart or adoption of the later UVM-MS standard.", "sources": [ { "title": "Verification of Analog & Mixed Signal IPs Using SV-UVM Methodology — paper", "url": "https://www.ijitee.org/wp-content/uploads/papers/v8i7/G5928058719.pdf", "checkedAt": "2026-11-07", "summary": "The May 2019 paper describes LDO checking and coverage. The page 1543 biography explicitly places Padhee in STMicroelectronics’ Greater Noida TDP internship; Anil Arora’s affiliation is Thapar, not STMicroelectronics.", "status": "available", "archiveUrl": null }, { "title": "IJITEE: publication record for G5928058719", "url": "https://www.ijitee.org/portfolio-item/G5928058719/", "checkedAt": "2026-11-07", "summary": "The publisher explicitly gives manuscript publication as May 30, 2019. This is the paper date, distinct from a thesis submission/upload date or the internship’s employment period.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/stmicroelectronics-2019-05-tdp-intern-ldo-verification/" }, { "id": "analog-devices-2019-power-aware-rnm-verification", "when": { "start": "2019", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [ "jakub-dudek" ], "headline": "Analog Devices authors report power-aware RNM verification with schematic correlation", "fact": "An Analog Devices-authored presentation reports power-aware RNM models used with UVM supply and interrupt agents and assertions. It describes validating models against schematics, scripting chip-top connectivity, and running RNM with RTL; the authors report finding isolation and sequencing bugs and closing coverage without mixed-signal co-simulation for those full-chip tests.", "sources": [ { "title": "Taking RNM Model to the Next Level: Power-Aware Verification of Mixed-Signal Designs", "url": "https://dvcon-proceedings.org/document/taking-rnm-model-to-the-next-level-power-aware-verification-of-mixed-signal-designs/", "checkedAt": "2026-08-30", "summary": "2019 Analog Devices presentation on power-aware RNM, model-to-schematic validation, scripted integration, assertions, and coverage.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2019-power-aware-rnm-verification/" }, { "id": "broadcom-2019-uvm-dms-ams-methodology", "when": { "start": "2019", "precision": "year" }, "kind": "technical", "companies": [ "broadcom" ], "people": [], "headline": "Broadcom authors report a reusable full-chip UVM DMS/AMS methodology", "fact": "A Broadcom-authored paper reports a full-chip, coverage-driven constrained-random UVM environment for mixed-signal SoCs. It describes selectable analog abstraction through SystemVerilog user-defined nettypes, Verilog-AMS, transistor-level, or mixed views, with interface UVCs, scoreboards, assertions, checkers, and coverage reused across configurations; the authors also report analog-digital and schematic bug findings.", "sources": [ { "title": "Scalable, Re-usable UVM DMS AMS Based Verification Methodology for Mixed-Signal SoCs", "url": "https://dvcon-proceedings.org/document/scalable-re-usable-uvm-dms-ams-based-verification-methodology-for-mixed-signal-socs/", "checkedAt": "2026-08-30", "summary": "2019 DVCon paper by Broadcom authors describing reusable full-chip UVM environments across DMS, AMS, and transistor-level representations.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/broadcom-2019-uvm-dms-ams-methodology/" }, { "id": "intel-2019-serdes-uvm-mixed-signal-verification", "when": { "start": "2019", "precision": "year" }, "kind": "technical", "companies": [ "intel" ], "people": [], "headline": "Intel authors report a UVM framework for SerDes mixed-signal behavioral-model verification", "fact": "Intel of Canada authors report a UVM verification framework for a SerDes physical-media-attachment layer that spans fast, accurate, and AMS-mode behavioral models. The presented framework uses translator blocks between real and logic data, layered adapter sequences, common end-to-end checkers, and configurable NRZ/PAM4 stimulus, with the authors reporting reuse across model modes and improved verification of pre-emphasis and equalization behavior.", "sources": [ { "title": "Translating and Adapting to the 'real' world: SerDes Mixed Signal Verification using UVM", "url": "https://dvcon-proceedings.org/document/translating-and-adapting-to-the-real-world-serdes-mixed-signal-verification-using-uvm/", "checkedAt": "2026-09-02", "summary": "The DVCon archive dates the Intel of Canada paper to 2019 and identifies Akhila Madhu Kumar and Karl Herterich as its authors.", "status": "available", "archiveUrl": null }, { "title": "Translating and Adapting to the 'real' world: SerDes Mixed Signal Verification using UVM — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/translating-and-adapting-to-the-real-world-serdes-mixed-signal-verification-using-uvm.pdf", "checkedAt": "2026-09-02", "summary": "The paper details the behavioral-model modes, real-to-logic translators, UVM adapter sequences, NRZ/PAM4 configuration, and reported verification results.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/intel-2019-serdes-uvm-mixed-signal-verification/" }, { "id": "roche-2019-complex-udn-mixed-signal-verification", "when": { "start": "2019", "precision": "year" }, "kind": "technical", "companies": [ "roche-sequencing-solutions" ], "people": [], "headline": "Roche Sequencing authors report complex SystemVerilog UDNs for mixed-signal verification", "fact": "A DVCon 2019 paper by Roche Sequencing Solutions authors presents a structured SystemVerilog user-defined nettype with runtime port resolution and waveform-viewer support. In a SAR ADC case, the authors report 1,183.3 seconds for the referenced SPICE simulation versus 4.7 seconds for the real-number model and say the flow exposed an incorrect MSB capacitor-switch polarity.", "sources": [ { "title": "Novel Mixed-Signal Verification Methodology Using Complex UDNs", "url": "https://dvcon-proceedings.org/document/novel-mixed-signal-verification-methodology-using-complex-udns/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Roche Sequencing Solutions paper on complex SystemVerilog user-defined nettypes.", "status": "available", "archiveUrl": null }, { "title": "Novel Mixed-Signal Verification Methodology Using Complex UDNs — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/novel-mixed-signal-verification-methodology-using-complex-udns.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the structured UDN, runtime resolution, GUI support, SAR ADC timing comparison, and reported polarity defect.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/roche-2019-complex-udn-mixed-signal-verification/" }, { "id": "texas-instruments-2019-eenet-loading-verification", "when": { "start": "2019", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [], "headline": "Texas Instruments authors report EEnet loading models for digital mixed-signal power verification", "fact": "A DVCon 2019 paper by Texas Instruments authors describes using a SystemVerilog user-defined EEnet to model voltage, current, and resistance loading in power-regulation verification. The UVM-based flow randomized supplies, loads, and system states, supported reusable DMS and AMS environments, and extended verification to loading effects that simple voltage-only real-number interfaces could not represent.", "sources": [ { "title": "Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation Using a SystemVerilog User-Defined Nettype", "url": "https://dvcon-proceedings.org/wp-content/uploads/enabling-digital-mixed-signal-verification-of-loading-effects-in-power-regulation-using-systemveriloguser-defined-nettyp.pdf", "checkedAt": "2026-08-30", "summary": "The Texas Instruments paper defines the EEnet loading model and describes randomized, reusable UVM-based DMS and AMS power-regulation verification.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2019-eenet-loading-verification/" }, { "id": "nxp-infineon-2018-uvm-ms-standardization-ideas", "when": { "start": "2018-10-24", "precision": "day" }, "kind": "technical", "companies": [ "infineon", "nxp" ], "people": [ "sebastian-simon" ], "headline": "NXP and Infineon present UVM mixed-signal practices and standardization needs", "fact": "At DVCon Europe 2018, NXP and Infineon presented company practices for extending UVM into mixed-signal verification. NXP described analog/mixed-signal verification-component and UVC concepts and identified a need for flexible APIs between physical and signal layers, including a common interface for third-party VIP; Infineon presented its A-UVM analog extension with real-valued transactions, constrained-random stimulus, automated analog checks, waveform comparison, functional coverage, and an IGBT gate-driver application. The tutorial explicitly asked whether an Accellera UVM-AMS working group should be created, and Accellera later stated that DVCon Europe discussions resulted in creation of the proposed working group.", "sources": [ { "title": "UVM mixed signal extensions — Sharing Best Practice and Standardization Ideas", "url": "https://dvcon-proceedings.org/wp-content/uploads/UVM-mixed-signal-extensionsSharing-Best-Practice-and-Standardization-Ideas.pdf", "checkedAt": "2026-09-02", "summary": "DVCon Europe 2018 tutorial by NXP and Infineon presenting UVM mixed-signal practices, missing API and standardization needs, A-UVM features and an IGBT gate-driver case, and discussion of a possible Accellera UVM-AMS working group.", "status": "available", "archiveUrl": null }, { "title": "Accellera Community Newsletter: September 2019", "url": "https://www.accellera.org/news/newsletters/2019-september", "checkedAt": "2026-09-02", "summary": "Accellera states that multiple discussions at DVCon Europe the previous year resulted in creation of the UVM-AMS Proposed Working Group.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-infineon-2018-uvm-ms-standardization-ideas/" }, { "id": "apple-2018-10-toshi-kawashima-dms-verification", "when": { "start": "2018-10", "precision": "month" }, "kind": "organizational", "companies": [ "apple" ], "people": [ "toshi-kawashima" ], "headline": "Toshi Kawashima's profile dates an Apple DMS verification role to October 2018", "fact": "Toshi Kawashima's public professional profile dates the start of his Apple role as Manager, DMS (Digital Mixed-Signal) Design Verification to October 2018 and says he leads a team responsible for DMS and AMS verification and methodology work across mixed-signal LSI projects.", "sources": [ { "title": "Toshi Kawashima — LinkedIn", "url": "https://jp.linkedin.com/in/toshi532", "checkedAt": "2026-08-30", "summary": "Kawashima's public professional profile dates his Apple DMS design-verification manager role to October 2018 and describes the team's verification and methodology responsibilities.", "status": "available", "archiveUrl": null } ], "affiliationChange": { "person": "toshi-kawashima", "from": null, "to": "apple" }, "recordUrl": "https://ams-signals.com/events/apple-2018-10-toshi-kawashima-dms-verification/" }, { "id": "scientific-analog-2018-03-glister-virtuoso-ade-integration", "when": { "start": "2018-03-31", "precision": "day" }, "kind": "technical", "companies": [ "scientific-analog", "cadence" ], "people": [], "headline": "Scientific Analog announces GLISTER integration with Cadence Virtuoso ADE", "fact": "Scientific Analog announces that the official XMODEL 2018.03 release integrates GLISTER features into Cadence Virtuoso Analog Design Environment. The announced interface supports composing testbenches, generating netlists and launching XMODEL simulations through ADE menus and commands. The company attributes the integration to its partnership with Cadence through the Connections EDA Program. March 31 is the announcement date; the version label does not establish another release day. The announcement establishes workflow integration, not functional equivalence with SPICE or a customer performance result.", "sources": [ { "title": "GLISTER-ADE Integration Released", "url": "https://www.scianalog.com/news/glister-ade/", "checkedAt": "2026-10-25", "summary": "The dated release announcement names XMODEL 2018.03, the three ADE workflow operations and the Cadence Connections partnership.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2018-03-glister-virtuoso-ade-integration/" }, { "id": "infineon-2018-automated-rnm-generation-validation", "when": { "start": "2018", "precision": "year" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "sebastian-simon" ], "headline": "Infineon authors report automated generation and validation of real-number models and UVM-MS testbenches", "fact": "A DVCon 2018 paper by Infineon authors describes a meta-model-driven flow that automatically generates real-number models and UVM-MS testbench components. In its mixed-signal ADC case, the generated RNM ran in 4.5 seconds versus 74.1 seconds for the referenced VHDL model, and the generated testbench exposed a deadlock in the analog implementation.", "sources": [ { "title": "Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal Verification", "url": "https://dvcon-proceedings.org/document/methodology-for-automated-generation-and-validation-of-analog-behavioral-models-for-mixed-signal-verification/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Infineon work on automated RNM and UVM-MS generation and validation.", "status": "available", "archiveUrl": null }, { "title": "Methodology for Automated Generation and Validation of Analog Behavioral Models — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/methodology-for-automated-generation-and-validation-of-analog-behavioral-models-for-mixed-signal-verification.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the meta-model flow, reported MADC simulation timings, and analog-implementation deadlock found by the generated testbench.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2018-automated-rnm-generation-validation/" }, { "id": "nxp-2018-automotive-ethernet-uvm-ms", "when": { "start": "2018", "precision": "year" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "marcel-oosterhuis" ], "headline": "NXP authors extend one UVM environment across the digital and analog sides of an automotive Ethernet PHY", "fact": "An NXP-authored paper reports verifying an IEEE 802.3bw 100BASE-T1 PHY with one UVM environment extended to handle its analog interface. The environment adds analog source and probe components, error injection, and analog-domain coverage while retaining the digital UVM register-model environment; the authors demonstrate the approach on a released automotive Ethernet PHY.", "sources": [ { "title": "Protocol Verification of an IEEE 802.3bw PHY: Application of Mixed-Signal Extensions to a UVM Verification Environment", "url": "https://dvcon-proceedings.org/wp-content/uploads/protocol-verification-of-an-ieee-802-3bw-phy-application-of-mixed-signal-extensions-to-an-uvm-verification-environment.pdf", "checkedAt": "2026-08-30", "summary": "2018 NXP paper describing a UVM environment spanning the digital and analog interfaces of an automotive Ethernet PHY.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2018-automotive-ethernet-uvm-ms/" }, { "id": "sk-hynix-2018-dram-peripheral-model-verification", "when": { "start": "2018", "precision": "year" }, "kind": "technical", "companies": [ "sk-hynix", "scientific-analog" ], "people": [], "headline": "SK hynix, SNU and Scientific Analog describe automatically generated DRAM peripheral models", "fact": "A 2018 DAC Designer/IP Track case study concerns analog/mixed-signal verification of DRAM peripherals with automatically generated SystemVerilog models. Scientific Analog’s announcement identifies joint work with SK hynix and Seoul National University, describes MODELZEN model generation followed by XMODEL simulation, and schedules a June 27 poster. SNU’s laboratory publication list independently records the 2018 work. The accessible sources establish the modeling flow and participants, but do not establish quantitative accuracy, speedup, silicon correlation or company-wide deployment. The Event retains year precision rather than treating the advance announcement as proof of the actual presentation day.", "sources": [ { "title": "SNU MICS Group publication list: Analog/Mixed-Signal Verification of DRAM Peripherals with Automatically-Generated System Verilog Models", "url": "https://mics.snu.ac.kr/people.html", "checkedAt": "2026-10-25", "summary": "Jiho Lee’s publication list records the Yinjae Lee, Jiho Lee et al. DAC IP/DT Track work in 2018.", "status": "available", "archiveUrl": null }, { "title": "SK Hynix to Present DRAM Verification Flow Based on XMODEL at DAC 2018 Designer Track", "url": "https://www.scianalog.com/news/skhynix-dac2018/", "checkedAt": "2026-10-25", "summary": "The April 19 advance announcement explicitly identifies joint SK hynix/SNU/Scientific Analog work, MODELZEN and XMODEL, and a planned June 27 poster; no quantitative result is given.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/sk-hynix-2018-dram-peripheral-model-verification/" }, { "id": "analog-devices-2017-rf-transceiver-soc-verification", "when": { "start": "2017", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [ "jakub-dudek" ], "headline": "Analog Devices authors report RNM and generated UVM testbenches for a 2.4 GHz transceiver SoC", "fact": "An Analog Devices-authored paper reports verification of a 2.4 GHz BLE and proprietary-mode transceiver SoC using UVM RF agents, real-number models, randomized packet parameters and blockers, and full-system pads-to-RTL simulation. The paper also describes Veri-DSP, an internal flow that generated UVM block testbenches and integrated Python post-processing for DSP verification.", "sources": [ { "title": "Advances in RF Transceiver SoC Verification", "url": "https://dvcon-proceedings.org/document/advances-in-rf-transceiver-soc-verification-a-walk-through-over-a-2-4-ghz-multi-modal-integrated-transceiver-verification-cycle/", "checkedAt": "2026-08-30", "summary": "2017 Analog Devices paper covering UVM, RF agents, RNM, full-system verification, and the Veri-DSP testbench-generation flow.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2017-rf-transceiver-soc-verification/" }, { "id": "cadence-2017-uvm-mixed-signal-serdes", "when": { "start": "2017", "precision": "year" }, "kind": "technical", "companies": [ "cadence" ], "people": [], "headline": "Cadence authors describe reusing a digital UVM environment for mixed-signal SerDes verification", "fact": "A Cadence-authored paper reports reusing a digital UVM environment for mixed-signal verification of a Type-C USB and SerDes design. It describes analog-parameter agents, scoreboards and checkers, and added functional coverage and verification-plan content; the evidence documents a vendor-authored methodology rather than customer adoption.", "sources": [ { "title": "Mixed-Signal Verification Methodology to Verify Type-C USB", "url": "https://dvcon-proceedings.org/document/mixed-signal-verification-methodology-to-verify-type-c-usb/", "checkedAt": "2026-08-30", "summary": "Cadence-authored 2017 paper on extending a digital UVM environment to mixed-signal Type-C USB and SerDes verification.", "status": "available", "archiveUrl": null }, { "title": "Efficient Verification of Mixed-Signal SerDes IP Using UVM", "url": "https://www.cadence.com/en_US/home/resources/white-papers/efficient-verification-of-mixed-signal-series-ip-using-uvm-wp.html", "checkedAt": "2026-08-30", "summary": "Cadence's companion methodology page for UVM-based mixed-signal SerDes IP verification.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2017-uvm-mixed-signal-serdes/" }, { "id": "texas-instruments-2017-analog-assertions-and-pvt-ml", "when": { "start": "2017", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "zhipeng-ye" ], "headline": "TI authors report schematic-bound analog assertions and machine-learning-guided PVT exploration", "fact": "Two TI-authored 2017 papers report methods for analog and mixed-signal verification. One binds assertions directly to electrical ports in a schematic; the other applies support vector machines and active learning to adaptively explore process, voltage, and temperature space for coverage and worst-case conditions.", "sources": [ { "title": "Assertion-Based Verification for Analog and Mixed-Signal Designs", "url": "https://dvcon-proceedings.org/document/assertion-based-verification-for-analog-and-mixed-signal-designs/", "checkedAt": "2026-08-30", "summary": "TI-authored 2017 paper on binding assertions to schematic electrical ports for analog and mixed-signal verification.", "status": "available", "archiveUrl": null }, { "title": "Machine Learning-Based PVT Space Coverage and Worst-Case Exploration in Analog and Mixed-Signal Design Verification", "url": "https://dvcon-proceedings.org/document/machine-learning-based-pvt-space-coverage-and-worst-case-exploration-in-analog-and-mixed-signal-design-verification-presentation/", "checkedAt": "2026-08-30", "summary": "TI-authored 2017 work applying support vector machines and active learning to PVT coverage and worst-case exploration.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2017-analog-assertions-and-pvt-ml/" }, { "id": "dialog-semiconductor-2016-mixed-signal-model-validation", "when": { "start": "2016-10-20", "precision": "day" }, "kind": "technical", "companies": [ "renesas" ], "people": [ "carsten-wegener" ], "headline": "Dialog Semiconductor author presents a model-validation process for chip-level mixed-signal verification", "fact": "Dialog Semiconductor's Carsten Wegener, listed with PMIC Analog in Germering, presents a model-validation process for analog behavioral models used in event-driven chip-level mixed-signal verification. The paper argues that modeling requires an associated validation process and demonstrates the approach on a mixed-signal digital I/O buffer treated as a 1-bit DAC and ADC, using post-handoff model bugs and issues as one measure of model quality.", "sources": [ { "title": "Model Validation for Mixed-Signal Verification: The Importance of Being Earnest about Modeling", "url": "https://dvcon-proceedings.org/wp-content/uploads/model-validation-for-mixed-signal-verification-the-importance-of-being-earnest-about-modeling.pdf", "checkedAt": "2026-08-30", "summary": "Wegener's DVCon Europe paper identifies his Dialog Semiconductor PMIC Analog affiliation in Germering and presents a validation process for behavioral models used in event-driven chip-level mixed-signal verification.", "status": "available", "archiveUrl": null }, { "title": "DVCon Europe 2016 conference program", "url": "https://dvcon-proceedings.org/wp-content/uploads/2016-dvcon-eu-program.pdf", "checkedAt": "2026-08-30", "summary": "The official program places Wegener's Dialog Semiconductor presentation in Session 8, Mixed-Signal Verification, on Thursday, October 20, 2016.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/dialog-semiconductor-2016-mixed-signal-model-validation/" }, { "id": "scientific-analog-2016-08-snu-idec-analog-cell-library", "when": { "start": "2016-08-08", "precision": "day" }, "kind": "technical", "companies": [ "scientific-analog" ], "people": [ "jaeha-kim" ], "headline": "Scientific Analog reports SNU/IDEC analog-cell library distribution with XMODEL PLL verification", "fact": "Scientific Analog reports an August 8, 2016 announcement by Seoul National University’s MICS Group of an Analog Cell Library and reference flow released through IDEC. The flow uses XMODEL for PLL behavior/performance simulation and Synopsys IC Compiler for physical implementation. The reported Samsung 65-nm library supports an 8-GHz LC-oscillator PLL or 1–2-GHz ring-oscillator PLL and is restricted to research groups with appropriate technology access and NDA. The October 4 report quotes MICS director and Scientific Analog founder Jaeha Kim. SNU/IDEC are the library’s releasing/distributing organizations; the named tool vendors and technology provider are not thereby coauthors of every design. The source does not establish unrestricted public library availability.", "sources": [ { "title": "Seoul National University and IDEC distributes Analog Cell Library (ACL) in 65nm CMOS", "url": "https://www.scianalog.com/news/celllibrary/", "checkedAt": "2026-10-25", "summary": "The October 4, 2016 report explicitly dates the SNU release announcement to August 8, identifies IDEC distribution, XMODEL/IC Compiler roles, PLL examples and technology-access/NDA restrictions.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/scientific-analog-2016-08-snu-idec-analog-cell-library/" }, { "id": "analog-devices-2016-automatic-real-number-abstraction", "when": { "start": "2016", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices authors report automatic real-number abstraction for mixed-signal SoC verification", "fact": "A DVCon 2016 paper by Analog Devices authors reports automatically generating schematic-consistent, high-fidelity real-number abstractions for mixed-signal SoC verification. The authors describe deployment across several ADI SoC tapeouts, detection of subtle design bugs, and circuit-simulation speedups greater than 1,000x while preserving the analog-function accuracy needed for the reported verification cases.", "sources": [ { "title": "Mixed-Signal Systems-on-Chip Design Verification with Automatic Real-Number Abstraction", "url": "https://dvcon-proceedings.org/document/mixed-signal-systems-on-chip-design-verification-with-automatic-real-number-abstraction/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Analog Devices paper on automatically generated real-number abstractions for SoC verification.", "status": "available", "archiveUrl": null }, { "title": "Mixed-Signal Systems-on-Chip Design Verification with Automatic Real-Number Abstraction — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/mixed-signal-systems-on-chip-design-verification-with-automatic-real-number-abstraction.pdf", "checkedAt": "2026-08-30", "summary": "The paper reports the abstraction flow, use across ADI tapeouts, defect detection, and its stated simulation-speed and accuracy results.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2016-automatic-real-number-abstraction/" }, { "id": "analog-devices-2016-sv-rnm-model-validation", "when": { "start": "2016", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices authors report UVM regression for SV-RNM model-to-netlist validation", "fact": "An Analog Devices-authored paper reports a block-level UVM constrained-random testbench run against both an SV-RNM behavioral model and the analog netlist. The same stimuli and checks provide one-to-one comparison, the tests can run in regular or nightly regressions, and the paper describes reusing the block-level agents in system-level verification.", "sources": [ { "title": "UVM Based Approach To Model Validation For SV-RNM Behavioral Models", "url": "https://dvcon-proceedings.org/document/uvm-based-approach-to-model-validation-for-sv-rnm-behavioral-models/", "checkedAt": "2026-08-30", "summary": "2016 Analog Devices paper on shared-stimulus UVM regression against SV-RNM models and analog netlists.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2016-sv-rnm-model-validation/" }, { "id": "infineon-2016-automotive-uvm-ams-verification", "when": { "start": "2016", "precision": "year" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon author reports UVM-based AMS verification of automotive mixed-signal requirements", "fact": "A DVCon 2016 paper by Infineon's Silvia Strähle describes UVM-based verification of an automotive mixed-signal design with more than 1,000 requirements. The environment could exchange a VHDL behavioral model for a transistor-level netlist where needed and checked analog quantities and operating conditions including temperature, overcurrent, and overtemperature behavior.", "sources": [ { "title": "AMS Verification in a UVM Environment", "url": "https://dvcon-proceedings.org/document/ams-verification-in-a-uvm-environment/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies Silvia Strähle of Infineon and the UVM-based AMS verification paper.", "status": "available", "archiveUrl": null }, { "title": "AMS Verification in a UVM Environment — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/ams-verification-in-a-uvm-environment-paper.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the automotive requirements context, behavioral-model and netlist substitution, and analog-condition checks.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2016-automotive-uvm-ams-verification/" }, { "id": "nxp-2016-low-power-mixed-signal-case-studies", "when": { "start": "2016", "precision": "year" }, "kind": "technical", "companies": [ "nxp" ], "people": [], "headline": "NXP authors report low-power full-chip verification across Verilog, wreal, and Verilog-AMS abstractions", "fact": "An NXP-authored paper reports low-power mixed-signal IoT case studies using CPF power intent, assertions, formal and connectivity checks, and self-checking verification while moving a verification database through Verilog, wreal, and Verilog-AMS abstraction levels. The examples include PMU, brownout detector, and LDO behavior at full-chip scope. The paper identifies evaluating UVM as a next step rather than reporting UVM deployment.", "sources": [ { "title": "Unique Verification Case Studies of Low Power Mixed Signal Chips", "url": "https://dvcon-proceedings.org/document/unique-verification-case-studies-of-low-power-mixed-signal-chips/", "checkedAt": "2026-08-30", "summary": "2016 NXP paper on low-power mixed-signal abstraction switching, assertions, formal and connectivity checks, with UVM explicitly left as future evaluation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/nxp-2016-low-power-mixed-signal-case-studies/" }, { "id": "texas-instruments-2016-analog-functional-coverage", "when": { "start": "2016", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [ "zhipeng-ye" ], "headline": "TI authors propose a handoff from schematic annotations to analog functional coverage", "fact": "A TI-authored paper proposes an Analog Coverage Collector through which analog designers mark internal schematic and device threshold information for use by chip-level verification engineers. The paper describes turning that information into top-level covergroups and coverage data to coordinate analog design and verification work.", "sources": [ { "title": "Functional Coverage Collection for Analog Circuits: Enabling Seamless Collaboration Between Design and Verification", "url": "https://dvcon-proceedings.org/document/functional-coverage-collection-for-analog-circuits-enabling-seamless-collaboration-between-design-and-verification/", "checkedAt": "2026-08-30", "summary": "TI-authored 2016 paper proposing schematic-level annotations that feed top-level analog functional coverage.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2016-analog-functional-coverage/" }, { "id": "texas-instruments-2016-cpf-ams-power-verification", "when": { "start": "2016", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments", "cadence" ], "people": [], "headline": "Texas Instruments and Cadence authors report CPF-driven low-power mixed-signal verification", "fact": "A DVCon 2016 paper by Texas Instruments and Cadence authors reports applying Common Power Format power intent to a complex industrial mixed-signal SoC. The flow generated power-smart interface elements, matched results from the authors' traditional inherited-interface-element method, and reduced the reported setup time from several weeks to less than two days.", "sources": [ { "title": "A Holistic Approach to Low-Power Mixed-Signal Design Verification Using Power Intent", "url": "https://dvcon-proceedings.org/document/a-holistic-approach-to-low-power-mixed-signal-design-verification-using-power-intent/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Texas Instruments and Cadence industrial case study using power intent for mixed-signal verification.", "status": "available", "archiveUrl": null }, { "title": "A Holistic Approach to Low-Power Mixed-Signal Design Verification Using Power Intent — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/a-holistic-approach-to-low-power-mixed-signal-design-verification-using-power-intent.pdf", "checkedAt": "2026-08-30", "summary": "The paper documents CPF-generated interface handling, its comparison with an inherited-interface flow, and the reported setup-time reduction.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2016-cpf-ams-power-verification/" }, { "id": "infineon-2015-common-pre-post-silicon-test-platform", "when": { "start": "2015-05-13", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon and FH Technikum Wien publish a common pre/post-silicon test description for mixed-signal SoCs", "fact": "A joint FH Technikum Wien/Infineon Technologies Austria paper presented a bidirectional pre/post-silicon bridge for Infineon's mixed-signal verification flow. It used a common platform-independent human-readable scripting test description, implemented with Perl, while environment-specific interpreters mapped the same test intent into the AGENtiX SystemC simulation environment or the JAZZ/lab-instrument post-silicon environment.", "sources": [ { "title": "2015 IEEE International Instrumentation and Measurement Technology Conference Final Program", "url": "https://imtc2015.ieee-ims.org/sites/2015.imtc.ieee-ims.org/files/I2MTC-2015_final-program_v7.pdf", "checkedAt": "2026-09-02", "summary": "Official I2MTC 2015 program listing the Infineon/FH Technikum Wien pre- and post-silicon verification paper on May 13, 2015.", "status": "available", "archiveUrl": null }, { "title": "A common platform for bridging pre- and post-silicon verification in mixed-signal designs", "url": "https://www.researchgate.net/publication/283668530_A_common_platform_for_bridging_pre-_and_post-silicon_verification_in_mixed-signal_designs", "checkedAt": "2026-09-02", "summary": "Author-uploaded paper describing the common Perl-based test description and its mapping to Infineon's AGENtiX pre-silicon and JAZZ post-silicon environments.", "status": "available", "archiveUrl": null }, { "title": "Unification of Pre- and Post-Silicon Verification Flows", "url": "https://embsys.technikum-wien.at/staff/widhalm/docs/2016_mess-unification_of_pre_and_post_silicon_verification_flows.pdf", "checkedAt": "2026-09-02", "summary": "Follow-up poster summarizing the single-test-description approach, hardware abstraction, SystemC pre-silicon execution and lab-equipment post-silicon execution.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2015-common-pre-post-silicon-test-platform/" }, { "id": "hitachi-2015-rnm-full-chip-mixed-signal-verification", "when": { "start": "2015-02-23", "precision": "day" }, "kind": "technical", "companies": [ "hitachi", "cadence" ], "people": [], "headline": "Cadence reports Hitachi used RNM for full-design verification of a mixed-signal backplane signal conditioner", "fact": "A Cadence press release reports that Hitachi used Virtuoso AMS Designer with real-number modeling to simulate the entire design of a backplane signal-conditioner mixed-signal chip, reducing verification from days to 30 minutes. Cadence says Hitachi presented the design and RNM results at ISSCC 2015 on February 23; this is a vendor-published customer report.", "sources": [ { "title": "日立、ケイデンスのVirtuoso AMS Designerを採用し、ミックスシグナル・チップの検証時間を短縮", "url": "https://www.cadence.com/ja_JP/home/company/newsroom/press-releases/pr-jp/2015/post952-2015-02-26.html", "checkedAt": "2026-08-30", "summary": "Cadence's vendor-published customer release reports Hitachi's full-design RNM simulation, the days-to-30-minutes reduction, and the February 23 ISSCC presentation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/hitachi-2015-rnm-full-chip-mixed-signal-verification/" }, { "id": "bosch-sensortec-2015-uvm-wreal-full-chip-mixed-signal-verification", "when": { "start": "2015", "precision": "year" }, "kind": "technical", "companies": [ "bosch-sensortec", "cadence" ], "people": [ "felix-assmann" ], "headline": "Bosch Sensortec and Cadence authors report extending UVM and wreal to analog-centric full-chip verification", "fact": "A Bosch Sensortec and Cadence DVCon Europe paper reports extending an existing digital UVM verification environment to address analog and full-chip verification in one mixed-signal testbench. The paper describes the architecture and implementation of the reusable approach and explicitly identifies wreal as part of the methodology.", "sources": [ { "title": "A concept for expanding a UVM testbench to the analog-centric toplevel", "url": "https://dvcon-proceedings.org/wp-content/uploads/a-concept-for-expanding-a-uvm-testbench-to-the-analog-centric-toplevel.pdf", "checkedAt": "2026-08-30", "summary": "The 2015 DVCon Europe paper identifies Felix Assmann and Axel Strobel with Bosch Sensortec and Hans Zander with Cadence, and reports a reusable UVM/wreal testbench spanning analog, digital, and full-chip verification.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/bosch-sensortec-2015-uvm-wreal-full-chip-mixed-signal-verification/" }, { "id": "hewlett-packard-2015-digital-centric-serdes-ams-verification", "when": { "start": "2015", "precision": "year" }, "kind": "technical", "companies": [ "hewlett-packard" ], "people": [], "headline": "Hewlett-Packard authors report a digital-centric mixed-signal methodology for SerDes verification", "fact": "A DVCon 2015 paper by Hewlett-Packard authors describes extending a mature digital UVM testbench to next-generation SerDes mixed-signal verification. The methodology supports model swapping and progressive refinement, allowing early link-training and equalization verification with behavioral models and later integration of schematics without refactoring the testbench.", "sources": [ { "title": "Advanced Digital-Centric Mixed-Signal Methodology", "url": "https://dvcon-proceedings.org/wp-content/uploads/advanced-digital-centric-mixed-signal-methodology.pdf", "checkedAt": "2026-08-30", "summary": "The Hewlett-Packard paper describes reuse of a digital UVM environment, progressive model refinement, and behavioral-to-schematic integration for SerDes verification.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/hewlett-packard-2015-digital-centric-serdes-ams-verification/" }, { "id": "xilinx-2015-octave-rnm-uvm-verification", "when": { "start": "2015", "precision": "year" }, "kind": "technical", "companies": [ "amd" ], "people": [ "patrick-lynch" ], "headline": "Xilinx authors report combining generated real-number models, Octave, and UVM for AMS verification", "fact": "A DVCon 2015 paper by Xilinx authors describes a mixed-signal verification flow combining automatically generated netlist real-number models, Octave signal processing, and a UVM environment with random stimulus and coverage. In one reported analog-multiplexer case, handwritten model content was limited to 10% of modules and 4% of lines; the paper also reports direct Octave FFT integration running 1.58x faster than its file-based comparison.", "sources": [ { "title": "Comprehensive AMS Verification Using Octave, Real Number Modelling and UVM", "url": "https://dvcon-proceedings.org/document/comprehensive-ams-verification-using-octave-real-number-modelling-and-uvm/", "checkedAt": "2026-09-02", "summary": "DVCon's record identifies John McGrath, Patrick Lynch, and Ali Boumaalif as the Xilinx authors of the paper on generated real-number models, Octave analysis, and UVM verification.", "status": "available", "archiveUrl": null }, { "title": "Comprehensive AMS Verification Using Octave, Real Number Modelling and UVM — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/comprehensive-ams-verification-using-octave-real-number-modelling-and-uvm.pdf", "checkedAt": "2026-09-02", "summary": "The paper identifies Patrick Lynch as a Xilinx author and documents the model-generation proportions, Octave integration, UVM environment, functional coverage, and FFT timing comparison.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/xilinx-2015-octave-rnm-uvm-verification/" }, { "id": "dialog-semiconductor-2014-selcuk-talay-ams-top-level-dv-lead", "when": { "start": "2014-12-02", "precision": "day" }, "kind": "organizational", "companies": [ "renesas" ], "people": [ "selcuk-talay" ], "headline": "An ITU seminar identifies Selcuk Talay as Dialog Semiconductor's AMS top-level design and verification lead", "fact": "An Istanbul Technical University seminar listing dated December 2, 2014 identifies Selcuk Talay of Dialog Semiconductor as AMS Toplevel Design and Verification Lead. The record establishes his publicly identified role at that time; it does not establish when the role began.", "sources": [ { "title": "EHB111 Dersi — December 2, 2014 seminar listing", "url": "https://web.itu.edu.tr/~yalcinmust/ehb111.html", "checkedAt": "2026-08-30", "summary": "Istanbul Technical University's dated seminar page identifies Dr. Selçuk Talay of Dialog Semiconductor as AMS Toplevel Design and Verification Lead on December 2, 2014.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/dialog-semiconductor-2014-selcuk-talay-ams-top-level-dv-lead/" }, { "id": "analog-devices-2014-metric-driven-mixed-signal-verification", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices" ], "people": [], "headline": "Analog Devices teams report two metric-driven mixed-signal verification deployments", "fact": "Two Analog Devices-affiliated 2014 papers report distinct deployments. The LMA team described its local organization's first heavily analog project staffed with dedicated DV engineers, using verification planning, self-checking and constrained-random testbenches, regressions, SPICE co-simulation, and SystemVerilog RNM. A Beijing ASSP team described UVM, assertions, real-number functional coverage, regression, and metric sign-off for a Cortex-M3 mixed-signal device.", "sources": [ { "title": "Digitizing Mixed Signal Verification on the LMA Project", "url": "https://dvcon-proceedings.org/document/digitizing-mixed-signal-verification-digital-verification-techniques-applied-to-mixed-signal-and-analog-blocks-on-the-lma-project/", "checkedAt": "2026-08-30", "summary": "2014 Analog Devices presentation documenting local organizational heterogeneity and the LMA project's planning, automation, SPICE co-simulation, UVM, and RNM practices.", "status": "available", "archiveUrl": null }, { "title": "Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-signal ASSPs", "url": "https://dvcon-proceedings.org/document/metric-driven-mixed-signal-verification-methodology-and-practices-for-complex-mixed-signal-assps/", "checkedAt": "2026-08-30", "summary": "2014 paper from an Analog Devices Beijing team describing UVM, assertions, real-number coverage, regression, and metric sign-off on a mixed-signal ASSP.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/analog-devices-2014-metric-driven-mixed-signal-verification/" }, { "id": "infineon-2014-analog-uvm-model-validation", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "infineon" ], "people": [ "sebastian-simon" ], "headline": "Infineon authors report Analog UVM stimulus and automated behavioral-model comparison", "fact": "Two Infineon DVCon 2014 papers describe an Analog UVM library for constrained-random analog transactions and automated comparison of analog behaviors. The model-validation flow uses an earth mover's distance implementation connected through SystemVerilog and C to convert waveform comparison into regression pass/fail results, reducing reliance on manual waveform inspection.", "sources": [ { "title": "Generation of Constraint-Random Transactions for Verification of Mixed-Signal Blocks", "url": "https://dvcon-proceedings.org/wp-content/uploads/generation-of-constraint-random-transactions-for-verification-of-mixed-signal-blocks.pdf", "checkedAt": "2026-08-30", "summary": "The Infineon paper presents an Analog UVM library and constrained-random analog transactions for mixed-signal block verification.", "status": "available", "archiveUrl": null }, { "title": "Automated Comparison of Analog Behavior in a UVM Environment", "url": "https://dvcon-proceedings.org/document/automated-comparison-of-analog-behavior-in-a-uvm-environment/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Infineon model-comparison work and its UVM context.", "status": "available", "archiveUrl": null }, { "title": "Automated Comparison of Analog Behavior in a UVM Environment — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/automated-comparison-of-analog-behavior-in-a-uvm-environment.pdf", "checkedAt": "2026-08-30", "summary": "The paper details earth-mover-distance waveform comparison, SystemVerilog/C integration, and automated pass/fail regression use.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2014-analog-uvm-model-validation/" }, { "id": "infineon-2014-upf-power-aware-mixed-signal-verification", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "infineon", "siemens-eda" ], "people": [], "headline": "Infineon and Mentor authors report UPF-based power-aware mixed-signal verification of a sensor SoC", "fact": "A DVCon 2014 paper by Infineon and Mentor Graphics authors reports applying UPF with RTL and SPICE content to power-aware mixed-signal verification of a tire-pressure-monitoring sensor SoC. The paper says the flow exposed power blackouts, sequencing errors, missing level shifters, and incorrect isolation polarity before gate-level verification.", "sources": [ { "title": "Power-Aware Verification in Mixed-Signal Simulation", "url": "https://dvcon-proceedings.org/document/power-aware-verification-in-mixed-signal-simulation-presentation/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Infineon and Mentor Graphics power-aware mixed-signal verification presentation.", "status": "available", "archiveUrl": null }, { "title": "Power-Aware Verification in Mixed-Signal Simulation — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/power-aware-verification-in-mixed-signal-simulation.pdf", "checkedAt": "2026-08-30", "summary": "The paper documents the UPF, RTL, and SPICE flow, its sensor-SoC context, and the classes of power-intent defects it reported.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2014-upf-power-aware-mixed-signal-verification/" }, { "id": "stmicroelectronics-2014-analog-model-equivalence-validation", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "stmicroelectronics", "siemens-eda" ], "people": [], "headline": "STMicroelectronics and Mentor authors report equivalence validation of analog behavioral models", "fact": "A DVCon 2014 paper by STMicroelectronics and Mentor Graphics authors describes a verification-plan-driven equivalence-validation component that applies common tests to analog implementations and behavioral models, produces pass/fail results and waivers, and can be reused across projects. The paper reports use by ST's high-speed serial-links group across HDMI, USB, and D-PHY work and says it exposed functional, connectivity, and test-mode differences before models were delivered to SoC teams.", "sources": [ { "title": "Equivalence Validation of Analog Behavioral Models", "url": "https://dvcon-proceedings.org/document/equivalence-validation-of-analog-behavioral-models/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the STMicroelectronics and Mentor Graphics authors and the analog-model equivalence-validation topic.", "status": "available", "archiveUrl": null }, { "title": "Equivalence Validation of Analog Behavioral Models — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/equivalence-validation-of-analog-behavioral-models.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the reusable validation component, pass/fail and waiver workflow, ST application context, and reported model differences.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/stmicroelectronics-2014-analog-model-equivalence-validation/" }, { "id": "texas-instruments-2014-ams-interface-automation", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments", "cadence" ], "people": [], "headline": "Texas Instruments and Cadence authors report automating supply-aware AMS interface handling", "fact": "A DVCon 2014 paper by Texas Instruments, IIT, and Cadence authors compares connect-module and interface-element methods for analog/mixed-signal boundaries and describes automation for true supply sensitivity. The authors state that the methods were applied on several commercial mixed-signal SoCs and present practical tradeoffs and guidelines for automating supply-sensitive interface handling.", "sources": [ { "title": "Efficient Methods for Analog Mixed-Signal Verification: Interface Handling Methods, Trade-offs and Guidelines", "url": "https://dvcon-proceedings.org/wp-content/uploads/efficient-methods-for-analog-mixed-signal-verification-interface-handling-methods-trade-offs-and-guidelines.pdf", "checkedAt": "2026-08-30", "summary": "The paper compares AMS interface approaches and reports application of automated, supply-sensitive interface handling on commercial mixed-signal SoCs.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2014-ams-interface-automation/" }, { "id": "texas-instruments-2014-specification-driven-ams-testbench-automation", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [], "headline": "Texas Instruments authors report specification-driven AMS testbench and RTL generation", "fact": "A DVCon 2014 paper by Texas Instruments authors reports a specification-driven flow that automatically generated mixed-signal testbench elements, RTL, assertions, and results infrastructure. In a power-management case study, the authors say the approach enabled analog IP-level SPICE simulation almost three months earlier than comparable prior executions within an approximately twelve-month development cycle.", "sources": [ { "title": "Automated Correct-by-Construct Methodology for RTL Design and AMS Test Bench Generation", "url": "https://dvcon-proceedings.org/document/automated-correct-by-construct-methodology-for-rtl-design-and-analog-mixed-signal-test-bench-generation-enables-early-design-closure-of-mixed-signal-soc/", "checkedAt": "2026-08-30", "summary": "DVCon's record describes the Texas Instruments specification-driven RTL and AMS testbench-generation methodology.", "status": "available", "archiveUrl": null }, { "title": "Automated Correct-by-Construct Methodology — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/automated-correct-by-construct-methodology-for-rtl-design-and-analog-mixed-signal-test-bench-generation-enab.pdf", "checkedAt": "2026-08-30", "summary": "The paper details generated testbench, RTL, assertion, and results infrastructure and reports the timing outcome for its power-management case.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2014-specification-driven-ams-testbench-automation/" }, { "id": "texas-instruments-2014-wreal-uvm-mixed-signal-soc", "when": { "start": "2014", "precision": "year" }, "kind": "technical", "companies": [ "texas-instruments" ], "people": [], "headline": "TI authors report wreal and UVM methods in two mixed-signal SoC case studies", "fact": "Two TI-authored 2014 papers report mixed-signal SoC verification using higher-level analog abstractions. One describes wreal models and digital-regression reuse on a 45 nm secure SoC, including functional and design-for-test integration issues; the other describes a UVM environment for an RF transceiver SoC using wreal and Verilog-AMS models, constrained-random stimulus, assertions, coverage, and a MATLAB reference-model checker.", "sources": [ { "title": "Efficient SoC-Level Mixed-Signal Frontend Verification Using Wreal Models", "url": "https://dvcon-proceedings.org/document/efficient-soc-level-mixed-signal-frontend-verification-using-wreal-models/", "checkedAt": "2026-08-30", "summary": "TI-authored 2014 case study on wreal-based frontend verification and digital-regression reuse for a 45 nm secure SoC.", "status": "available", "archiveUrl": null }, { "title": "Advanced Functional Verification Methodology Using UVM for Complex DSP Algorithms in Mixed-Signal RF SoCs", "url": "https://dvcon-proceedings.org/document/advanced-functional-verification-methodology-using-uvm-for-complex-dsp-algorithms-in-mixed-signal-rf-socs/", "checkedAt": "2026-08-30", "summary": "TI-authored 2014 paper on a UVM environment with wreal and Verilog-AMS models, assertions, coverage, and MATLAB-based checking for an RF transceiver SoC.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/texas-instruments-2014-wreal-uvm-mixed-signal-soc/" }, { "id": "ibm-2013-wreal-rnm-mixed-signal-verification", "when": { "start": "2013", "precision": "year" }, "kind": "technical", "companies": [ "ibm", "cadence" ], "people": [], "headline": "IBM and Cadence authors report wreal modeling and digital mixed-signal regressions on an IBM project", "fact": "A DVCon 2013 paper by IBM and Cadence authors reports that IBM created and deployed Verilog-AMS wreal models on a mixed-signal project. The authors describe correlation against circuit-level simulations, approximately 40x simulation speedup for a representative case, and digital mixed-signal regressions that could run overnight.", "sources": [ { "title": "Real Number Modeling", "url": "https://dvcon-proceedings.org/document/real-number-modeling/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies IBM and Cadence authors for the real-number-modeling methodology paper.", "status": "available", "archiveUrl": null }, { "title": "Real Number Modeling — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/real-number-modeling.pdf", "checkedAt": "2026-08-30", "summary": "The paper describes IBM's wreal model development, correlation, reported speed comparison, and overnight regression use.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/ibm-2013-wreal-rnm-mixed-signal-verification/" }, { "id": "stmicroelectronics-2012-06-metric-driven-ams-ip-presentation", "when": { "start": "2012-06-05", "precision": "day" }, "kind": "technical", "companies": [ "stmicroelectronics" ], "people": [], "headline": "STMicroelectronics presentation covers metric-driven analog/mixed-signal IP verification", "fact": "Cadence’s account of DAC 2012 identifies STMicroelectronics’ Pierluigi Daglio and Marco Carlini as authors of “Metric Driven Verification Approach for Analog/Mixed Signal IPs.” The account dates the presentation at the EDA360 Theater in San Francisco to June 5 at 4 p.m. The account was published on August 27, 2012.", "sources": [ { "title": "Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM", "url": "https://community.cadence.com/cadence_blogs_8/b/cic/posts/mixed-signal-designs-ips-embraces-metric-driven-verification-using-rnm", "checkedAt": "2026-11-07", "summary": "Cadence’s August 27, 2012 article names the STMicroelectronics authors and gives June 5 at 4 p.m. for their DAC presentation. Its general RNM discussion does not establish ST implementation details. Linked historical slides and audio now redirect to the Cadence homepage and were not reviewed.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/stmicroelectronics-2012-06-metric-driven-ams-ip-presentation/" }, { "id": "cadence-2012-real-valued-systemverilog-coverage", "when": { "start": "2012", "precision": "year" }, "kind": "technical", "companies": [ "cadence", "intel" ], "people": [ "prabal-bhattacharya", "scott-little" ], "headline": "Cadence and Intel authors present real-valued SystemVerilog covergroups for mixed-signal functional coverage", "fact": "At DVCon 2012, Cadence's Prabal K. Bhattacharya, Intel's Scott Little, and coauthors proposed extending SystemVerilog coverpoints to accept real-valued data for analog and mixed-signal functional coverage. The work reports a prototype following a year-long Cadence research-and-development effort and addresses real-valued bins and ranges, range precision, coverage scoring, cross coverage, and remaining floating-point issues. The affiliations are specific to this paper and do not imply methodology transfer between the companies.", "sources": [ { "title": "DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups", "url": "https://community.cadence.com/cadence_blogs_8/b/cic/posts/dvcon-2012-bringing-continuous-domain-into-systemverilog-covergroups", "checkedAt": "2026-08-30", "summary": "Cadence-authored account of Bhattacharya's DVCon presentation and the research-and-development effort behind the real-valued covergroup prototype.", "status": "available", "archiveUrl": null }, { "title": "Bringing Continuous Domain into SystemVerilog Covergroups", "url": "https://dvcon-proceedings.org/wp-content/uploads/bringing-continuous-domain-into-systemverilog-covergroups.pdf", "checkedAt": "2026-08-30", "summary": "DVCon 2012 paper specifying real-valued SystemVerilog coverpoints, binning, precision, scoring, and cross-coverage behavior.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/cadence-2012-real-valued-systemverilog-coverage/" }, { "id": "maxim-2012-uvm-ms-mixed-signal-soc-verification", "when": { "start": "2012", "precision": "year" }, "kind": "technical", "companies": [ "analog-devices", "cadence" ], "people": [ "neyaz-khan" ], "headline": "Maxim and Cadence authors report UVM-MS verification of a complex mixed-signal SoC", "fact": "A DVCon 2012 paper by Maxim Integrated and Cadence authors reports applying a UVM-MS methodology to a complex noise-cancelling receiver SoC. The case study describes an executable verification plan, wreal behavioral models, constrained-random stimulus, assertions, functional coverage, and verification closure supporting first-pass success.", "sources": [ { "title": "From Spec to Verification Closure: Applying UVM-MS for First-Pass Success to a Complex Mixed-Signal SoC", "url": "https://dvcon-proceedings.org/document/from-spec-to-verification-closure-a-case-study-of-applying-uvm-ms-for-first-pass-success-to-a-complex-ms-soc-design/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies the Maxim and Cadence case study on UVM-MS verification of a complex mixed-signal receiver SoC.", "status": "available", "archiveUrl": null }, { "title": "From Spec to Verification Closure — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/from-spec-to-verification-closure-a-case-study-of-applying-uvm-ms-for-first-pass-success-to-a-complex-mixed-signal-soc-design.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the executable plan, wreal models, constrained-random tests, assertions, coverage, and reported first-pass outcome.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/maxim-2012-uvm-ms-mixed-signal-soc-verification/" }, { "id": "infineon-2011-xvp-multiplatform-mixed-signal-crv", "when": { "start": "2011-09-22", "precision": "day" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon links mixed-signal constrained-random tests to XVP across simulation, PXI and ATE", "fact": "An Infineon-authored paper described linking Markov-based mixed-signal constrained-random test generation to an Executable Verification Plan (XVP) so test cases could be transferred to Cadence simulators and MATLAB/Simulink for simulation and to PXI and ATE for post-silicon verification. The paper also reports applying generated tests on mixed VHDL-AMS/Verilog models and post-silicon PXI/ATE systems and identifying mixed-signal design issues.", "sources": [ { "title": "Extending Constrained Random Verification to mixed-signal Automotive Power Devices using a non-stationary Markov process", "url": "https://project.edacentrum.de/rescar/system/files/ct_publication/2.2_nirmaier.pdf", "checkedAt": "2026-09-02", "summary": "Infineon-authored 2011 paper describing XVP-linked constrained-random generation across simulation, PXI and ATE targets for automotive mixed-signal power devices.", "status": "available", "archiveUrl": null }, { "title": "RESCAR Public Publications", "url": "https://project.edacentrum.de/rescar/show/public_publications", "checkedAt": "2026-09-02", "summary": "EDAcentrum publication index dating the Infineon paper to September 22, 2011.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2011-xvp-multiplatform-mixed-signal-crv/" }, { "id": "renesas-2011-2014-mizukusa-wreal-uvm-ams-verification", "when": { "start": "2011-04", "end": "2014-11", "precision": "month" }, "kind": "technical", "companies": [ "renesas" ], "people": [ "tomokatsu-mizukusa" ], "headline": "Tomokatsu Mizukusa's profile describes whole-chip Wreal and UVM-AMS verification work at Renesas", "fact": "Tomokatsu Mizukusa's public professional profile describes his 2011–2014 Renesas role as developing EDA and design methodology for mixed-signal and analog systems. It specifically reports MCU and SoC whole-chip mixed-signal functional and connectivity verification using Verilog Wreal, along with SystemVerilog discrete-real modeling and UVM-AMS.", "sources": [ { "title": "Tomokatsu Mizukusa — LinkedIn", "url": "https://jp.linkedin.com/in/tomokatsu-mizukusa-b2943724", "checkedAt": "2026-08-30", "summary": "Mizukusa's public profile directly associates whole-chip Wreal verification, SystemVerilog discrete-real modeling, and UVM-AMS with his April 2011–November 2014 Renesas role.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/renesas-2011-2014-mizukusa-wreal-uvm-ams-verification/" }, { "id": "freescale-2011-realtime-ams-assertions", "when": { "start": "2011", "precision": "year" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "scott-little" ], "headline": "Freescale coauthor proposes realtime regular expressions for analog and mixed-signal assertions", "fact": "At FMCAD 2011, John Havlicek and Freescale Semiconductor's Scott Little presented syntax and semantics for realtime regular expressions that extend SystemVerilog Assertion-style regular expressions to describe continuous-time analog and mixed-signal properties. The paper says the work was influenced by the Accellera analog-assertions effort; it does not claim an internal Freescale deployment.", "sources": [ { "title": "FMCAD 2011 Proceedings: Realtime Regular Expressions for Analog and Mixed-Signal Assertions", "url": "https://www.cs.utexas.edu/~hunt/fmcad/FMCAD11/papers/fmcad-2011-proceedings.pdf", "checkedAt": "2026-08-30", "summary": "The proceedings list Scott Little with Freescale Semiconductor and present realtime regular expressions for specifying continuous-time analog and mixed-signal properties.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/freescale-2011-realtime-ams-assertions/" }, { "id": "lsi-2011-2012-hdd-preamplifier-rnm-verification", "when": { "start": "2011", "end": "2012", "precision": "year" }, "kind": "technical", "companies": [ "broadcom", "cadence" ], "people": [ "neyaz-khan" ], "headline": "LSI and Cadence records describe RNM verification of a hard-disk-drive preamplifier", "fact": "A 2011 DVCon paper by LSI and Cadence authors describes real-number models for mixed-signal verification of a hard-disk-drive preamplifier and reports roughly 24x speedup over the referenced SPICE simulation with about 0.3% gain inaccuracy. A later Cadence-authored report describes LSI applying the models in mixed-signal SoC verification, reporting roughly 600x speedup, 95% accuracy, full functional coverage, and no functional bugs in first silicon. These performance and outcome statements retain their respective paper and vendor-report modalities.", "sources": [ { "title": "Metric Driven Verification of Mixed Signal Designs", "url": "https://dvcon-proceedings.org/document/metric-driven-verification-of-mixed-signal-designs/", "checkedAt": "2026-08-30", "summary": "DVCon's record identifies LSI and Cadence authors for the HDD-preamplifier real-number-modeling case study.", "status": "available", "archiveUrl": null }, { "title": "Metric Driven Verification of Mixed Signal Designs — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/metric-driven-verification-of-mixed-signal-designs.pdf", "checkedAt": "2026-08-30", "summary": "The paper reports the RNM architecture, simulation-speed comparison, accuracy result, and chip-level verification option.", "status": "available", "archiveUrl": null }, { "title": "Real Number Model Development and Application in Mixed-Signal SoC Verification", "url": "https://community.cadence.com/cadence_blogs_8/b/cic/posts/cdnlive-real-number-model-development-and-application-in-mixed-signal-soc-verification", "checkedAt": "2026-08-30", "summary": "Cadence's 2012 account reports LSI's application results, including its stated speed, accuracy, coverage, and first-silicon outcomes.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/lsi-2011-2012-hdd-preamplifier-rnm-verification/" }, { "id": "medtronic-2011-metric-driven-mixed-signal-verification", "when": { "start": "2011", "precision": "year" }, "kind": "technical", "companies": [ "medtronic" ], "people": [], "headline": "Medtronic author reports plan- and metric-driven mixed-signal verification for a medical-device IC", "fact": "A DVCon 2011 paper by Medtronic's Gregg Sarkinen reports applying an integrated analog/digital verification environment to a mixed-signal medical-device IC prototype. The flow used a verification plan, constrained-random stimulus, checkers, reusable models, and coverage closure. The paper reports more than 3,000 mixed-signal simulations with automated pass/fail results.", "sources": [ { "title": "Plan- & Metric-Driven Mixed-Signal Verification for Medical Devices", "url": "https://dvcon-proceedings.org/document/plan-metric-driven-mixed-signal-verification-for-medical-devices/", "checkedAt": "2026-08-30", "summary": "DVCon's record describes Medtronic's plan- and metric-driven mixed-signal verification case study for a medical-device IC.", "status": "available", "archiveUrl": null }, { "title": "Plan- & Metric-Driven Mixed-Signal Verification for Medical Devices — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/plan-metric-driven-mixed-signal-verification-for-medical-devices.pdf", "checkedAt": "2026-08-30", "summary": "The paper details the integrated test environment, constrained-random stimulus, checkers, model reuse, coverage, and reported simulation volume.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/medtronic-2011-metric-driven-mixed-signal-verification/" }, { "id": "freescale-2010-trace-generated-ams-models", "when": { "start": "2010", "precision": "year" }, "kind": "technical", "companies": [ "nxp" ], "people": [ "scott-little" ], "headline": "Freescale author reports generating mixed-signal abstraction models from circuit-simulation traces", "fact": "A 2010 journal paper coauthored by Freescale Semiconductor's Scott Little proposes automatically generating abstraction models from transistor-level simulation traces for formal verification and system simulation. The paper demonstrates the approach on a switched-capacitor integrator and a PLL phase detector and evaluates how the generated models reproduce the observed circuit behaviors.", "sources": [ { "title": "Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces", "url": "https://doi.org/10.1142/S0129054110007209", "checkedAt": "2026-08-30", "summary": "The 2010 journal record identifies Scott Little with Freescale Semiconductor and describes automatic generation of abstraction models from transistor-level traces for formal verification and system simulation.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/freescale-2010-trace-generated-ams-models/" }, { "id": "intel-2010-full-chip-mixed-signal-validation", "when": { "start": "2010", "precision": "year" }, "kind": "technical", "companies": [ "intel" ], "people": [], "headline": "Intel authors report a real-valued full-chip mixed-signal validation strategy", "fact": "Intel authors report a full-chip mixed-signal validation strategy that represents top-level analog ports as real-valued signals, reuses a SystemVerilog real-port testbench from top-down development through bottom-up implementation, and selectively replaces analog blocks with behavioral models. The paper says the tool-independent method was applied to three successive Intel SoC projects with open- and closed-loop mixed-signal networks and includes behavioral-model equivalence checking.", "sources": [ { "title": "Strategy and Environment for SOC Mixed-Signal Validation: A Case Study", "url": "https://dvcon-proceedings.org/document/strategy-and-environment-for-soc-mixed-signal-validation-a-case-study/", "checkedAt": "2026-09-02", "summary": "The DVCon archive dates the Intel-authored paper to 2010 and identifies it as a full-chip mixed-signal validation case study.", "status": "available", "archiveUrl": null }, { "title": "Strategy and Environment for SOC Mixed-Signal Validation: A Case Study — paper", "url": "https://dvcon-proceedings.org/wp-content/uploads/strategy-and-environment-for-soc-mixed-signal-validation-a-case-study.pdf", "checkedAt": "2026-09-02", "summary": "The paper describes the real-valued SystemVerilog port strategy, behavioral-model substitution and equivalence checking, and reported application to three successive Intel SoC projects.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/intel-2010-full-chip-mixed-signal-validation/" }, { "id": "infineon-2009-07-verilog-buck-converter-modeling", "when": { "start": "2009-07", "precision": "month" }, "kind": "technical", "companies": [ "infineon" ], "people": [], "headline": "Infineon and University of Trieste authors report Verilog HDL buck-converter modeling", "fact": "A PRIME-09 paper by University of Trieste researchers and Infineon Technologies authors Giuseppe Bernacchia and Emanuele Bodano, affiliated with Padova, describes a discrete-time buck-converter model implemented in Verilog HDL. The model combines the switching network, output inductor and capacitor, including parasitic effects. The authors compare simulated electrical waveforms with an experimental prototype in PWM continuous-conduction, discontinuous-conduction and pulse-frequency-modulation modes, and investigate controller behavior during mode transitions.", "sources": [ { "title": "Discrete time large-signal model of dc-dc converters for system level simulation of digitally controlled SMPS", "url": "https://www.researchgate.net/publication/224576504_Discrete_time_large-signal_model_of_dc-dc_converters_for_system_level_simulation_of_digitally_controlled_SMPS", "checkedAt": "2026-11-07", "summary": "The author-uploaded original paper identifies the historical University of Trieste and Infineon Technologies, Padova affiliations and describes the Verilog HDL buck-converter model and comparisons with a prototype. ResearchGate labels the publication August 2009 and the author upload January 9, 2017; the Event uses the July 2009 proceedings month recorded by the university bibliography.", "status": "available", "archiveUrl": null }, { "title": "University of Trieste, Image Processing Laboratory: 2009 publications", "url": "https://ipl.dia.units.it/the-laboratory/publications/42-2009", "checkedAt": "2026-11-07", "summary": "The University of Trieste bibliography lists the paper title and authors in PRIME-09, Cork, pages 60–63, July 2009, establishing the proceedings month used for this Event.", "status": "available", "archiveUrl": null } ], "recordUrl": "https://ams-signals.com/events/infineon-2009-07-verilog-buck-converter-modeling/" } ] }