AMS Signals

Analog

    • AI Design
    • AI Simulation
    • AI-ASSISTED

    Analog Canvas

    Agent-assisted hierarchical schematic editor with connectivity inspection, simulation-source authoring and SPICE/Spectre/RNL interchange. Its hosted ngspice SG13G2 profile adds device/corner and combinational-cell qualification; local headless drawing does not execute simulation, and EDA adapters retain separate service, installation and PDK requirements.

    Development provenance

    Claude-credited implementation added hosted standard-cell simulation binding and integrated coupled-inductor support across editing, persistence, rendering and netlist export. The current edit engine retains the coupling transaction implementation.

    • AI Design
    • Simulation
    • AI Layout
    • AI-ASSISTED

    klayout-tools

    Headless IC toolkit for parametric layout, DRC/LVS/extraction, ngspice corner simulation and gm/Id sizing, with JSON CLI/MCP interfaces. Bundled agent skills guide topology and physical-layout decisions; deterministic kernels perform execution, while process coverage, optional native extensions and development-versus-release capabilities remain explicit.

    Development provenance

    Claude-coauthored changes implement and test rendering of citation, recorded-hash and metric checks in attestation reports; the canonical module retains the handlers after refactoring. This attributes those changes, not the whole toolkit.

    • Simulation

    Palace

    Parallel finite-element electromagnetic solver for eigenmode, driven-frequency, transient, electrostatic and magnetostatic analyses. Configured meshes, materials and boundary conditions yield field responses and capacitance or inductance matrices, with explicit geometry preparation and numerical convergence requirements separating it from automatic layout signoff.

    • Design
    • Simulation
    • AI-ASSISTED

    RSpice

    Rust SPICE and mixed-signal simulator with schematic editing, Verilog-AMS/wreal, HDL tracing, circuit assertions and selected LTspice special-function devices. SystemVerilog support remains a subset without custom real-net resolution functions; its personal-use license restricts commercial evaluation, prototyping and redistribution without separate permission.

    Development provenance

    A commit coauthored with Claude Opus 5 connected solver controls to netlist parsing and executable engine configuration. The current source retains the continuation, damping, solver-backend and timestep handling.

    • AI Design
    • AI Simulation
    • AI Layout
    • AI-ASSISTED

    Vibe-IC

    Combines Claude Code skills with EDA tools for analog topology selection, transistor sizing, testbench generation, PVT simulation and physical implementation. Model-guided layout and verification workflows use Magic, Netgen and ngspice; the broader digital/AMS framework requires a configured EDA container and PDK, and its published gates do not establish general autonomous design success.

    Development provenance

    Claude and Codex are credited on merged actuator-progress and post-route repair-policy code, including executable regression tests. Those contributions remain in the canonical repository; they establish assistance without proving AI built most of the project.

    • Simulation
    • AI-ASSISTED

    gsim

    Connects GDSFactory layouts to electromagnetic solvers through PDK-derived geometry, meshing and multimode ports, including terminal S-parameter extraction. Optional FEMwell mode solving and DEVSIM-driven electro-optic workflows extend the analysis interface; local/cloud backends retain separate dependencies, and the package requires GDSFactory 9.

    Development provenance

    Claude is co-credited for implementing conversion from SParams to a scikit-rf Network. The canonical result adapter retains frequency-unit conversion and complex multiport matrix construction.

    • Layout
    • AI-ASSISTED

    KLayout-PEX

    Layout parasitic extraction infrastructure combining KLayout connectivity and process stacks with Magic, FasterCap and an internal 2.5D engine. Exclusion markers and model cutouts preserve external coupling while partitioning RC extraction; PEX25D exchange, pre-alpha status and backend-specific accuracy limits remain explicit.

    Development provenance

    Claude-credited development reworked device-terminal attachment to extracted resistor networks and implemented RC/LVS identity consistency checking. The netlist-checking module remains in the current extraction flow.

    • AI Design
    • AI-ASSISTED

    RNL

    Constraint-aware schematic notation embedded in SPICE/Spectre netlists, with Rust check, solve and render tools and native/WASM viewers. A local browser-based viewer adds native solving and file saving for older Linux systems; browser-only solving and graphical drag-placement editing remain unavailable.

    Development provenance

    A Claude-coauthored change to the public EDA symbol and style packages includes executable viewer, WASM and CLI regression tests retained on the default branch. This supports assisted development of that change, not AI authorship of the entire project.

    • Simulation
    • AI-ASSISTED

    VACASK

    Analog simulator loading compiled Verilog-A models through OSDI for DC, AC, transient, noise and periodic analyses, with scripted controls and file-driven stimuli. Periodic noise uses a driven-circuit algorithm rather than oscillator phase-noise analysis; SPICE/Spectre import remains experimental, and model compilation requires OpenVAF-Reloaded.

    Development provenance

    Claude Code is credited with co-developing the ng2vc parameter-parser correction. The canonical converter retains comparison-aware assignment splitting after the code moved into the Python package.

    • AI Design

    AnalogToBi

    Generates transistor-level circuit topologies from circuit-type tokens with a grammar-constrained language model. Device-net bipartite graphs encode component connections, and structural validity and novelty checks assess the generated topologies without measuring electrical performance.

    • Simulation

    ESPice

    Zig circuit simulator using VerA-compiled Verilog-A device kernels for operating-point, transient and frequency-domain analyses. Runtime HDL loading and adaptive transient handling connect behavioral models to the solver; CPU and optional CUDA/HIP paths have distinct dependencies, and reported benchmark results do not establish universal speed or accuracy.

    • AI Layout
    • AI-ASSISTED

    GDSFactory

    Python library for parametric chip-layout generation, hierarchical composition and electrical or photonic routing. A released agent skill guides model-driven component generation and visual iteration; geometry export remains in the core library, while electromagnetic simulation and commercial extensions are separate integrations.

    Development provenance

    Claude is co-credited for repairing component-sequence connections without replacing electrical ports. The retained executable sample allows cross-section mismatches while preserving the original port identities for layout export.

    • Simulation

    Gnucap

    Modular analog and mixed-signal circuit simulator with numerical analyses, device plugins and logic integration. Recent logic changes separate acceptance-queue handling from timestep review and move connection rules into the logic plugin; behavioral-model compilation is provided separately by Modelgen-Verilog, and Verilog-AMS support remains partial.

    • Layout
    • AI-ASSISTED

    Magic

    VLSI layout editor with design-rule checking, circuit extraction and parasitic extraction (PEX) for custom-IC workflows. Interactive editing and Tcl scripts operate on layout geometry, with technology files supplying the process-specific rules used by open PDKs.

    Development provenance

    The maintainer explicitly credits Claude with implementing optional corner-fringe capacitance extraction. The patch adds extraction geometry calculations, coupling/substrate corrections and command controls retained in Magic.

    • Design
    • Simulation

    Qucs-S

    Qt GUI for schematic capture, circuit-analysis setup and result visualization using ngspice, Xyce, SpiceOpus or Qucsator backends. Component libraries and plotting keep circuit editing and simulation in one application, with available analyses and device support depending on the selected engine.

    • AI Design
    • Simulation
    • AI-ASSISTED

    Razavi-Bench

    Benchmarks LLM answers to 50 analog-circuit questions through direct QA, workspace-agent and experimental ngspice-assisted modes. Reference solutions and a shared rubric grade explanations about MOS devices, feedback and oscillators; the published leaderboard reports direct-QA results rather than circuit-performance closure.

    Development provenance

    Claude-credited implementation added the per-model results explorer with rollout scores, responses, judge rationales, task navigation and shared cost calculations. The current site retains this results-browsing application.

    • AI Design
    • Simulation
    • Layout
    • AI-ASSISTED

    virtuoso-bridge-lite

    Python, CLI and optional MCP bridge for Virtuoso schematic/layout editing, Maestro engine and Spectre X preset configuration, asynchronous simulation jobs, standalone Spectre execution and PSF parsing. A bundled model-driven netlist skill repairs circuit/testbench structure; licensed EDA installations and PDKs remain user-supplied.

    Development provenance

    Claude-credited development added the doctor diagnostic subsystem and CLI integration. Its retained implementation analyzes connection identity, configuration, session blockers, host permissions and EDA availability, with structured findings and guarded read-only checks.

    • Layout
    • AI-ASSISTED

    Vyges EM-IR

    Physical power-grid analysis tool computing resistive IR drop and electromigration-limit violations from supplied networks or routed geometry. Analog and digital examples use externally supplied loads; current limits, thermal assumptions and process data must be reviewed independently from claims of foundry-certified signoff.

    Development provenance

    Claude is co-credited for implementing the release workflow guard that checks a tag against the crate version. The canonical workflow retains this executable build check; the evidence does not attribute most of the engine to AI.

    • Layout
    • AI-ASSISTED

    Vyges LVS

    Experimental layout-versus-schematic netlist comparator with structural refinement, explicit device/net bijection and divergence diagnostics. It checks supported SPICE primitives and shared device parameters, while extraction coverage, parameter availability and matching assumptions limit its use as an independent development-time comparison path.

    Development provenance

    Claude is co-credited for implementing the release workflow guard that checks a tag against the crate version. The canonical workflow retains this executable build check; it does not establish AI authorship of the shared extraction dependency.

    • Design
    • Simulation
    • AI-ASSISTED

    Xschem

    Captures hierarchical custom-IC schematics, emits SPICE/Verilog/VHDL netlists and integrates simulator control and backannotation. Embedded waveform tools include Smith charts for complex S-parameter or impedance data, with reference-impedance conversion and frequency cursors; numerical analyses run through separately configured simulators and PDKs.

    Development provenance

    The Smith-chart contributor explicitly states that an AI coding assistant implemented the feature. The merged and retained code adds complex-expression conversion, Smith-grid and trace rendering, and frequency-linked cursor interaction.

    • Layout
    • AI-ASSISTED

    Open-PDKs Regression Tests

    Executable DRC, LVS and parasitic-extraction regression suites for selected open PDKs. Make targets and Python checks compare positive and negative layouts with documented expectations and pinned extraction results; coverage varies by process, and agreement does not establish silicon accuracy.

    Development provenance

    Claude is co-credited for correcting substrate-net handling in the parasitic-extraction comparison tools. The canonical scripts retain the PDK-specific substrate names and use them when comparing capacitance results.

    • Design
    • Simulation
    • Layout
    • AI-ASSISTED

    OpenLayout

    Custom-IC environment connecting xschem, ngspice, KLayout and FasterCap through a shared workspace and command interface. It exposes schematic editing, simulation, DRC, LVS and post-layout netlisting for ASAP7, with calibrated extraction geometry and idealized supply nets limiting the current flow.

    Development provenance

    Claude is co-credited for correcting ASAP7 diffusion connectivity through trench contacts. The canonical extractor retains the SDT layer and the corresponding source/drain-to-LISD connectivity rules.

    • Simulation
    • AI-ASSISTED

    snp2le

    GUI and batch converter from Touchstone S-parameters to SPICE or VACASK circuit macromodels. Vector fitting, optional passivity enforcement and structure-specific fitting support RF modeling, while fit bandwidth, model identifiability and optional thermal-noise conditions bound the exported approximation.

    Development provenance

    Claude is co-credited for correcting S-parameter plotting on PySide6 builds that return list-valued selector data. The canonical plot view retains handling of both tuples and lists.

    • Layout
    • AI-ASSISTED

    KLayout

    Layout editor and verification platform for custom integrated circuits, with GDS/OASIS support. Python/Ruby scripts and parameterized cells automate geometry construction, while programmable DRC/LVS checks use technology-specific rules to examine layout and connectivity.

    Development provenance

    GLM 5.3 is credited on a merged global-net cluster repair that redirects every absorbed entry before deletion. The corrected C++ implementation remains in the canonical project.

    • AI Design
    • AI Simulation
    • AI Layout

    Microelectronic Block Generator

    Generates analog layouts from SPICE subcircuits and connects sizing, DRC/LVS, extraction and post-layout simulation. Agent-facing tools expose netlist checks, measurements and PDK profiles alongside optional model-driven corrections; GF180 remains the documented physical flow, and supported devices, configured tools and PDK revisions bound results.

    • Simulation

    VerA

    Verilog-A/AMS compiler producing Zig device code, shared libraries and OSDI 0.4 models for host simulators. Its fixture runner also exercises analog and mixed-signal models, but uses a declared time grid; adaptive circuit simulation and event-time accuracy depend on the host and supported interface.

    • Simulation
    • AI-ASSISTED

    verilog-a-sim

    Pure-Rust Verilog-A circuit simulator compiling models with automatic differentiation into an MNA/Newton solver for DC, transient, AC and noise analysis across multiple disciplines. Current main includes temperature propagation and additional noise grids; digital events, wreal and connectmodule are outside its supported language subset.

    Development provenance

    Claude Opus is explicitly coauthor-credited for implementing oct/lin noise-grid parsing and execution, with parser regressions and a validation-harness extension. These executable changes are retained at the reviewed canonical main revision.

    • Simulation
    • AI-ASSISTED

    openEMS

    Electromagnetic field solver using the EC-FDTD method, with Python and Octave/Matlab interfaces. Geometry, materials, excitations and ports define RF analyses and network responses; device or interconnect studies require explicit meshing and boundary setup rather than automatic foundry-qualified GDS extraction.

    Development provenance

    Claude Code is credited with assisting implementation of the VTK-independent field-dump writer. The canonical C++ implementation retains XML escaping, base64 encoding and zlib-compressed array output.

    • Simulation
    • AI-ASSISTED

    OpenVAF-Reloaded

    Verilog-A compiler whose current development branch emits OSDI 0.5 model libraries for compatible circuit simulators, retaining timestep-bound and batch-cache correctness work. Host compatibility is separate from language coverage; cross, above, timer and absdelta event controls still warn that their events are not scheduled.

    Development provenance

    Claude- and Cursor-credited development implemented VAMS-2023 named events and jump statements across compiler representation, validation and lowering. The current lowering code retains these language-support paths.

    • Design
    • Simulation

    PyOPUS

    Python library and GUI for analog circuit sizing and simulation-driven optimization across process corners. Simulator adapters and performance extraction connect numerical search with sensitivity analysis, worst-case methods and yield-oriented design, integrating circuit evaluation with sizing decisions.

    • Simulation
    • AI-ASSISTED

    scikit-rf

    Python toolkit for measured or simulated N-port RF networks, including S-parameter operations, calibration and transmission-line models. Vector fitting turns sampled frequency responses into rational models, with SPICE subcircuit export for fitted S-parameters, connecting RF characterization to circuit simulation.

    Development provenance

    Claude Opus 4.7 is credited on the MDIF parser repair that folds tab-prefixed continuation lines before parsing. The merged implementation remains in the canonical project.

    • Simulation

    VAMS Conformance Suite

    Verilog-A/AMS and SPICE compatibility test suite with a C harness, tool adapters and numerical-output oracles. It separates compile acceptance, execution, skips and expected failures across selected fixtures; the infrastructure compares model and simulator behavior without certifying full language conformance or serving as a standalone circuit simulator.

    • AI Design
    • Simulation
    • Layout
    • AI-ASSISTED

    vcli

    Rust CLI for concurrent Virtuoso sessions, schematic edits, Maestro/Spectre runs, PSF results and SKILL layout helpers. Repository-shipped agent skills add model-guided sizing and schematic workflows; an Evidence Loop records human GUI corrections, verifies follow-up evidence and extracts reusable rule candidates for human review.

    Development provenance

    A Claude-credited campaign implemented OCEAN simulation automation and integrated setup, run, measurement, sweep and corner commands into the Rust CLI. The current simulation commands still use that OCEAN layer.

    • Layout

    Netgen

    Netlist comparison tool for layout-versus-schematic checking of SPICE and Verilog circuits. Its Tcl interface compares connectivity and device properties using process-specific setup rules; layout extraction is supplied by other tools such as Magic or KLayout.

    • Design
    • Layout
    • AI-ASSISTED

    Revolution EDA

    Custom-IC workspace with hierarchical symbol, schematic and layout editors, parameterized cells and SPICE netlist import/export. The public core adds correspondence-based cross-probing between layout and LVS-extracted schematics; commercial AI and integration plugins retain separate availability and licensing boundaries.

    Development provenance

    A Devin-generated implementation introduced the shared connectivity engine, typed parameter model and inherited net expressions, integrating them with editor scenes and netlisters. The current source retains the connectivity resolver.

    • AI Design
    • AI Simulation

    AnalogCoder-Pro

    Uses multimodal LLMs to generate analog netlists and diagnose or repair candidates from ngspice results and waveform images. Its fixed-topology sizing stage uses Optuna TPE with PySpice/ngspice DC-bias and AC evaluation; standalone sizing needs no model API, while generation and multimodal diagnosis require a configured endpoint.

    • Layout
    • AI-ASSISTED

    gdscheck

    Experimental Rust design-rule checker for GDSII layouts with declarative YAML rule decks. Its CLI runs selected checks and bundled process decks, while incomplete rule coverage and unqualified results limit its use to reviewed development and regression workflows.

    Development provenance

    Claude is co-credited for correcting edge-piece classification at polygon walls. The canonical Rust implementation retains separate tolerances for labels and edge midpoints, with an executable regression.

    • Simulation

    Gnucap Modelgen-Verilog

    Verilog-AMS behavioral-model compiler that generates C++ plugins for Gnucap, with analog operators and mixed-signal event support under active development. Recent fixes address pending soft-event evaluation and delayed signals; execution requires a compatible Gnucap build, and language support remains partial.

    • Design
    • Simulation
    • Layout
    • AI-ASSISTED

    OpenRAM

    Transistor-level SRAM compiler generating circuit netlists, physical layouts and integration views for ASIC memory macros. Its Python flow connects process-specific cell construction, DRC/LVS and SPICE timing/power characterization; supported technologies and external verification tools bound the generated macros.

    Development provenance

    Claude is co-credited for implementing optional width-dependent transistor model lookup retained in the canonical generator. Current SKY130 profiles no longer declare the special narrow-NFET model after an upstream compatibility correction.

    • AI Design
    • AI Simulation
    • AI-ASSISTED

    Masala-CHAI

    Reconstructs SPICE netlists from schematic images using component detection and multimodal connectivity reasoning, with a V2 agent loop that revises candidates from judge feedback and optional ngspice simulation.

    Development provenance

    A Cursor-credited implementation introduced the agents_v2 refinement pipeline, including component/connectivity/netlist agents and judge-driven conflict resolution. The current code retains the judge and pipeline modules.

    • AI Design
    • Simulation
    • AI Layout
    • AI-ASSISTED

    SpiceXplorer

    Combines a PDK-neutral analog circuit database with gm/ID sizing, numerical and Bayesian optimization, SPICE evaluation and parameterized layout flows. Released agent workflows and worked IHP designs span schematic/layout co-design, including a PAM-4 driver and a low-pass-filter front end, with inspectable verification artifacts.

    Development provenance

    The September 1 EM-verification contribution credits Claude Opus and adds net extraction, openEMS S-parameter orchestration and SPICE-model export with tests. The reviewed diff establishes AI-assisted implementation of this analysis subsystem.

    • AI Design
    • Simulation
    • AI-ASSISTED

    Ngspice + OpenVAF Enhancements

    Extends ngspice simulation and OpenVAF Verilog-A compilation with circuit-parameter optimization. A Gaussian-process surrogate guides Bayesian search alongside conventional optimizers, while SPICE evaluates each candidate; these Claude-assisted enhancements belong to the combined development tree rather than automatically to either upstream project.

    Development provenance

    The owner identifies Claude Code use, and a Claude-credited commit implements compiler discipline-attribute handling and OSDI callbacks retained in this tree. These contributions support assistance; the evidence does not establish AI built most of the combined project.

    • Simulation

    uberWAVE

    Open-source waveform viewer for inspecting large ngspice analog simulation datasets, with RAW/UwRaw loading, multi-pane plots and cursor measurements. Its WP5 alpha adds Spectre PSF/PSFXL import and uses native memory-mapped access, min/max decimation and hierarchical caching; mixed-signal acceptance and automated rise/fall measurements remain pending.

    • Simulation

    Xyce

    Sandia-developed SPICE-compatible circuit simulator with DC, transient, AC, noise and harmonic-balance analyses. Its C++ implementation supports MPI-based parallel execution and compact-device models, with an XDM netlist translator for adapting supported external SPICE syntax.

    • Simulation

    SerDesSystemCProject

    Behavioral SerDes link simulator in SystemC/SystemC-AMS, covering transmitter, channel, equalization and clock/data recovery. Recent work applies modeled channel transport delay and adds phase/noise BER exploration; per-input MIMO delay skew remains approximated, and numerical link studies do not establish transistor-level accuracy or protocol compliance.

    • AI Design
    • Simulation

    AnalogSAGE

    Uses LLM agents for topology selection, refinement and transistor sizing in SKY130 op-amps, LDOs and bandgap references. Retrieved knowledge, accumulated experience and Bayesian/genetic search guide circuit proposals, while released adapters and testbenches execute ngspice measurements; the configured model and PDK remain external dependencies.

    • Design
    • Simulation
    • Layout

    IHP SG13G2 AMS Chip Template

    AMS chip-design template integrating analog schematics and simulation, digital verification, macro hardening, top-level assembly and DRC/LVS/PEX for IHP SG13G2. Project-creation targets and process-specific tool recipes organize a reusable flow, while external engines and PDK versions determine checking and extraction coverage.

    • Layout

    openPCells

    Technology-independent parametric layout generator using Lua cells and a C geometry/export engine for analog, RF and mixed-signal ICs. It generates devices, matched structures and hierarchical circuits into GDSII/OASIS and other formats; technology mappings and process-specific physical verification remain the user's responsibility.

    • Design

    MorphNet

    Python circuit model and bidirectional netlist translation library supporting SPICE-family dialects and Verilog-AMS. Parsers and writers map connectivity, parameters and simulation declarations through a shared schema, helping interchange circuit descriptions without executing electrical analyses or proving equivalent simulator behavior.

    • AI Design
    • AI Simulation
    • AI-ASSISTED

    vibe-analog

    Turns natural-language circuit requirements into editable schematics and SPICE artifacts. Its agent authors verification plans, analysis directives and measurements before ngspice execution; analog-IC mode adds PDK/model binding and device-parameter audits, while PCB layout, IC mask layout and production signoff remain outside the core workflow.

    Development provenance

    Cursor-credited implementation added project-specific component parameter forms, PDK installation/registration binding and schematic import/export integration. The current desktop retains the Analog IC parameter-form implementation.

    • Simulation
    • AI-ASSISTED

    SuperPEEC

    PEEC electromagnetic solver for voxelized conductors, dielectrics, traces and bond-wire assemblies described in TOML. It computes frequency-dependent network and port quantities for interconnect and passive structures, with discretization, solver tolerances and backend selection governing numerical cost and accuracy.

    Development provenance

    Claude is co-credited for implementing guarded variational impedance readout. The canonical solver retains the residual-based correction and its signal-to-noise guard.

    • Design
    • Simulation
    • Layout

    ShapeIC

    Rust platform for hierarchical analog circuit exploration using device lookup tables, small-signal models and propagated circuit requirements. Electrical evaluation and a bounded OTA layout/PEX workflow support comparisons with ngspice; supported PDKs, generated tables and fixed layout policies constrain the demonstrated coverage.

    • Design
    • Simulation
    • Layout

    XicTools

    Integrated electronic-design tools combining Xic schematic and layout editing with WRspice circuit simulation. Xic supplies process-dependent design-rule checking and extraction, while the shared repository also maintains simulator and support components with platform-specific build and device-model requirements.

    • AI Design
    • Simulation
    • Layout
    • AI-ASSISTED

    IC Design Studio

    Open-source Qt workspace combining hierarchical schematics, analog sizing and optimization, SPICE/RTL experiments, and editable IC layouts with external DRC/LVS/extraction engines. Optional Gaussian-process search learns from simulated candidates to guide design choices; the engineering preview retains process-specific verification limits, and its bounded ngspice/Icarus bridge does not provide general Verilog-AMS support.

    Development provenance

    The maintainer explicitly marks the integrated digital simulation/synthesis and implementation work as implemented with Codex. The campaign adds RTL execution, waveform handling, mapped verification and physical-flow orchestration retained in the desktop workspace.

    • AI Design
    • Simulation
    • AI Layout
    • AI-ASSISTED

    ChipJev

    Uses a typed decision model and GPU Bayesian search to select circuit topologies and size devices, with ngspice evaluation on PTM 45 nm and SKY130. A model-guided SKY130 Magic flow proposes layout changes and accepts them through DRC, LVS, RC extraction and post-layout simulation.

    Development provenance

    Claude-credited implementation added hierarchical wired-Xschem schematic generation and physical-layout/post-extraction support for SAR, flash and sampler circuit families. The current source retains the schematic geometry/connectivity layer.

    • AI Design
    • Simulation
    • AI-ASSISTED

    SGAnalog

    Benchmark built from commit-pinned, human-designed Tiny Tapeout circuits. Evaluates AI schematic-to-SPICE transcription with device–net graph matching and fixed-topology sizing with ngspice against human-reference performance; public code includes circuit data, evaluation scripts and a pinned open-PDK environment.

    Development provenance

    The public implementation release credits Claude and includes executable harvesting, netlist preparation, blinded rendering and sizing/evaluation software. Its sizing evaluator remains in the published project.

    • AI Design
    • AI Simulation

    EDA Agent

    Retrieval-grounded agent that writes and executes Python against a live Virtuoso session to construct schematics and configure simulation tasks. API documentation, scanned design knowledge and prior error resolutions guide code generation and recovery; users supply the licensed EDA environment, bridge, PDK and model service.

    • AI Design

    diagen

    Turns textual circuit connectivity into automatically arranged TikZ and SVG schematics for analog and digital diagrams. A shipped agent skill authors the connection netlist, inspects the rendered preview and revises the diagram; deterministic placement/routing produces drawings rather than electrical simulation or IC mask layout.

    • AI Design
    • Simulation

    Analog Design Bench

    Benchmarks long-horizon AI agents on 50 transistor-level analog, RF and mixed-signal design tasks. Public SKY130 task packages combine editable netlists and development benches with isolated, specification-based ngspice verifiers, including task-specific PVT sweeps and Monte Carlo checks.

    • Simulation
    • Layout

    CACE

    Characterization framework for analog and mixed-signal circuits, including condition sweeps, Monte Carlo analysis and datasheet generation. The maintained FOSSi implementation also orchestrates process-dependent DRC, LVS, antenna checks and extracted-netlist preparation through external simulation and layout tools.

    • Simulation
    • AI-ASSISTED

    vagen

    Python library for generating Verilog-A testbench stimulus and behavioral models, including voltage/current sources, clocks, digital buses and timed sequences. It emits Verilog-A source for an external simulator; typed validation and sequence construction help author repeatable analog-IP verification setups without providing a numerical solver.

    Development provenance

    The maintainer attributes the September refactor to AI. The retained implementation replaces assertion-based validation with typed exceptions across the generator and adds error/sequence regression coverage, beyond reorganizing files.

    • AI Design
    • AI Simulation

    AgenticSizing

    Uses a planner and role-specialized LLM agents to propose device-parameter updates and predict electrical metrics for an existing analog netlist. Provisional predictions guide the inner loop; a Cadence backend evaluates committed candidates against typed specifications, with deterministic mock simulation available for workflow tests.

    • Simulation

    CharLib

    SPICE-based standard-cell characterization tool producing Liberty timing and power data from YAML configurations. It evaluates combinational and sequential cells through a modified PySpice backend with ngspice or Xyce; supported procedures and model quality constrain the resulting library characterization.

    • Simulation

    SpiceBind

    HDL-first mixed-signal co-simulation bridge embedding ngspice circuits in Verilog through VPI. A time barrier coordinates HDL events with adaptive analog steps, including step cuts or retries at intervening digital changes; the early implementation is tested upstream with Icarus Verilog and Verilator, while other simulators require qualification.

    • AI Design
    • Simulation
    • AI-ASSISTED

    AnalogGym-Opt

    Sizes fixed-topology amplifier and LDO circuits with a relational-GNN GRPO policy, multi-objective rewards and Pareto tracking, using ngspice and SKY130. Optional PVT proxies guide candidate selection before corner checks; released CLI, skills and MCP tools expose evaluation and optimization workflows.

    Development provenance

    A Claude-credited expansion implemented the LDO evaluation environment, circuit-category environment dispatch and circuit import/validation tooling. The current project retains LdoEnv and its measurement/reward path.

    • Layout
    • AI-ASSISTED

    ALIGN

    Generates hierarchical analog layouts from SPICE netlists and circuit constraints. The flow annotates circuit hierarchy, builds parameterized primitive cells and assembles placed and routed GDSII geometry using technology-specific layout rules.

    Development provenance

    Claude-credited development added release-benchmark metrics aggregation and regression detection, connected to a Magic/ngspice execution matrix. The aggregation implementation remains in the current repository.

    • AI Design
    • AI Simulation
    • AI Layout
    • AI-ASSISTED

    Agentic AI Analog IC Auto-Designer

    Provides Claude Code agents for transistor sizing, layout construction and repair, and pre/post-layout verification using ngspice, Magic and Netgen. Four of six planned roles are released; the newer Miller OTA mechanism example explicitly does not demonstrate design convergence, and GF180 support remains unverified alongside the SKY130 default.

    Development provenance

    Claude-credited implementation added routing optimization, shared design-constraint handling and device-shaping algorithms. The retained shaping code preserves tie-group geometry and total device width within declared bounds.

    • AI Design
    • AI Simulation

    EvoLDO-Bench

    Benchmarks LLM reasoning about low-dropout regulators (LDOs), with separate SKY130/ngspice tasks for circuit edits, simulation setup and failure diagnosis. The reasoning track grades structured answers without tools; controlled tool tracks also evaluate execution and evidence handling.

    • AI Layout

    gLayout

    Generates analog device and circuit layouts from reusable Python primitives, placement and routing utilities, with DRC/LVS-oriented verification support across mapped open PDKs. The repository also includes an LLM fine-tuning and inference path that generates or repairs Python PCell code, so AI materially participates in the layout-generation workflow.

    • Simulation

    Libretto

    Standard-cell characterization flow generating Liberty tables and documentation from scripted cell definitions and SPICE analyses. It provides combinational and sequential characterization with process examples; supported cell templates, simulation conditions and table conventions must be checked when preparing a usable timing library.

    • AI Design
    • Simulation

    G-DiffPS

    Selects among six RF phase-shifter topologies and predicts component values with a graph-conditioned flow policy, using analytic circuit priors and ngspice feedback to meet phase, loss and matching targets.

    • Simulation
    • AI-ASSISTED

    ngspice

    Open-source SPICE circuit simulator for DC, transient, AC, noise and device-model analysis in analog and custom-IC workflows. It takes circuit netlists and model parameters and returns voltages, currents and other electrical quantities as plots or data files.

    Development provenance

    Claude Fable 5 is credited on the E-178 diode-noise repair incorporated into upstream ngspice. The retained code initializes sidewall noise slots when no sidewall model is present.

    • AI Layout

    Reticle

    Browser and native IC-layout editor with incremental geometric DRC and programmatic editing. An optional model-driven propose–verify–correct workflow edits layouts against bounded checks; its SKY130 rule subset and internal comparison APIs do not constitute a product-level LVS or tape-out signoff flow.

    • AI Design
    • Simulation

    LOADBench

    Dataset and benchmark for machine-learning analog design, covering 101 SKY130 op-amp topologies with ngspice benches and electrical performance data. Python metrics evaluate topology generation/selection, inverse sizing and multi-objective optimization, separating structural coverage from simulation-based performance comparisons.

    • Simulation
    • AI-ASSISTED

    EVAS

    Event-driven behavioral Verilog-A simulator that accepts Spectre-style testbenches and produces transient waveforms and machine-readable lint diagnostics. Its Rust engine evaluates voltage-mode behavioral models; it does not solve transistor-level SPICE networks through KCL/MNA.

    Development provenance

    Claude is credited on merged voltage-contribution classification code and a repair to the executable parser tests. The corrected implementation and tests remain in the canonical project.

    • AI Design
    • AI Simulation
    • AI-ASSISTED

    vaBench

    Benchmarks AI agents on behavioral Verilog-A model generation, bug repair and testbench writing across 400 circuit families and 1,200 tasks. A task-isolated Bash/EVAS runtime supports visible tests and a matched no-EVAS comparison; testbench tasks require agents to design stimulus and transient-analysis setup.

    Development provenance

    The maintainer merged an explicitly autonomous Codex implementation campaign that added bridge preflight, dual-simulator execution and EVAS evaluation runners. These runners remain part of vaBench.

    • AI Design
    • AI Simulation

    gmoverid-skill

    Agent skills and Python tools for gm/ID transistor sizing and characterization. The agent selects topology and sizing trade-offs, then visually checks characterization plots for physical or extraction problems; conventional lookup tables and ngspice scripts supply device data, sizing quantities and SKY130 PVT/Monte Carlo results.

    • AI Design
    • AI Simulation
    • AI-ASSISTED

    virtuoso-agent

    Uses an LLM to tune existing circuit parameters from Virtuoso/Maestro/Spectre measurements or remote HSpice results. An optional Maestro path also applies model-authored analyses, outputs and corners; the spec-derived path computes setup and pass/fail conventionally, with stopping controlled by specification checks or an iteration limit.

    Development provenance

    Claude-credited development added the HSpice backend, including remote execution, measurement parsing, netlist rewriting and CLI integration. The backend extends the existing Maestro/Spectre workflow.

    • AI Design
    • AI Simulation
    • AI-ASSISTED

    analog-agents

    Coordinates architect, designer and verifier agents across architecture decomposition, behavioral modeling, transistor-level design, pre-simulation review, Spectre verification, integration and PVT sign-off. Virtuoso bridge operations, iteration logs, cross-model review and a reusable design-knowledge wiki support the agent workflow.

    Development provenance

    Claude-credited development implemented the session-evolution backend and parasitic-netlist crawl/audit tooling. The session-analysis engine remains in the current project.

    • AI Design
    • Simulation

    AutoSizer

    Uses an LLM to choose transistor-sizing variables, ranges and optimization strategies, then runs ngspice-backed search. Its companion AMS-SizingBench supplies 24 analog and mixed-signal circuit configurations, with SKY130 examples and an outer strategy loop around numerical candidate evaluation.

    • AI Design
    • Simulation
    • AI-ASSISTED

    ARCS

    Generates and sizes circuits within predefined topology families from target specifications using an autoregressive model. Decoded candidates become ngspice netlists for electrical evaluation and reward-based training, with examples spanning converters, amplifiers and filters.

    Development provenance

    A Claude-credited implementation added the latent reward predictor and gradient-based refinement loop, alongside classifier-free guidance for circuit generation. The predictor and its training path remain in the project.

    • Simulation
    • AI-ASSISTED

    VAJAX

    JAX-based analog simulator that compiles Verilog-A device models through an OpenVAF-derived path and evaluates circuit equations on CPU or GPU. Public analysis code includes DC, transient and frequency-domain workflows; model coverage, backend setup and numerical behavior remain implementation-specific rather than universal SPICE compatibility.

    Development provenance

    Claude Code co-development credits accompany the SCCP optimizer and its production integration. The retained MIR pass propagates constants, tracks executable edges and removes dead blocks before JAX model code generation.

    • AI Design
    • AI Layout

    AMS-IO-Agent

    Uses LLM interpretation of pin plans and design intent to generate AMS I/O-ring schematics and layouts. Structured intent graphs guide pad placement and domain isolation, with Virtuoso SKILL generation, Calibre DRC/LVS checks and companion AMS-IO-Bench cases.