AMS Signals

Analog

    • Simulation
    • AI-BUILT

    Ngspice + OpenVAF Enhancements

    Claude-assisted development project extending ngspice SPICE simulation and OpenVAF Verilog-A compilation. Language features and correctness fixes are developed together through OSDI model integration; they are not automatically features of either upstream project.

    Development provenance

    The owner describes this repository as a Claude Code effort to enhance ngspice and OpenVAF. Its defining work includes compiler lowering and OSDI simulator callbacks; the attribution concerns these enhancements.

    • Design
    • Simulation
    • Layout
    • AI-ASSISTED

    vcli

    Rust CLI for concurrent Virtuoso sessions, exposing schematic edits, Maestro/Spectre runs, PSF results and SKILL layout helpers. A session registry and daemon dispatch commands locally or through SSH, returning structured output for scripts and agent workflows.

    Development provenance

    A Claude-credited campaign implemented OCEAN simulation automation and integrated setup, run, measurement, sweep and corner commands into the Rust CLI. The current simulation commands still use that OCEAN layer.

    • Design
    • Simulation
    • Layout

    virtuoso-bridge-lite

    Python and CLI bridge for local or remote Virtuoso schematic editing, SKILL layout operations and Maestro setup. It also runs standalone Spectre jobs and parses PSF results, with connection profiles for separately configured EDA hosts.

    • Design
    • Simulation

    Xschem

    Schematic capture and netlisting environment for hierarchical custom-IC designs, with Tcl scripting and open-PDK examples. It emits SPICE, Verilog and VHDL netlists and integrates simulator run control, waveform inspection and result backannotation with tools such as ngspice and Xyce.

    • Simulation

    scikit-rf

    Python toolkit for measured or simulated N-port RF networks, including S-parameter operations, calibration and transmission-line models. Vector fitting turns sampled frequency responses into rational models, with SPICE subcircuit export for fitted S-parameters, connecting RF characterization to circuit simulation.

    • AI Design
    • Simulation

    Razavi-Bench

    Benchmarks LLM answers to illustrated analog-circuit questions through direct QA, workspace-agent and experimental ngspice-assisted modes. Reference solutions and a shared rubric grade the final explanation, covering topics such as MOS devices, feedback and oscillators rather than circuit-performance closure.

    • Layout

    KLayout-PEX

    Parasitic extraction infrastructure connecting KLayout layouts and process stacks to Magic, FasterCap and experimental internal 2.5D extraction. KPEX also generates PEX25D interconnect descriptions and provides standalone validation, conversion and solver-input export; backend maturity varies and the project remains early-stage.

    • Layout

    Magic

    VLSI layout editor with design-rule checking, circuit extraction and parasitic extraction (PEX) for custom-IC workflows. Interactive editing and Tcl scripts operate on layout geometry, with technology files supplying the process-specific rules used by open PDKs.

    • Design
    • Simulation

    PyOPUS

    Python library and GUI for analog circuit sizing and simulation-driven optimization across process corners. Simulator adapters and performance extraction connect numerical search with sensitivity analysis, worst-case methods and yield-oriented design, integrating circuit evaluation with sizing decisions.

    • Layout

    ALIGN

    Generates hierarchical analog layouts from SPICE netlists and circuit constraints. The flow annotates circuit hierarchy, builds parameterized primitive cells and assembles placed and routed GDSII geometry using technology-specific layout rules.

    • Design
    • Simulation

    Analog Design Bench

    Benchmarks agents that edit analog and RF circuits to meet electrical specifications. Task packages combine starter netlists, ngspice testbenches and graded measurements, including SKY130 designs with task-specific PVT sweeps or Monte Carlo checks.

    • Design
    • Simulation

    Qucs-S

    Qt GUI for schematic capture, circuit-analysis setup and result visualization using ngspice, Xyce, SpiceOpus or Qucsator backends. Component libraries and plotting keep circuit editing and simulation in one application, with available analyses and device support depending on the selected engine.

    • AI Design
    • AI Simulation
    • AI Layout

    ViraStack AI Super Agent

    Cadence's commercial custom/analog AI agent operates across Virtuoso design tasks, ADE testbench creation and debug, circuit optimization, migration and layout exploration. September 2026 demonstrations show the agent diagnosing ADE failures and applying fixes, and generating multiple constrained layout prototypes for comparison.

    • AI Design
    • Simulation

    ASTRA

    Guides transistor sizing with an LLM and retrieved gm/ID knowledge. It initializes feasible designs, identifies influential transistor parameters and prioritizes staged Bayesian optimization, with a two-stage OTA example using a separately configured ngspice simulation environment.

    • AI Design
    • AI Simulation

    EvoLDO-Bench

    Benchmarks LLM reasoning about low-dropout regulators (LDOs), with separate SKY130/ngspice tasks for circuit edits, simulation setup and failure diagnosis. The reasoning track grades structured answers without tools; controlled tool tracks also evaluate execution and evidence handling.

    • AI Layout

    gLayout

    Generates analog device and circuit layouts from reusable Python primitives, placement and routing utilities, with DRC/LVS-oriented verification support across mapped open PDKs. The repository also includes an LLM fine-tuning and inference path that generates or repairs Python PCell code, so AI materially participates in the layout-generation workflow.

    • Design
    • Simulation
    • Layout

    IHP SG13G2 AMS Chip Template

    Provides a reproducible AMS chip template spanning analog schematics and simulation, cocotb/SystemVerilog digital verification, macro hardening, top-level assembly, DRC/LVS and extraction in IHP SG13G2. The 2026.08 release extends post-layout and parasitic-aware paths while keeping the project as an integration template rather than a new simulator or layout engine.

    • Layout

    KLayout

    Layout editor and verification platform for custom integrated circuits, with GDS/OASIS support. Python/Ruby scripts and parameterized cells automate geometry construction, while programmable DRC/LVS checks use technology-specific rules to examine layout and connectivity.

    • Simulation

    OpenVAF-Reloaded

    Community-maintained Verilog-A compiler that produces OSDI shared libraries for SPICE-class simulators. Extending the original OpenVAF, it fixes model-compilation issues and develops the OSDI 0.4 interface; numerical circuit analysis runs in a compatible host simulator.

    • AI Design
    • Simulation

    G-DiffPS

    Selects among six RF phase-shifter topologies and predicts component values with a graph-conditioned flow policy, using analytic circuit priors and ngspice feedback to meet phase, loss and matching targets.

    • Design
    • Simulation

    AnalogForge Agent

    Experimental workbench for template-based circuit proposals and bounded transistor-sizing search. Default runs use analytic fixtures; a separate ngspice/Xyce command executes prepared netlists and checks model dependencies before retaining simulation measurements.

    • Simulation

    ngspice

    Open-source SPICE circuit simulator for DC, transient, AC, noise and device-model analysis in analog and custom-IC workflows. It takes circuit netlists and model parameters and returns voltages, currents and other electrical quantities as plots or data files.

    • Simulation

    Xyce

    Sandia-developed SPICE-compatible circuit simulator with DC, transient, AC, noise and harmonic-balance analyses. Its C++ implementation supports MPI-based parallel execution and compact-device models, with an XDM netlist translator for adapting supported external SPICE syntax.

    • AI Design
    • AI Simulation

    Masala-CHAI

    Reconstructs SPICE netlists from schematic images using component detection and multimodal connectivity reasoning, with a V2 agent loop that revises candidates from judge feedback and optional ngspice simulation.

    • Design

    NetlistBench

    Benchmarks recognition, editing, hierarchy and structural equivalence of existing SPICE netlists in 2,342 cases across 24 task families. A deterministic canonical-IR grader checks submitted edits or structured answers, without treating structural agreement as an electrical-equivalence proof.

    • Design
    • Simulation

    LOADBench

    Dataset and benchmark covering 101 SKY130 op-amp topologies with ngspice testbenches and electrical performance data. Python metrics evaluate topology generation/selection, inverse sizing and multi-objective optimization, keeping structural coverage separate from simulation-based performance comparisons.

    • Simulation

    EVAS

    Event-driven behavioral Verilog-A simulator that accepts Spectre-style testbenches and produces transient waveforms and machine-readable lint diagnostics. Its Rust engine evaluates voltage-mode behavioral models; it does not solve transistor-level SPICE networks through KCL/MNA.

    • Design
    • Simulation
    • AI-ASSISTED

    vaBench

    Benchmarks behavioral Verilog-A model generation, bug repair and testbench writing across 400 circuit families and 1,200 tasks. A task-isolated Bash/EVAS runtime lets agents exercise visible tests, with a matched no-EVAS mode for comparing tool access.

    Development provenance

    The maintainer merged an explicitly autonomous Codex implementation campaign that added bridge preflight, dual-simulator execution and EVAS evaluation runners. These runners remain part of vaBench.

    • AI Design

    AnalogXpert

    Research implementation for analog topology synthesis that prompts an LLM with reusable circuit-design knowledge, checks generated netlists against structural rules, and iteratively asks the model to repair detected errors. The release also includes subcircuit libraries and real and synthetic evaluation data.

    • AI Design
    • AI Simulation

    ATLAS

    Paper-described SAR ADC flow that uses LLM agents to select and connect expert circuit templates, adapt testbenches and choose sizing ranges. Spectre simulation feedback and expert checks guide iteration; the reported workflow stops before layout.

    • Design
    • Simulation

    gmoverid-skill

    Python tools for transistor sizing through gm/ID characterization and lookup tables. Cached device sweeps yield widths and operating points for current, speed or gain targets, alongside ngspice examples and SKY130 PVT/Monte Carlo simulation scripts.

    • AI Design
    • Layout

    AnalogMaster

    Paper-described framework that converts circuit images into structured analog designs, refines device parameters, and continues into physical implementation. The public repository supplies circuit-image data, SKY130 model collateral, placement logic and A* routing code; its README explicitly says code and data are still being progressively refined.

    • AI Design
    • Simulation
    • AI-ASSISTED

    virtuoso-agent

    Uses an LLM to tune existing circuit parameters from Virtuoso/Maestro/Spectre measurements or remote HSpice results. A Markdown specification defines targets, variables and measurement rules, and the loop stops on a specification pass or an iteration limit.

    Development provenance

    Claude-credited development added the HSpice backend, including remote execution, measurement parsing, netlist rewriting and CLI integration. The backend extends the existing Maestro/Spectre workflow.

    • Design

    CircuitRubric

    Grades generated analog SPICE netlists by graph matching and relative device sizing. Its fixtures and Python grader identify topology, connectivity and sizing-ratio errors without a simulator or PDK; the score describes structure rather than electrical performance.

    • AI Design
    • Simulation
    • Layout

    PANDA

    Analog design framework combining LLM-guided topology generation and transistor sizing with placement/routing. Structured artifacts connect each stage to configured Virtuoso/Spectre and physical-design backends, with adapters for parasitic extraction (PEX) and post-layout simulation feedback.

    • AI Design
    • Simulation

    AnalogAgent

    Runs LLM agents that generate and revise analog-circuit solutions while a curator retains reusable lessons from executed attempts. The public MVP executes generated Python/PySpice against ngspice, checks task results, and feeds failures or measured outcomes back into the design loop.

    • AI Design
    • Simulation

    AutoSizer

    Uses an LLM to choose transistor-sizing variables, ranges and optimization strategies, then runs ngspice-backed search. Its companion AMS-SizingBench supplies 24 analog and mixed-signal circuit configurations, with SKY130 examples and an outer strategy loop around numerical candidate evaluation.

    • AI Design
    • Simulation

    AnalogSAGE

    Uses LLM agents for topology exploration and transistor sizing in SKY130 op-amps. Retrieved circuit knowledge and memory of earlier attempts guide topology proposals and sizing ranges, while Bayesian search evaluates candidates through ngspice feedback.

    • AI Design

    AnalogToBi

    Generates transistor-level circuit topologies from circuit-type tokens with a grammar-constrained language model. Device-net bipartite graphs encode component connections, and structural validity and novelty checks assess the generated topologies without measuring electrical performance.

    • AI Simulation

    ZeroSim

    Predicts amplifier performance from circuit topology and device parameters using a transformer surrogate. Training and evaluation target transfer to unseen topologies; separate ngspice scripts generate simulation data, while inference returns learned estimates rather than executing a circuit solver.

    • AI Design
    • Simulation
    • AI-ASSISTED

    ARCS

    Generates and sizes circuits within predefined topology families from target specifications using an autoregressive model. Decoded candidates become ngspice netlists for electrical evaluation and reward-based training, with examples spanning converters, amplifiers and filters.

    Development provenance

    A Claude-credited implementation added the latent reward predictor and gradient-based refinement loop, alongside classifier-free guidance for circuit generation. The predictor and its training path remain in the project.

    • Simulation

    cocotbext-ams

    Connects cocotb-driven Verilog/VHDL simulation to SPICE blocks through ngspice or Xyce shared-library interfaces. Digital changes drive analog voltage sources and threshold or hysteresis crossings return events to the HDL side, providing a lightweight AMS co-simulation layer rather than a separate analog simulator.

    • AI Design
    • AI Simulation

    AnalogCoder-Pro

    Uses multimodal LLMs to generate analog netlists and diagnose or repair candidates from ngspice results and waveform images. Circuit requests specify input/output ports, while released sample circuits and testbenches support generation and feedback experiments.

    • AI Design
    • Layout

    AMS-IO-Agent

    Uses LLM interpretation of pin plans and design intent to generate AMS I/O-ring schematics and layouts. Structured intent graphs guide pad placement and domain isolation, with Virtuoso SKILL generation, Calibre DRC/LVS checks and companion AMS-IO-Bench cases.

    • Design
    • Simulation

    AnalogGym

    Analog sizing benchmark with ngspice testbenches for amplifiers and LDOs, SKY130 examples and PVT evaluation. Optimizers update separate design-variable files, run electrical measurements and use the supplied extraction code or reinforcement-learning environments to evaluate candidates.

    • AI Design

    EEschematic

    Converts SPICE netlists into editable schematic descriptions using multimodal reasoning and visual feedback. Released notebooks refine symbol positions and wiring from rendered circuit images, producing a structured diagram representation rather than a physical IC layout.