AMS Signals

Digital

    • Verification

    cocotb

    Python coroutine-based verification framework for driving and observing Verilog, SystemVerilog and VHDL designs in HDL simulators. Triggers and testbench scheduling coordinate stimulus and checks with simulator events, allowing tests to use Python libraries alongside the simulator's execution engine.

    • AI Design
    • AI Synthesis
    • AI Verification
    • AI Layout
    • AI-ASSISTED

    CoreSmith

    Uses LLM agents to generate and repair RTL/testbenches, then drive Yosys synthesis, OpenROAD placement/routing and Magic checks toward GDS output. LangGraph coordinates the stages and backend repair loops, with explicit interruption and human-review paths when decisions are needed.

    Development provenance

    Claude-credited implementation added interface-contract checking and repair, then integrated it into the per-block RTL flow before testbench generation. The current pipeline calls this conformance stage.

    • Design
    • Synthesis
    • Verification

    Google XLS

    High-level synthesis (HLS) infrastructure with DSLX and experimental C++ frontends targeting XLS IR. Optimization and scheduling drive Verilog/SystemVerilog code generation, while documented property proving and equivalence tools check hardware computations alongside interpreter and native execution.

    • Verification
    • AI-BUILT

    iverilog-uvm

    Experimental Icarus-derived SystemVerilog simulator extending UVM, constrained randomization, assertions, functional coverage and DPI-C support. Development uses Claude under human review, with conformance tests tracking behavior against the unmodified Accellera library and language standards.

    Development provenance

    The maintainer attributes the bulk of this fork’s SystemVerilog/UVM implementation to Claude, with human direction and review. The attribution covers the fork’s extensions to Icarus Verilog.

    • Layout

    nextpnr

    Vendor-neutral, timing-driven FPGA place-and-route framework. Architecture backends consume synthesized netlists and device databases to pack, place and route supported FPGA families, with timing reports, constraints and optional GUI inspection.

    • Layout

    OpenROAD

    Physical-design implementation engine for floorplanning, placement, clock-tree synthesis, timing analysis and routing. It supplies the backend operations used within RTL-to-GDS flows; surrounding orchestration and agent interfaces are provided separately by projects such as OpenROAD-flow-scripts and OpenROAD-MCP.

    • Verification

    Pono

    SMT-based formal model checker for safety and liveness properties, with bounded, inductive and IC3-style algorithms. Its C++ implementation uses the Smt-Switch solver interface, with transition-system APIs for building verification applications and inspecting proof or counterexample outcomes.

    • Verification

    pyuvm

    Implements widely used UVM concepts in Python on top of cocotb, including components, factory, phasing, TLM, sequences and a developing register layer. The project deliberately does not claim complete IEEE 1800.2 coverage; its documentation identifies remaining register-model gaps and unimplemented UVM memory functionality.

    • Synthesis
    • Verification
    • Layout
    • AI-ASSISTED

    SiliconCompiler

    Modular hardware build system that defines EDA flowgraphs, manages inputs and results, and records provenance in compilation manifests. It orchestrates simulation and formal checking alongside synthesis and ASIC/FPGA APR, integrating tools such as Verilator, Yosys, OpenROAD and KLayout through a common tool interface.

    Development provenance

    Claude-credited flow work implemented an optional post-global-route timing-repair task and connected it to SiliconCompiler’s routing flow. The campaign also aligned the OpenROAD adapter and repair sequence.

    • Design
    • Synthesis
    • Verification
    • Layout

    Spade

    HDL for RTL design with a strong type system, zero-cost abstractions and pipelines with checked latency, compiling to Verilog/SystemVerilog. Its Swim toolchain manages packages and simulation tests, synthesizes through Yosys, and coordinates supported FPGA place-and-route with pin constraints and timing reports.

    • Design

    Surelog + UHDM

    SystemVerilog preprocessing, parsing and elaboration stack that exports UHDM design models. Serialized models and VPI access let downstream synthesis, simulation, lint and formal tools consume a shared representation without implementing their own complete SystemVerilog frontend.

    • AI Verification

    UCAgent

    Uses LLMs to analyze DUTs and generate unit tests, refining them from execution and coverage feedback. Configurable stages and checkers guide the workflow, with MCP collaboration allowing external coding agents to participate in test development and coverage closure.

    • Synthesis
    • AI-BUILT

    uhdm2rtlil

    SystemVerilog synthesis frontend that imports elaborated Surelog/UHDM designs into Yosys RTLIL. Surelog handles preprocessing and elaboration before translation, allowing Yosys optimization and technology-mapping passes to operate on the imported circuit.

    Development provenance

    The maintainer documents Claude implementing and refining the C++ UHDM-to-RTLIL frontend using UHDM dumps and RTLIL comparisons. The initial implementation and continued handler development support a major role in the translation core.

    • Verification

    Verilator

    Compiled SystemVerilog simulator and lint system that translates RTL into C++/SystemC models. The generated models execute with a simulation harness, with assertions, coverage collection and waveform output supporting testbench-driven verification and debug.

    • Verification
    • AI-ASSISTED

    vitamin

    Rust simulator for four-state Verilog/SystemVerilog execution with a native backend and VCD/FST waveform output. A source-to-runtime pipeline handles RTL and selected verification features, with differential tests against Icarus used to check behavior as language support expands.

    Development provenance

    Claude-credited implementation added SystemVerilog package-variable storage and import resolution, then extended package array parameters and initialization. Current elaboration code and regressions retain this package-support work.

    • Verification
    • AI-BUILT

    xezim

    Rust SystemVerilog simulator combining four-state event-driven execution, native compilation, UVM features and DPI/VPI interfaces. It translates HDL into an executable simulation representation and waveform traces, with public conformance tests tracking the behavior of implemented language features.

    Development provenance

    The maintainer describes AI agents implementing the parser, elaboration and event-driven simulation core through iterative coding and testing. The repository presents AI-assisted construction of core EDA software as its development premise.

    • Synthesis
    • Verification

    Yosys

    RTL synthesis framework for Verilog/SystemVerilog logic optimization and FPGA/ASIC technology mapping. Scripts compose reusable passes into synthesis flows, while formal transformations and solver-facing primitives support verification drivers such as SymbiYosys and EQY.

    • Verification

    Icarus Verilog

    Verilog compiler and event-driven simulator supporting a SystemVerilog subset. The compiler emits code for the VVP runtime, while VPI extensions connect testbenches and external tools; the separate iverilog-uvm project develops additional verification-language and UVM support.

    • Verification

    Kepler-Formal

    Open-source equivalence checker supporting gate-level combinational LEC, gate-level and RTL sequential equivalence, SystemVerilog file-list flows, RTL-to-gate SEC and Naja interchange inputs. It can export SEC problems to BTOR2 and distinguishes proved, partially proved, inconclusive and counterexample outcomes.

    • Design
    • Verification

    slang

    SystemVerilog frontend exposing parsing, elaboration, type checking and reusable design representations. Its standalone tool performs static analysis, while C++ APIs and pyslang Python bindings support source inspection, refactoring and integration into other compilers or developer tools.

    • Design
    • Verification

    Verible

    SystemVerilog developer-tool suite providing parsing, linting, formatting, language-server support and source-analysis utilities. Its parser handles unpreprocessed source for editor and single-file workflows, with reusable components for building additional HDL tooling without a full simulation or synthesis run.

    • Design
    • Synthesis

    Microsoft Kanagawa

    High-level hardware design language for HLS, using Wavefront Threading to express concurrency, synchronization and scheduling in an imperative program. A statically typed frontend and optimizing scheduler lower designs through CIRCT to SystemVerilog RTL, with libraries of composable hardware abstractions.

    • Design
    • Synthesis
    • Verification
    • Layout

    Amaranth HDL

    Python HDL and hardware construction toolchain with typed signals, reusable interfaces and a native simulator for testbenches and waveform generation. Its build system specializes device primitives, generates constraints and drives Yosys or vendor synthesis through FPGA placement, routing and bitstream creation.

    • Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    CIRCT

    MLIR/LLVM hardware compiler infrastructure with reusable hardware IRs and synthesis transformations. Compiler pipelines lower design representations for downstream tools, while LLHD models event-based execution and upstream formal-checking tools support verification of hardware behavior.

    Development provenance

    An explicitly AI-assisted change implemented the ESI ChannelArbiter’s pipelined grant scheduler, including its grant queue and datapath integration. The scheduler remains a selectable ESI component.

    • Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    Veryl

    HDL for RTL design with readable SystemVerilog transpilation, typed generics and integrated formatting, linting and package management. Its toolchain combines native simulator testing, external SystemVerilog and cocotb tests, and lightweight logic synthesis with early area, timing and power estimates.

    Development provenance

    The maintainer reports that Claude Code implemented module instantiation and much of the remaining native-simulator syntax after its overall structure was in place. The simulator remains integrated with Veryl’s native test command.

    • AI Design
    • Synthesis
    • Verification

    RTLScout

    LLM-driven RTL generation and optimization harness for Verilog/SystemVerilog, Spire HDL and Amaranth. Agents iterate against Verilator correctness checks and configurable Yosys/ABC, OpenROAD or AIG-derived cost metrics, with single-run, elite-pool and Pareto-search workflows plus an isolated re-evaluation path for shell-capable agents.

    • Verification

    EQY

    Yosys-based formal equivalence-checking flow that matches and partitions reference and transformed designs. Configurable proof strategies work on the partitions, making it possible to inspect which portions were proven and which remain failed, timed out or unproven.

    • Verification

    naja-scope

    MCP server exposing elaborated SystemVerilog structure to coding agents through bounded hierarchy, connectivity, driver/load, logic-cone and source-location queries. It supports RTL and post-synthesis gate netlists with Liberty libraries, giving an agent structural context without treating source search or waveform text as a substitute for elaboration.

    • Synthesis
    • AI-ASSISTED

    sv-elab

    Slang-based SystemVerilog elaborator that lowers synthesizable designs into a word-level netlist. It is integrated into current Yosys and OpenROAD synthesis tooling and can also be built as a frontend component, carrying design semantics into downstream synthesis flows.

    Development provenance

    Explicitly AI-assisted changes introduced an intermediate-representation layer and refactored frontend emission around it. The current Yosys backend retains the IR and builder separation.

    • AI Verification
    • AI-ASSISTED

    VerifyRTL

    Generates verification plans and properties with an LLM, runs Icarus simulations and SymbiYosys formal checks, and explains failures from execution traces. Simulator and solver results determine the verdicts, keeping coverage, bounded checks and unbounded proofs distinct.

    Development provenance

    A Claude-credited campaign implemented the Vivado XSim backend, RTL profiling and synthesis checks, with verification-pipeline integration. The backend and profiling modules remain in the project.

    • Verification

    Surfer

    Native and web waveform viewer for VCD, FST, GHW and transaction data, with extensible value translations. Client-server mode lets users inspect remote waveform files without copying them locally; the browser build offers a subset of native features.

    • Layout
    • AI-ASSISTED

    OpenROAD-MCP

    MCP server exposing persistent OpenROAD and OpenROAD-flow-scripts sessions to external agents. It runs physical-design commands and makes session history, reports and metrics available for inspection, while the underlying OpenROAD tools perform the layout operations.

    Development provenance

    A Claude-credited implementation introduced separate query and execute tools with Tcl command-permission checks. That permission model remains in the current TypeScript server; the evidence concerns the original subsystem implementation.

    • Design
    • Synthesis
    • Verification
    • Layout
    • AI-ASSISTED

    Dynamatic

    MLIR-based HLS compiler for C/C++ kernels that produces dynamically scheduled dataflow circuits and synthesizable RTL, addressing irregular memory and control behavior. Handshake IR and load-store queues organize execution, with C–RTL co-simulation, interactive dataflow visualization and a fixed-target Vivado synthesis/place-and-route flow for timing and utilization evaluation.

    Development provenance

    An explicitly Claude-assisted implementation added automatic loop initiation-interval instrumentation, covering compiler analysis, monitor insertion and VHDL monitor generation. The instrumentation remains integrated in the compiler.

    • Design
    • Verification

    RgGen

    Register-map and CSR generator producing SystemVerilog RTL, UVM RAL models, C headers and Markdown documentation. Ruby, structured-text and spreadsheet inputs feed an extensible bit-field, bus-protocol and writer system; current master adds an optional SystemRDL input plugin beyond the latest stable release.

    • Verification

    wave-mcp

    MCP backend exposing FST waveform values, SystemVerilog hierarchy, drivers, fan-in, X propagation and waveform comparisons. It combines pyslang design analysis with existing simulation artifacts to answer structured debug queries; simulation itself remains in the user's tool flow.

    • Design
    • Verification

    Chisel

    Scala-embedded hardware construction language for reusable, parameterized RTL generators. Chisel elaborates typed generator code and uses FIRRTL/CIRCT infrastructure to emit synthesizable Verilog or SystemVerilog; the repository also includes the lightweight svsim simulation-control library.

    • Verification

    eevee-rs

    Pre-alpha Rust SystemVerilog simulator with four-state event-driven execution, class elaboration and early runs of the unmodified Accellera UVM library. An event kernel and register-bytecode interpreter execute processes; broader UVM workflows and language conformance remain under development.

    • AI Design
    • Synthesis
    • Verification

    Dr. RTL

    Uses an LLM to rewrite RTL from synthesis timing feedback, then checks candidates with sequential equivalence and compares timing and area. Tool-derived verdicts determine which version advances, while iteration records preserve the attempted transformations and their evaluation results.

    • Design
    • Verification

    PeakRDL

    SystemRDL-centered toolchain compiling register descriptions into SystemVerilog CSR blocks, UVM RAL models, C headers and HTML documentation. A shared elaborated register model connects independently packaged exporters and IP-XACT import/export through a Python CLI, with custom plugins extending the supported outputs.

    • Verification

    RTLDebugDBKit + RTLTracer

    Elaborates SystemVerilog into an instance-level SQLite dependency database for static RTL debug. The companion RTLTracer follows signals, drivers, fan-in, fan-out and bit-level paths through that data; stored relations describe design structure rather than runtime waveform values.

    • AI Design
    • Verification

    LACE

    LangGraph workflow that turns natural-language RISC-V instruction-extension requirements into source-localized RTL edits. Agents decompose the instruction, analyze CPU structure and write interface/datapath changes; Verilator checks and riscv-formal/SymbiYosys return deterministic evidence for bounded repair and formal-verification loops.

    • Verification

    UVM 2020-3.2 Reference Implementation

    Accellera's SystemVerilog reference implementation for IEEE 1800.2-2020 UVM. The official download page lists UVM 2020-3.2 as the current library with an August 2026 modification date, while the public GitHub repository still identifies its public release line as 3.1, so the catalog keeps the downloadable release and GitHub state distinct.

    • Design
    • Synthesis

    Calyx

    Intermediate language and compiler infrastructure for accelerator generators. Calyx represents structural hardware and explicit control, applies reusable compiler passes, and emits Verilog or CIRCT-compatible output for downstream implementation.

    • Synthesis
    • Verification
    • Layout
    • AI-ASSISTED

    OpenADA

    Local agent-to-EDA interface for circuit simulation, measurement, synthesis and DRC/LVS operations. Drivers translate structured intent into native tool actions, including ngspice/Xyce, Yosys and KLayout paths, and return evidence while preserving the original design and result files.

    Development provenance

    The maintainer credits Codex with implementing the experiment runner and conformance-receipt verification work. These additions provide experiment orchestration and validation of recorded execution evidence within OpenADA.

    • Verification

    MCY

    Measures how well a self-checking testbench detects meaningful RTL faults using Yosys netlist mutations and formal filtering. Mutated designs run against the testbench, and result views help identify undetected changes that call for stronger checks.

    • Verification

    SymbiYosys

    Driver for Yosys-based formal verification flows, orchestrating bounded checks, inductive proofs and cover analysis. Task configurations select engines and solvers, while the driver manages their execution and collects proof status or counterexample traces for inspection.

    • Verification

    Sentinel DV

    Read-only MCP server for triaging UVM logs, assertions, coverage, regressions and waveform summaries. Exported verification artifacts are indexed in DuckDB for structured agent queries; replay operations produce reviewable commands rather than launching simulations or modifying RTL.

    • Verification
    • AI-BUILT

    WHAT

    Browser HDL debugger linking SystemVerilog hierarchy and source-level driver/load navigation with interactive FST waveform analysis. Users can follow signals between source and waveforms, inspect values at the current cursor and save the resulting debug session.

    Development provenance

    The maintainer reports using AI to implement the application’s main code, including its architecture, interface and functional logic. Building the HDL and waveform viewer was an explicit AI-programming experiment.

    • AI Design
    • Verification

    Duck RTL

    Agent-oriented Verilog build-and-verify loop with deterministic guardrails: an architecture ledger, Icarus compile gate, cocotb co-simulation against a Python golden model, and AST-derived FSM checks and diagrams. The host coding agent writes design artifacts while Duck RTL enforces interfaces and tool verdicts.

    • AI Verification

    HAVEN

    Uses an LLM to turn protocol specifications into UVM testbenches through a constrained DSL. Structured JSON intent is translated into SystemVerilog, then VCS execution and VC Formal feedback guide repair and testing of uncovered behavior.

    • Verification
    • AI-ASSISTED

    PyUCIS

    Python UCIS library for importing, merging and analyzing hardware verification coverage. CLI/TUI tools connect coverage reports, regression comparisons, test history and testplan closure; SQLite and NCDB storage support richer metadata, while format conversions have preservation limits.

    Development provenance

    The maintainer describes using AI to extend the pre-existing PyUCIS library. A Copilot-attributed implementation adds substantial test-history storage/query, testplan analysis, reports and CLI/TUI integration retained in the current code and released package.

    • Synthesis
    • Verification
    • Layout
    • AI-BUILT

    vivado_mcp

    MCP server keeping a persistent Vivado Tcl session for FPGA synthesis, implementation, timing and XSim operations. External agents can query the design, inspect utilization or timing reports and request bitstream generation without restarting Vivado for each command.

    Development provenance

    The maintainer reports creating this MCP server through conversations with Claude, including persistent Vivado sessions and tool commands. The account describes implementation of the server itself.

    • AI Verification

    Spec2Cov

    Generates testbenches from specifications and feeds Verilator or Questa coverage back to an LLM to target uncovered RTL behavior. The project includes hardware-module setups and experiment scripts for compiling tests, running simulations and collecting code-coverage results.