AMS Signals

Digital

    • AI Design
    • Synthesis
    • AI Verification
    • Layout
    • AI-ASSISTED

    Booley

    RTL workspace that runs a coding agent with EDA tools and checks recorded results against explicit acceptance goals. Typed simulation, lint, synthesis and Vivado FPGA implementation flows combine with waveform queries and sandboxed execution; the agent revises RTL and investigates failures while deterministic gates evaluate progress.

    Development provenance

    Claude is credited for correcting executable QA test logic to require mutation-goal source-file scopes. The canonical project retains the corrected test.

    • Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    Google XLS

    High-level synthesis (HLS) infrastructure with DSLX and experimental C++ frontends targeting XLS IR. Optimization and scheduling drive Verilog/SystemVerilog code generation, while documented property proving and equivalence tools check hardware computations alongside interpreter and native execution.

    Development provenance

    Gemini is credited for implemented block-level MLIR operations and translation logic. The canonical XLS project retains the operations and round-trip translation code.

    • Design
    • Verification
    • AI-BUILT

    iverilog-uvm

    Experimental Icarus-derived SystemVerilog simulator for UVM, constrained randomization, assertions, coverage and DPI-C, retaining the Verilog-1995 source translator. It runs implemented subsets of unmodified Accellera UVM; simulation and translation have documented gaps, and the maintainer warns against production or tapeout use.

    Development provenance

    The maintainer attributes the bulk of this fork’s SystemVerilog/UVM implementation to Claude, with human direction and review. The attribution covers the fork’s extensions to Icarus Verilog.

    • Layout
    • AI-ASSISTED

    OpenROAD

    Physical-design engine for floorplanning, placement, clock-tree synthesis, timing, routing and UPF isolation/level-shifter insertion over OpenDB. An experimental floating-random-walk field solver reads routed net geometry for capacitance extraction; Manhattan and dielectric-model limits remain, and upstream regressions do not establish signoff accuracy.

    Development provenance

    Claude is credited for correcting the web viewer shutdown to wait for its Tcl evaluation before interpreter teardown. The canonical project retains the synchronization code.

    • Verification
    • AI-ASSISTED

    pssc

    Portable Stimulus compiler translating PSS models through Zuspec IR into SystemVerilog verification classes and selected C/Python execution targets. Implemented backends cover action/control lowering and operation-model APIs, with target-specific refusals and dependencies; generated stimulus infrastructure does not synthesize DUT RTL or prove design correctness.

    Development provenance

    Claude is credited for implementing a HAL fixture plugin that generates a stateless C API through backend hooks. The executable plugin and differential tests remain in the current canonical tree; this supports assisted development of that contribution.

    • Verification
    • AI-ASSISTED

    sv-tests

    SystemVerilog language-feature test suite with runners for multiple parsers, simulators and synthesis tools. Small source cases and executable integration examples expose compatibility differences through generated reports; passing selected tests does not certify complete language support or production-design correctness.

    Development provenance

    Claude is credited for correcting the executable tagged-union formatting assertion. The canonical test suite retains the corrected expected value and assertion syntax.

    • Synthesis
    • AI-ASSISTED

    uhdm2rtlil

    SystemVerilog synthesis frontend that translates elaborated Surelog/UHDM designs into Yosys RTLIL. It can invoke Surelog in-process or read an existing UHDM database, then exposes the imported circuit to Yosys optimization and technology mapping; its equivalence and co-simulation suites validate the frontend.

    Development provenance

    The project documents iterative Claude implementation of SystemVerilog-to-RTLIL handlers, with credited executable harness corrections retained in the canonical project. The reviewed evidence does not establish that AI built most of the project.

    • Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    Veryl

    HDL for RTL design with readable SystemVerilog transpilation, typed generics and integrated formatting, linting and package management. Its toolchain combines native simulator testing, external SystemVerilog and cocotb tests, and lightweight logic synthesis with early area, timing and power estimates.

    Development provenance

    The maintainer reports that Claude Code implemented module instantiation and much of the remaining native-simulator syntax after its overall structure was in place. The simulator remains integrated with Veryl’s native test command.

    • AI Design
    • AI Synthesis
    • AI Verification
    • AI Layout
    • AI-ASSISTED

    Vibe-IC

    Claude Code plugin and MCP-EDA flow that turns natural-language or document specifications into RTL and drives simulation/formal, synthesis/STA, FPGA prototyping and OpenROAD/KLayout/Netgen physical implementation under deterministic compliance gates. Agent skills generate and repair artifacts while tool-produced evidence remains authoritative.

    Development provenance

    A Codex-signed canonical change implements the required post-global-routing design-repair policy in the physical-flow producer. Current code retains the policy overlay and executable regressions.

    • Verification
    • AI-BUILT

    xezim

    Rust SystemVerilog simulator for RTL, gate-level and UVM verification, with constrained randomization, coverage, DPI/VPI, SDF timing and optional native compilation. It also supports a UPF power-aware simulation subset and resolved real-number nets, including tested Verilog-AMS `wreal`, without a general analog solver.

    Development provenance

    The maintainer reports building the simulator with entirely AI-generated code through iterative coding, testing and correction. Current canonical code retains credited implementation contributions; the project-wide account is a maintainer report, not an independently reproduced code percentage.

    • Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    CIRCT

    MLIR/LLVM hardware compiler infrastructure with reusable hardware IRs and synthesis transformations. Compiler pipelines lower design representations for downstream tools, while LLHD models event-based execution and upstream formal-checking tools support verification of hardware behavior.

    Development provenance

    An explicitly AI-assisted change implemented the ESI ChannelArbiter’s pipelined grant scheduler, including its grant queue and datapath integration. The scheduler remains a selectable ESI component.

    • Design
    • Synthesis
    • Verification
    • Layout
    • AI-ASSISTED

    Dynamatic

    MLIR-based HLS compiler for C/C++ kernels that produces dynamically scheduled dataflow circuits and synthesizable RTL, addressing irregular memory and control behavior. Handshake IR and load-store queues organize execution, with C–RTL co-simulation, interactive dataflow visualization and a fixed-target Vivado synthesis/place-and-route flow for timing and utilization evaluation.

    Development provenance

    An explicitly Claude-assisted implementation added automatic loop initiation-interval instrumentation, covering compiler analysis, monitor insertion and VHDL monitor generation. The instrumentation remains integrated in the compiler.

    • Synthesis
    • Verification
    • Layout

    FuseSoC

    Manages reusable RTL cores, versioned dependencies, generators and build targets through CAPI metadata. Its configure/build/run commands use Edalize to drive simulation and FPGA synthesis/place-and-route flows, with required tools and device support supplied separately; it orchestrates these flows rather than providing a new simulator or implementation engine.

    • Design
    • Verification
    • AI-ASSISTED

    Icarus Verilog

    Verilog compiler and event-driven simulator supporting a SystemVerilog subset. The VVP runtime and VPI extensions support testbench-driven verification, while a separate source-translation target emits Verilog-1995 for supported newer constructs, with documented language and conversion limitations.

    Development provenance

    Claude is credited for implemented constant-function unpacked-array handling across elaboration and compile-time evaluation. The canonical project retains the code.

    • Verification
    • AI-ASSISTED

    Kepler-Formal

    Equivalence checker for gate-level combinational LEC and gate/RTL sequential equivalence, with SystemVerilog file lists, RTL-to-gate comparisons, Naja interchange and Python design inputs. Experimental VHDL SEC and BTOR2 export extend the checking paths; proved, partial, inconclusive and counterexample outcomes remain distinct.

    Development provenance

    Claude is credited for correcting internal-relation certification to use literal substitution rather than SAT assumptions. The canonical project retains the proof implementation and executable regressions.

    • Design
    • Synthesis
    • AI-ASSISTED

    Naja

    C++ and Python EDA framework for elaborating RTL, inspecting hierarchy and connectivity, and editing structural netlists. Its netlist CLI applies dead-logic elimination, constant propagation and primitive optimizations, with Verilog/SNL interchange and beta VHDL loading; companion tools provide formal checking and agent interfaces.

    Development provenance

    Claude is credited in a canonical implementation change that releases parameter properties before destruction, including Python-wrapper invalidation. Current Naja code retains these cleanup calls.

    • Layout
    • AI-ASSISTED

    OpenSTA

    Standalone static-timing analyzer consuming gate netlists, Liberty libraries, SDC constraints and parasitics. Tcl commands support timing checks and incremental analysis, with reviewed upstream extensions for scenes, LVF statistical timing and coupling-related noise delays; capabilities remain revision- and configuration-dependent.

    Development provenance

    Claude is co-credited for implementing configurable precision in JSON timing reports. The canonical path-report writer retains the report-digits setting for timing and capacitance values.

    • Design
    • Verification
    • AI-ASSISTED

    ROHD

    Dart framework for constructing hardware modules, simulating signal behavior and emitting synthesizable SystemVerilog. Its module graph, event-driven simulator and debug facilities connect design authoring with verification; generated RTL still needs a separate implementation toolchain for logic synthesis and physical design.

    Development provenance

    Copilot-credited implementation introduced module-scoped services for waveform capture, netlist output and inspection, with registry and lifecycle integration. The merged API and current registry/waveform implementations retain this substantial extension to ROHD.

    • Synthesis
    • Verification
    • Layout
    • AI-ASSISTED

    SiliconCompiler

    Modular hardware build system that defines EDA flowgraphs, manages inputs and results, and records provenance in compilation manifests. It orchestrates simulation and formal checking alongside synthesis and ASIC/FPGA APR, integrating tools such as Verilator, Yosys, OpenROAD and KLayout through a common tool interface.

    Development provenance

    Claude is credited for correcting executable Python tests for Yosys v0.70 tool manifests and synthesis warning counts. The canonical project retains the test logic.

    • Design
    • Verification

    Slang Server

    SystemVerilog language server providing editor completion, rename, references and diagnostics, plus elaborated-hierarchy browsing and selected-instance types, widths and parameters. Design/filelist configuration enables full-design context and waveform-viewer navigation; it is an editing and debug interface, not a simulator or formal proof engine.

    • Design
    • AI-ASSISTED

    Surelog + UHDM

    SystemVerilog preprocessing, parsing and elaboration stack that exports UHDM design models. Serialized models and VPI access let downstream synthesis, simulation, lint and formal tools consume a shared representation without implementing their own complete SystemVerilog frontend.

    Development provenance

    Integrated September changes explicitly credit Claude Code across a substantial frontend-correctness campaign: preprocessing, instance parameter resolution and multidimensional default-pattern expansion. The attribution concerns these improvements to the existing Surelog/UHDM stack.

    • AI Verification
    • AI-ASSISTED

    UCAgent

    Hardware unit-test agent that analyzes DUTs, generates tests and refines them from execution and coverage feedback. Direct model backends and MCP-connected coding agents share configurable stages and checkers, with optional formal and coverage workflows; heuristic, model and human review remain distinct quality gates.

    Development provenance

    Copilot is co-credited for implementing workspace-bound path checks in the MiniWorkflow word-count example. The canonical executable example retains absolute-path rejection and real-path containment checks.

    • Design
    • Verification

    Verilator

    Compiled SystemVerilog simulator and lint system supporting timing, assertions, coverage, constrained randomization and VPI-based testbench access. It translates designs into C++/SystemC models and can export elaborated JSON representations for downstream tooling; feature availability depends on the selected version and build.

    • Verification
    • AI-ASSISTED

    VUnit

    Unit-testing framework for VHDL and SystemVerilog, combining Python project configuration with HDL test libraries and simulator-driven execution. It discovers and runs test suites, manages compilation dependencies and reports results, supporting automated regressions while relying on separately installed HDL simulators.

    Development provenance

    Claude-credited development implemented package setup contexts and simulator-hook registration across multiple backends. The current package/runtime integration retains the hook registry and simulator dispatch.

    • Synthesis
    • Verification
    • AI-ASSISTED

    Yosys

    RTL synthesis framework for logic optimization and FPGA/ASIC technology mapping, with Verilog support and integrated sv-elab/slang SystemVerilog lowering. Scripts compose reusable passes, while SAT, equivalence and formal-model operations support direct checks and verification drivers such as SymbiYosys and EQY.

    Development provenance

    Claude is credited for implementing unpacked array-to-array assignments and ternary expansion in AST simplification. The canonical Yosys project retains the implementation and executable tests.

    • Design
    • Verification
    • AI-ASSISTED

    Chisel

    Scala-embedded hardware construction language for reusable, parameterized RTL generators. Chisel elaborates typed designs through FIRRTL/CIRCT to SystemVerilog, with integrated svsim simulation control and a current-branch bounded formal-checking path using BTOR2 and the external btormc model checker.

    Development provenance

    Claude Code is credited for updating executable Scala domain tests to preserve domains with the new firtool option. The canonical commit and current tests retain the changes.

    • Verification
    • AI-ASSISTED

    cocotb

    Python coroutine-based verification framework for driving and observing Verilog, SystemVerilog and VHDL designs in HDL simulators. The 2.1 release adds managed concurrent tasks and an experimental pytest regression plugin with fixtures and test selection; simulation still executes in a separately installed HDL simulator.

    Development provenance

    A Claude-credited correction changes the executable nox release backport tool to find consumed newsfragments from the release branch fork point. The correction remains in current code.

    • Verification
    • AI-ASSISTED

    Pono

    SMT-based formal model checker for safety and liveness properties, with bounded, inductive and IC3-style algorithms. Its C++ implementation uses the Smt-Switch solver interface, with transition-system APIs for building verification applications and inspecting proof or counterexample outcomes.

    Development provenance

    Claude-credited development integrated Btor2 fairness with justice checking and implemented Python access to liveness properties/provers. Current bindings retain the liveness API alongside safety compatibility.

    • Design
    • Verification
    • AI-ASSISTED

    slang

    SystemVerilog frontend exposing parsing, elaboration, type checking and reusable design representations. Its standalone tools and slang-tidy provide static analysis, while C++ APIs and pyslang Python bindings support source inspection and compiler integration; parsing assertions does not itself prove their properties.

    Development provenance

    Claude is credited for correcting parseGuess to handle member keywords that do not parse as members, avoiding a null dereference. The canonical project retains the parser correction and tests.

    • Verification
    • AI-ASSISTED

    vitamin

    Rust event-driven, four-state Verilog/SystemVerilog simulator with staged compile/elaborate/run commands and VCD/FST waveform output. A native executor and interpreter/VM cross-check paths support a documented language subset, with differential and conformance regressions; it does not claim unrestricted SystemVerilog, UVM or SDF support.

    Development provenance

    Claude-credited implementation added SystemVerilog package-variable storage and import resolution, then extended package array parameters and initialization. Current elaboration code and regressions retain this package-support work.

    • Synthesis
    • Verification
    • AI-ASSISTED

    ABC

    Logic synthesis and formal-verification system with an independent command shell and reusable algorithms. AIG optimization, technology mapping, equivalence checking and sequential property checking operate on supported logic models; assertion languages and RTL elaboration are normally handled by surrounding frontends.

    Development provenance

    Claude is co-credited for correcting Booth-multiplier result widths in executable bit-blasting code. The canonical implementation retains the product-width truncation before result extension.

    • Design
    • Verification
    • AI-ASSISTED

    LazyVerilog

    SystemVerilog language server for Neovim and VS Code, with class, package and UVM-aware completion, navigation, formatting and diagnostics. Slang-backed analysis and configurable lint rules accompany RTL code actions for module instantiation, wiring, arguments and sequential logic.

    Development provenance

    Claude-credited implementation introduced project-scoped compilation groups and connected cross-reference resolution to the requesting project. The current analyzer and background compiler retain the per-project compilation architecture.

    • AI Verification
    • AI-ASSISTED

    naja-scope

    MCP server for bounded RTL and gate-netlist hierarchy, connectivity, logic-cone and source queries, with optional schematic viewing and beta VHDL loading. Its runnable CVA6 benchmark evaluates AI agents answering post-elaboration verification questions with structural tools versus source search; the server itself returns deterministic design facts.

    Development provenance

    Claude is credited for implementing the MCP structural-query layer, including design loading, navigation, connectivity and cone operations. Current canonical code retains the contribution; the reviewed evidence does not establish that AI built most of the project.

    • Layout
    • AI-ASSISTED

    nextpnr

    Vendor-neutral, timing-driven FPGA place-and-route framework. Architecture backends consume synthesized netlists and device databases to pack, place and route supported FPGA families, with timing reports, constraints and optional GUI inspection.

    Development provenance

    Claude is credited for correcting RAMB36E1 width-9 parity connections in the Xilinx packer. The canonical project retains the implemented pin connections.

    • Synthesis
    • Layout
    • AI-ASSISTED

    OpenROAD-MCP

    MCP server exposing persistent OpenROAD sessions and tracked OpenROAD-flow-scripts jobs to external agents. Explicit targets cover synthesis through floorplanning, placement, CTS and routing, with validated overrides, current-run metrics and report access; the server supplies execution tools rather than its own model-driven optimization policy.

    Development provenance

    Claude-credited Python work implemented command-permission checks and separate query/execute tools. The documented one-to-one TypeScript port retains that policy and enforcement; attribution covers this retained contribution, not authorship of the port.

    • Design
    • Verification
    • AI-ASSISTED

    OpenTestability

    Gate-netlist testability toolkit computing SCOAP, COP and reconvergent-fanout metrics from Yosys JSON. It also inserts control and observation test points and exports modified netlists, while structural scores and optional ATPG-oracle feedback remain distinct from comprehensive DFT qualification or proven fault coverage.

    Development provenance

    Claude is co-credited for repairing the output-root option in SCOAP, COP and test-point analysis. The canonical CLI retains refreshed project paths and passes the selected root to output management.

    • AI Verification
    • AI-ASSISTED

    rIC3

    Hardware model checker with IC3/PDR, bounded and inductive engines over compiled transition systems. An optional experimental CIll workflow guides a language-model agent in proposing helper invariants and inspecting CTI traces; RTL preparation, reset assumptions and solver outcomes constrain that path.

    Development provenance

    Copilot is co-credited on the integrated sequential-correlation repair. The canonical transition-system implementation retains polarity-aware initialization handling when replacing latch variables.

    • Synthesis
    • Verification
    • Layout
    • AI-ASSISTED

    RTL Buddy

    CLI workflow manager for Verilog/SystemVerilog regression, simulation and formal checking, with current synthesis and place-and-route commands. YAML configurations dispatch external simulators, SymbiYosys, Yosys and OpenROAD and organize artifacts; supported tool versions and platform definitions bound each integrated flow.

    Development provenance

    Claude is co-credited for repairing SDC clock resolution and unresolved-clock reporting. The canonical Tcl reader retains structured read results and detection of clock commands inside unevaluated script bodies.

    • Design
    • Synthesis
    • Verification
    • Layout

    Spade

    HDL for RTL design with a strong type system, zero-cost abstractions and pipelines with checked latency, compiling to Verilog/SystemVerilog. Its Swim toolchain manages packages and simulation tests, synthesizes through Yosys, and coordinates supported FPGA place-and-route with pin constraints and timing reports.

    • Synthesis
    • AI-ASSISTED

    sv-elab

    Slang-based SystemVerilog elaborator that lowers synthesizable designs into a word-level netlist. It is integrated into current Yosys and OpenROAD synthesis tooling and can also be built as a frontend component, carrying design semantics into downstream synthesis flows.

    Development provenance

    Explicitly AI-assisted changes introduced an intermediate-representation layer and refactored frontend emission around it. The current Yosys backend retains the IR and builder separation.

    • Verification

    Verilua

    LuaJIT hardware verification framework with coroutine scheduling, signal handles and simulator control through native bindings. It supports interactive and scripted checking, waveform-oriented analysis and SystemVerilog coverage construction; simulator backends and their supported operations retain separate compatibility limits.

    • Verification
    • AI-ASSISTED

    EBMC

    Model checker for Verilog and SystemVerilog hardware with bounded and unbounded verification engines. Its implemented assertion subset is translated through engine-specific paths, so SVA support, proof status and counterexample interpretation depend on the selected encoding and reviewed revision.

    Development provenance

    Claude is co-credited for implementing implicit-net declarations for nested concatenations on continuous-assignment left-hand sides. The canonical Verilog type checker retains the recursive implementation.

    • Verification

    GTKWave

    GTK-based waveform viewer for Verilog VCD/EVCD and FST traces, with signal search, saved sessions and value translation for digital debug. Current master is GTKWave 4 pre-alpha; its format and build support must be distinguished from the separately maintained 3.3 LTS line.

    • Synthesis
    • Verification
    • Layout

    LibreLane

    ASIC implementation flow infrastructure orchestrating Verilog synthesis, lint and physical implementation with Yosys, Verilator, OpenROAD, KLayout and related tools. Classic and Chip flows retain configuration/state snapshots and PDK-dependent checks; the stable main branch accepts fixes while feature development proceeds separately.

    • Design
    • Synthesis
    • AI-ASSISTED

    Microsoft Kanagawa

    High-level hardware design language for HLS, using Wavefront Threading to express concurrency, synchronization and scheduling in an imperative program. A statically typed frontend and optimizing scheduler lower designs through CIRCT to SystemVerilog RTL, with libraries of composable hardware abstractions.

    Development provenance

    Copilot is credited for implementing per-export SystemVerilog packages and qualified named-type references. The canonical compiler retains the implementation.

    • Verification
    • AI-ASSISTED

    pssparser

    PSS parser, linked AST and semantic/lint tooling with C++ and Python interfaces, targeting the documented PSS 3.1 public-review draft. Annotation evaluation, reference queries and checker plugins support verification-model tooling; parsing or checking a PSS model does not execute stimulus, simulate RTL or certify standard conformance.

    Development provenance

    Claude is credited for implementing computed annotation values, parameter checks and export-reference support with parsing/linking tests. The canonical head retains the executable annotation module, supporting assisted development of this change.

    • Verification
    • AI-ASSISTED

    pyuvm

    Implements widely used UVM concepts in Python on top of cocotb, including components, factory, phasing, TLM, sequences and a developing register layer. The project deliberately does not claim complete IEEE 1800.2 coverage; its documentation identifies remaining register-model gaps and unimplemented UVM memory functionality.

    Development provenance

    Claude is credited for implementing the executable SimpleMem UVM-agent example and simulator build integration. The canonical project retains the example and build targets.

    • AI Design
    • Synthesis
    • AI Verification
    • AI-ASSISTED

    RTLScout

    LLM RTL generation and optimization harness for Verilog/SystemVerilog, Spire HDL and Amaranth, using fixed correctness and PPA evaluators. Its optional OpenCode design-library workflow also delegates directed-stimulus authoring to a verification agent before freezing an acceptance oracle; independent re-evaluation guards candidate admission.

    Development provenance

    Claude-credited development implemented the OpenCode execution backend and the sandboxed advisory/authoritative evaluation split. The current orchestration retains backend execution, evaluation storage and post-run rescoring.

    • Verification
    • AI-ASSISTED

    Surfer

    Native and web waveform viewer for VCD, FST, GHW and transaction data, with extensible value translations. Client-server mode lets users inspect remote waveform files without copying them locally; the browser build offers a subset of native features.

    Development provenance

    Claude is credited for correcting file-watcher paths and translator-plugin configuration in executable Rust code. The canonical project retains the fixes for bare filenames and local translator configuration.

    • Design
    • Verification
    • AI-ASSISTED

    FaultFlow

    Digital-test flow for Yosys netlists with SAT-based ATPG, fault simulation, scan preparation and structural DFT checks. CLI and Tcl-shell operations generate patterns and transformed design artifacts, with supported cell libraries, clock protocols and masked cross-domain paths defining the current verification boundary.

    Development provenance

    Claude is co-credited for repairing stalled SAT ATPG and multi-bit primary-input handling. The canonical ATPG implementation retains the real-input enumeration and launch/capture constraints.

    • AI Verification

    AssertLLM2

    Benchmark and execution framework evaluating language-model-generated SystemVerilog assertions from design specifications. Its pipeline combines syntax and formal checks, coverage and mutation-based bug detection through JasperGold, separating generated-property validity from usefulness against injected design faults and requiring licensed tools and model access.

    • Verification
    • AI-ASSISTED

    OpenCDC

    Structural CDC analyzer for SystemVerilog RTL and gate-level Verilog netlists, with hierarchy elaboration, cell-library mapping, constraints and multiple report formats. Static recognition remains incomplete for FIFO, handshake payload and some RTL hierarchy patterns; clean reports require clock/cell coverage review and do not prove protocol safety.

    Development provenance

    Claude Opencode is co-credited with implementing hierarchical gate-level netlist flattening. The canonical frontend retains recursive elaboration, parent-port binding and cycle/depth checks.

    • Verification
    • AI-ASSISTED

    rtl-buddy-cdc

    Experimental structural CDC/RDC analyzer using Yosys or slang elaboration, clock constraints and configurable synchronizer recognition. It emits findings and domain maps with waiver support; runs without SDC skip rule checking, and unknown domains or unsupported structures require explicit review.

    Development provenance

    Claude is co-credited for correcting synchronizer-chain recognition through per-stage synchronous-reset multiplexers. The canonical rule engine retains the reset-mux index and chain-walking logic.

    • Design
    • Verification
    • AI-ASSISTED

    Verible

    SystemVerilog developer-tool suite providing parsing, linting, formatting, language-server support and source-analysis utilities. Its parser handles unpreprocessed source for editor and single-file workflows, with reusable components for building additional HDL tooling without a full simulation or synthesis run.

    Development provenance

    The maintainer credits Gemini-generated changes in executable C++ container tests, then human review and refinement. The canonical project retains the corrected allocation-capacity assertions.

    • Verification
    • AI-ASSISTED

    rustdv

    Rust verification framework combining simulator-driven async coroutines with UVM-inspired components, phases, configuration, factories and sequences. Testbenches compile to native libraries loaded through VPI, with Icarus/Verilator integration and trace control; it follows selected UVM concepts without claiming IEEE 1800.2 conformance.

    Development provenance

    The maintainer credits Sonnet with corrected simulator code and executable clock tests. The canonical project retains the falling-edge test window and per-test read-only-phase transition.

    • Verification

    EQY

    Yosys-based formal equivalence-checking flow that matches and partitions reference and transformed designs. Configurable proof strategies work on the partitions, making it possible to inspect which portions were proven and which remain failed, timed out or unproven.

    • Design
    • Synthesis
    • Verification

    Calyx

    Intermediate language and compiler infrastructure for accelerator generators, combining structural hardware with explicit control. Reusable optimization passes emit Verilog or CIRCT-compatible output, while the included Cider interpreter and interactive debugger let users execute programs, step through control and inspect hardware state.

    • Design
    • Verification

    PeakRDL

    SystemRDL-centered toolchain compiling register descriptions into SystemVerilog CSR blocks, UVM RAL models, C headers and HTML documentation. A shared elaborated register model connects independently packaged exporters and IP-XACT import/export through a Python CLI, with custom plugins extending the supported outputs.

    • AI Design
    • AI Verification

    Veri-Sure

    Multi-agent RTL generation and repair framework sharing a structured design contract across architecture, debugging and formal-check agents. Temporal traces and dependency slices narrow edits, while model-authored assertions and reference models feed conventional simulation and proof tools; benchmark results remain author-reported.

    • Verification

    wave-mcp

    RTL debug server and CLI exposing waveform values, hierarchy, drivers, X tracing and pass/fail comparisons through pyslang and FST analysis. It can prepare sessions from existing FST or converted VCD/FSDB data and open a synchronized browser viewer; simulation and model-driven diagnostic decisions stay in the external workflow.

    • Verification

    CNSTLint

    SystemVerilog constraint linter with targeted rules for random variables, distribution weights, expression sizing and constraint coding hazards. Python checks operate on Verible syntax trees and produce source diagnostics; they do not solve constraints or establish the behavior of generated stimulus.

    • Verification

    uvm_bridge

    Bridges Python test code to a SystemVerilog UVM environment through DPI-C, exposing UVM configuration and test operations without recompiling Python scenarios. The public svuvm binding and simulator compatibility tests support mixed Python/UVM workflows; a suitable simulator and UVM library remain required.

    • AI Design
    • AI Synthesis
    • Verification
    • AI-ASSISTED

    HLS-Eval

    Benchmark framework for LLM generation and editing of C++ HLS designs, with Vitis HLS simulation, synthesis and co-simulation checks. Optional agents optimize parameterized dataflow implementations and FIFO settings using resource reports and LightningSim latency, retaining tool evidence and trajectories; users provide the selected EDA and model environment.

    Development provenance

    A Claude-credited implementation rejects empty generated C++ and timed-out compile, execution and synthesis results, with executable regression updates. The canonical project retains these checks.

    • AI Design
    • AI Synthesis
    • AI Verification
    • AI-ASSISTED

    VeriPower

    Coding-agent workflow for specification-driven RTL, UVM testbenches, simulation triage, lint/CDC, synthesis and timing/power analysis. Stage skills direct model decisions while a persistent engine tracks file versions, evidence and invalidated checks; the released flow depends on configured commercial EDA tools and libraries.

    Development provenance

    Claude is credited for implementing duplicate clock-name rejection and structured specification-tool failures. The canonical project retains the executable validation and regression tests.

    • Verification
    • AI-ASSISTED

    SymbiYosys

    Driver for Yosys-based formal verification flows, orchestrating bounded checks, inductive proofs and cover analysis. Task configurations select engines and solvers, while the driver manages their execution and collects proof status or counterexample traces for inspection.

    Development provenance

    Copilot is credited for correcting the executed rIC3 unsupported-mode diagnostic in the BTOR engine. The canonical project retains the diagnostic-code correction; this attribution does not claim implementation of the solver.

    • AI Verification

    CodeV-SVA

    Research implementation for language-model generation of SystemVerilog assertions, including RTL-grounded data synthesis and generation/evaluation clients. Its public workflow connects model inference to a JasperGold-backed service; licensed formal tools, model access and the selected experimental branch remain execution requirements.

    • Verification
    • AI-ASSISTED

    TraceWeave

    Simulation-debugging MCP server that relates logs, waveform events and RTL hierarchy/connectivity to trace failure evidence. VCD and optional native waveform backends support signal-history, driver and cross-run queries; external assistants can use those results, while the released analysis tools remain deterministic.

    Development provenance

    Claude is credited for implementing worker-thread offload and cooperative cancellation for waveform tools. The canonical project retains the server dispatch, cancellation and query checkpoints.

    • AI Design
    • AI Synthesis
    • AI Verification
    • AI Layout
    • AI-ASSISTED

    CoreSmith

    Agent-driven ASIC flow generating architecture, RTL and testbenches, with synthesis and OpenROAD physical implementation repair loops. Persistent architect sessions and module builds track input identities, block contracts and tool-grounded acceptance; a resumed build rejects changed inputs before continuing toward SoC integration and GDS.

    Development provenance

    Claude-credited implementation added interface-contract checking and repair, then integrated it into the per-block RTL flow before testbench generation. The current pipeline calls this conformance stage.

    • Verification
    • AI-ASSISTED

    RTLDebugDBKit + RTLTracer

    Elaborates SystemVerilog into an instance-level SQLite dependency database for static RTL debug. The companion RTLTracer follows signals, drivers, fan-in, fan-out and bit-level paths through that data; stored relations describe design structure rather than runtime waveform values.

    Development provenance

    The maintainer's Claude Code-attributed PR implements branch-context extraction, static branch verdicts and loop iteration metadata across the extractor and SQL schema. Current statement-walker code retains this branch-context machinery.

    • AI Verification
    • AI-ASSISTED

    VerifyRTL

    LLM-assisted RTL verification combines simulation, property generation and formal checking with a goal-aware proof strategy planner and executor. Counterexample replay, abstraction labels, helper invariants, assumption checks and bounded progress analysis help interpret tool-produced results and select techniques for unresolved properties.

    Development provenance

    A Claude-credited campaign implemented the Vivado XSim backend, RTL profiling and synthesis checks, with verification-pipeline integration. The backend and profiling modules remain in the project.

    • Layout

    Ṛta

    Deterministic SDC constraint-analysis toolkit for validation, reference resolution, coverage, conflicts and change review before STA. Its CLI exposes context-aware diagnostics and machine-readable results, while unresolved context and supported-command limits prevent readiness scores from establishing timing closure or signoff.

    • AI Verification

    EquivSVA

    Benchmark and evaluator for LLM-generated SystemVerilog assertions across equivalent RTL variants. Behavior families provide interface-level gold properties, controlled mutants and family-separated splits, with code for RTL equivalence, gold-property reachability, assertion soundness and mutation checks. The evaluator supports a bounded assertion subset.

    • AI Design
    • AI Verification

    ACE-RTL

    Agentic RTL generation and verification framework with Generator, Reflector and Coordinator roles. Model-generated RTL, testbenches or assertions are checked by EDA tools; focused failure diagnosis and accumulated context guide repair or restart, with native and Docker CVDP integration.

    • Design
    • Synthesis
    • Verification
    • Layout

    Amaranth HDL

    Python HDL and hardware construction toolchain with typed signals, reusable interfaces and a native simulator for testbenches and waveform generation. Its build system specializes device primitives, generates constraints and drives Yosys or vendor synthesis through FPGA placement, routing and bitstream creation.

    • Verification

    FCOVLint

    Functional-coverage source linter for SystemVerilog covergroups, coverpoints, crosses and related options. Its Python rules extend Verible-based syntax inspection to coverage coding hazards and conventions, without measuring achieved coverage or proving that a verification plan is complete.

    • Design
    • Verification

    RgGen

    Register-map and CSR generator producing SystemVerilog RTL, UVM RAL models, C headers and Markdown documentation. Ruby, structured-text and spreadsheet inputs feed an extensible bit-field, bus-protocol and writer system; current master adds an optional SystemRDL input plugin beyond the latest stable release.

    • Design
    • AI-ASSISTED

    Bender

    Manages RTL IP dependencies, ordered source sets and tool inputs for reusable hardware projects. Its Slang-backed SystemVerilog pickling can trim unreachable sources and rename module, package and interface declarations with their references; generated scripts prepare downstream EDA tools rather than performing synthesis or verification themselves.

    Development provenance

    A Claude-coauthored June 2026 code change added parse-failure safeguards for script generation and source pickling. The reviewed master implementation retains the corresponding safeguards, including refusing to rewrite partially parsed source trees.

    • Verification

    OpenCollate

    Local-first consistency checker for RTL and implementation collateral including Liberty, LEF/DEF, SDC and UPF. Parsers and cross-view rules expose mismatches and unsupported facts, with revision-specific formal paths on main; it complements dedicated verification tools without providing comprehensive low-power or physical signoff.

    • Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    Spire HDL

    Python-embedded RTL language with an explicit circuit IR, arithmetic construction and optimization, plus Verilog generation and Yosys-backed processing. Registered pipeline primitives and simulation/testbench utilities support hardware exploration; synthesis outcomes depend on the selected backend, constraints and target library.

    Development provenance

    Claude is credited for implementing the ABC optimization decorator and executable regression. The canonical Spire project retains the optimization logic after its package rename.

    • AI Design
    • Synthesis
    • Verification

    Dr. RTL

    Uses an LLM to rewrite RTL from synthesis timing feedback, then checks candidates with sequential equivalence and compares timing and area. Tool-derived verdicts determine which version advances, while iteration records preserve the attempted transformations and their evaluation results.

    • AI Design
    • Verification

    RTL-BenchMT

    RTL-generation benchmark maintenance artifacts and an LLM evaluation harness comparing original and revised prompts. Version 2 publishes fixes for 47 ambiguous cases across six datasets and 438 expanded RTL variants; pluggable model backends feed Icarus or cocotb-based functional checks.

    • AI Design
    • AI Verification
    • AI-ASSISTED

    LACE

    LangGraph workflow that turns natural-language RISC-V instruction requirements into source-localized CPU RTL edits. Language-model agents also generate and repair instruction models and formal properties, while Verilator and riscv-formal/SymbiYosys supply tool-grounded checks for bounded design and verification loops.

    Development provenance

    Claude is credited for adding a Verilator lint gate after arithmetic integration so invalid integrated CPUs halt before formal checks. The canonical project retains the gate and regression code.

    • Verification

    SVALint

    SystemVerilog assertion linter implementing additional Python rules over Verible syntax trees. It checks assertion coding patterns, event usage and related style hazards through a standalone CLI, providing source-quality diagnostics rather than proving that properties hold or capture the intended specification.

    • Verification

    UVM 2020-3.2 Reference Implementation

    Accellera's SystemVerilog reference library for IEEE 1800.2-2020 reusable verification environments, including components, phasing, sequences, transaction-level interfaces and register models. The 2020-3.2 kit documents standard deviations and compatibility extensions; it requires a suitable simulator, and the official download is newer than the public GitHub release line.

    • Design

    sv2v

    Translates synthesizable SystemVerilog into Verilog for toolchains with narrower language support. Haskell conversion passes lower constructs such as packages, interfaces and structs while retaining explicit unsupported-feature boundaries; translation prepares a design for downstream tools rather than performing logic synthesis or proving equivalence.

    • AI Synthesis
    • AI Verification
    • AI Layout
    • AI-ASSISTED

    OpenADA

    Agent skills and local EDA drivers for evidence-backed RTL review, Liberty-mapped synthesis, timing analysis and incremental layout checks. Hosted models diagnose results and select controlled experiments through implemented CLI operations; Yosys, Verilator, OpenSTA, KLayout and Netgen retain responsibility for execution and engineering verdicts.

    Development provenance

    The maintainer credits Codex with implementing the experiment runner and conformance-receipt verification work. These additions provide experiment orchestration and validation of recorded execution evidence within OpenADA.

    • AI Verification

    Sentinel DV

    Read-only verification-evidence server with packaged agent skills for regression triage, causal failure analysis and coverage planning. Models query bounded UVM, assertion, coverage and waveform evidence indexed in DuckDB; replay and run requests produce reviewable commands rather than executing simulations or editing RTL.

    • Verification
    • AI-BUILT

    WHAT

    Browser HDL debugger linking SystemVerilog hierarchy and source-level driver/load navigation with interactive FST waveform analysis. Users can follow signals between source and waveforms, inspect values at the current cursor and save the resulting debug session.

    Development provenance

    The maintainer reports using AI to implement the application’s main code, including its architecture, interface and functional logic. Building the HDL and waveform viewer was an explicit AI-programming experiment.

    • AI Design
    • Synthesis
    • Verification
    • Layout

    TuRTLe

    LLM RTL-generation benchmark framework covering specification-to-RTL, module completion and line completion. It combines API or local inference with simulation, equivalence, synthesis and physical-design PPA evaluation, including the NotSoTiny collection derived from real Tiny Tapeout designs.

    • AI Design
    • Synthesis
    • Verification

    ICRTL-Benchmark

    Benchmark for LLM RTL generation and PPA-oriented optimization across ten design problems, with specifications, testbenches, reference implementations and task prompts. Fixed Icarus/Yosys scripts evaluate candidates; an optional Synopsys flow adds VCS, Design Compiler and PrimeTime measurements without making the grader model-driven.

    • Verification

    sva-rtl-transpiler

    Prototype translator from a supported concurrent-SVA subset into RTL checkers and immediate assertions for open formal flows. It consumes slang JSON ASTs; single-clock assumptions, bounded consequents, partial sequence composition and delayed failure signals constrain translation and bounded-check depth selection.

    • AI Design
    • AI Verification
    • AI-ASSISTED

    CVDP Benchmark

    Benchmark and evaluation harness for LLMs and agents tackling RTL generation, repair, testbench and assertion tasks. Direct-model and repository-based agent workflows run open-source or licensed EDA checks, with separate comprehension scoring and task-specific tool requirements.

    Development provenance

    Claude is credited for implementing the executable Docker build steps for the benchmark simulation environment. The canonical project retains the EDA-tool and Python-package installation logic.

    • AI Design
    • Synthesis
    • Verification
    • AI-ASSISTED

    VeriRL

    OpenEnv environment for training and evaluating agents on synthesizable Verilog tasks. Agents write RTL and explicitly invoke Icarus compile/simulation, Yosys synthesis and optional SymbiYosys formal checks; deterministic EDA outputs and weighted scoring provide the environment's ground truth.

    Development provenance

    Claude is credited for implementing the VeriRL environment client and action/observation contracts, with subsequent training infrastructure contributions. Current canonical code retains the contribution; the reviewed evidence does not establish that AI built most of the project.

    • Verification
    • AI-ASSISTED

    PyUCIS

    Python UCIS library for importing, merging and analyzing hardware verification coverage. CLI/TUI tools connect coverage reports, regression comparisons, test history and testplan closure; SQLite and NCDB storage support richer metadata, while format conversions have preservation limits.

    Development provenance

    The maintainer describes using AI to extend the pre-existing PyUCIS library. A Copilot-attributed implementation adds substantial test-history storage/query, testplan analysis, reports and CLI/TUI integration retained in the current code and released package.

    • Synthesis
    • Verification
    • Layout
    • AI-BUILT

    vivado_mcp

    MCP server keeping a persistent Vivado Tcl session for FPGA synthesis, implementation, timing and XSim operations. External agents can query the design, inspect utilization or timing reports and request bitstream generation without restarting Vivado for each command.

    Development provenance

    The maintainer reports creating this MCP server through conversations with Claude, including persistent Vivado sessions and tool commands. The account describes implementation of the server itself.

    • AI Verification

    Spec2Cov

    Generates testbenches from specifications and feeds Verilator or Questa coverage back to an LLM to target uncovered RTL behavior. The project includes hardware-module setups and experiment scripts for compiling tests, running simulations and collecting code-coverage results.

    • Layout

    OpenTimer

    Parallel incremental static-timing analysis engine with C++ APIs and a command shell. It reads supported netlist, Liberty and SDC inputs to construct timing graphs and report paths or slack; its constraint and library coverage should be evaluated independently from other STA implementations.