As observed November 7, Qualcomm advertised a Toronto Analog Design internship for 12 or 16 months beginning in May or June 2027. Possible assignments include SystemVerilog analog behavioral models, AMS co-simulation to validate them, simulation-data peer review and testbench-performance metrics, with analog, digital, firmware and system teams. The application feeds multiple project-specific roles, so these are possible duties rather than completed work or a promise that every intern receives the same assignment. The Event uses the observation date because a reliable first-publication date is unconfirmed; 2027 is the planned placement year.
An employer-attributed TYLsemi LinkedIn role observed October 25, 2026 describes high-current integrated-voltage-regulator verification. It assigns Verilog-A and SystemVerilog RNM models for power stages, integrated inductors, the power-delivery network and analog blocks; analog/digital co-simulation; and testbenches for load transients, loop stability, ripple, protection and startup/shutdown. Duties also include PVT/Monte Carlo regressions and simulation-to-lab correlation. The first publication date is unconfirmed, so this Event uses the observation date of the retained advertisement, not a claimed October hiring launch.
ADI posted AMS Design Verification Intern R267539 for its High-Performance Power Group in Milan, with a possible master’s thesis. The group designs display, lighting and cloud-power ICs. Advertised training covers verification planning, Verilog-AMS and SystemVerilog analog-block models, AMS simulations, state-machine checks, analog assertions and metric-driven SystemVerilog/UVM environments combining DMS and AMS at IP and top level. This records the current internship posting, not the launch of a new training program or completed student work.
Apple posted London internship 200688723 for its AMS IP team. The project develops property sets for hardware-model functional coverage, formalizes SVA properties, executes formal proofs and studies model-accuracy versus proof-convergence tradeoffs. It also extends the framework to integrate properties at higher levels for system verification. The posting describes proposed intern work within an AMS IP organization; it does not report completed proofs or a deployed formal flow.
Skyworks posted San Jose co-op 78610 within the Mobile Solutions Division Software Engineering group. It assigns LLM agents connected to circuit simulators such as Spectre/Virtuoso and ADS, RAG over design documents and PDKs, and agent-performance evaluation on LNAs, PAs, switches and bias circuits in Si/SOI processes. The project includes schematic and simulation automation alongside layout tasks. January-June 2027 is the advertised work term. This analog/RF circuit-design research mandate is distinct from the earlier mixed-signal verification-platform co-op; neither posting demonstrates completed deployment.
Microsoft posted a Senior Quantum Analog Mixed-Signal Verification Engineer role assigning the Quantum 1st Party Hardware ASIC team system-wide AMS models, simulation environments and test plans. It combines analog and digital blocks across multiple SoCs, supplies behavioral models to full-chip digital verification, and establishes standardized AMS verification/modeling methodology with peers. Qualifications include UVM/OVM, Spectre AMS or Synopsys XA, and modeling corners and process variability. AI-tool use is a general work requirement rather than a specified model-generation method. This records an advertised infrastructure mandate, not deployed quantum-SoC verification results.
Atrisa posted a Founding Analog Design Engineer role in Bengaluru on its Y Combinator recruiting page. The company describes building AI agents for analog circuit design. The role designs, simulates and verifies analog/mixed-signal blocks and works with software and AI engineers to turn circuit-design problems into tools and evaluations. It includes specification tradeoffs, schematic design, SPICE simulation, layout review and silicon validation. This is an advertised circuit-design and evaluation mandate, not evidence that agents autonomously complete specification-to-layout designs or have achieved silicon results.
Awani Khodkumbhe and Qualcomm-affiliated coauthors publish RFChipAgent, a human-supervised LLM-agent flow for analog/RF design. It connects document retrieval, topology selection, schematic and testbench assembly, simulation-guided optimization, and operating-point and stability checks. The reported case is a GF22FDSOI 60 GHz wideband LNA. The paper is a preprint submitted for possible publication, not a product release, measured-silicon result or evidence of company-wide adoption. Khodkumbhe also lists UC Berkeley affiliation.
HRL Laboratories' Qubit Systems Laboratory posted an AMS verification role for quantum-control cryogenic CMOS. It assigns Verilog-A/AMS, wreal and SV-RNM models aligned with transistor-level implementations; UVM-AMS environments, SVA/PSL and coverage; regression infrastructure; and block-to-top-level integration for ADCs, DACs, PLLs, LDOs, SerDes and power-management blocks. Model correlation spans PVT/corner simulation and later measurements. The employer identifies HRL as an IBM company. These are advertised responsibilities, not demonstrated model accuracy.
On October 5, Bosch Service Solutions listed a Valencia DMS Verification Engineer role for mixed-signal SoCs. The position defines the split between DMS and digital verification and model/schematic equivalence, validates behavioral-model accuracy and performance against circuit simulations and measurements, and debugs RTL, gate and schematic behavior. It also assigns verification planning, regressions, functional/code coverage and UVM infrastructure improvements. The posting is a hiring mandate and does not establish measured verification outcomes.
On October 5, IMMS listed an Erfurt student project to extend an existing Python framework for generating behavioral circuit models. The project adds signal-name classification, analog/digital structure detection and recognition of circuit classes, then develops suitable model generators and integrates and validates them. Verilog-AMS is named as an example modeling language. The listing accepts mandatory internships and student research or thesis work, with an application deadline of December 31, 2026. It does not describe the framework as AI-based.
Infineon's Bengaluru Senior Staff Engineer Analog Mixed-Signal Verification posting assigns AI-based SystemVerilog real-number behavioral models with speed/accuracy tradeoffs for pre-silicon verification. The role leads automotive subsystem and analog-on-top full-chip verification, develops AMS plans, SPICE-netlist integration, checkers, assertions and coverage, and models bandgaps, LDOs and buck-boost regulators. This is an advertised development and methodology-leadership mandate; the posting does not disclose an AI algorithm, model-generation results or production adoption.
On October 5, MediaTek listed Singapore internships for 2027 covering mixed-signal verification and design automation. The verification role assigns analog/RF macro models for system co-simulation, Verilog/wreal models of RF calibration engines and analog leaf cells, and RF-digital testbench templates. A preserved 2026-internship listing describes the same RF modeling and testbench duties, so the 2027 listing is grouped with that recruiting history rather than treated as a new modeling method. The automation role covers Python, EDA tools, data analysis and exploration of AI for simulation, layout, verification and design workflows. The listings establish advertised student work, not a newly deployed modeling or AI platform.
Melexis posted Bevaix internship/master's-thesis project 3932 for automotive sensor IC mixed-signal design verification and system integration. The six-month 2027 project assigns Claude Code workflows, test-case development, and automated classification and root-cause analysis of simulation/verification failures. SystemVerilog/Verilog is essential; UVM is beneficial. Optional work compares Chipstack with Claude. Deployment into real projects and efficiency improvements are expected project results, not demonstrated outcomes. The retained official timestamp is October 5 at 20:00 UTC; 2027 identifies the work cohort.
Micron advertised October 5 LinkedIn role JR113919 for block-to-full-chip AMS verification, power-loss/brownout checks and agents for requirements-to-test extraction, triage, failure clustering, waveform guidance and coverage gaps. Related official JR114263, dated October 8, adds behavioral/schematic models accurate enough for each verification objective. Both require validated engineering data, human review and evaluation of AI-output usefulness and limitations. Preferred experience measures reduced manual effort, faster debug, traceability or verification completeness; these are evaluation criteria, not reported improvements. The distinct requisitions are grouped as an advertised development mandate.
On October 5, SiTime listed an Ottawa ASIC Digital Verification Co-op for sixteen weeks beginning in January 2027. The student role contributes to mixed-signal PLL IC development by learning the verification environment and testbench and writing test cases for ongoing projects. Verilog, SystemVerilog, UVM, Python and Tcl knowledge are welcomed. The posting does not explicitly assign RNM model development to the Co-op.
Marvell posted Singapore AMS Verification Intern – Master’s Degree (2604802) on September 30, 2026. The role assigns verification planning, testbench development and simulation checks for broadband amplifier circuits. Its profile requests control/feedback and automatic-gain-control knowledge; Verilog and Verilog-A are desirable programming experience, rather than explicit commitments to RNM/UVM or model generation. This Event records AMS verification recruitment, not deployed practice; unrelated lab-only validation internships are not included.
Micron posted Hyderabad Staff Engineer, Analog Design role JR113578 for NAND Flash circuits including charge pumps, regulators, ADCs/DACs, references and sensor interfaces. It assigns development and evaluation of AI agents for specification-to-check extraction, schematic or connectivity review, and verification debug. Reusable workflows connect engineering data, scripts, simulation outputs and design checks, with validation and human review before decisions. These pre-silicon review tasks extend beyond the separate layout-automation and simulation-orchestration duties; the posting does not establish AI-generated circuit topology or achieved deployment benefits.
onsemi advertised Senior Director, AI NPD Platforms & Engineering Intelligence role 2506790 to define and govern agentic-AI semiconductor development. Duties include analog and verification agents, AI-enabled circuit design and architecture exploration, and an approved agent library with qualification, validation, versioning, release and human-review processes. The role spans additional disciplines, but circuit/architecture and verification work provide the qualifying scope. It is a development and governance hiring mandate, not evidence that the proposed platform or productivity gains have been delivered.
Keysight advertised EDA AI/ML Software Intern role 54582 in Calabasas, with retained listings dated September 29. The MS/PhD internship explores AI applications in RFIC/analog schematic generation alongside layout automation, device modeling and design optimization. Responsibilities include Python ML prototypes, training/evaluation pipelines and integration into desktop software. Schematic-generation exploration is the qualifying design task; the advertisement does not establish topology invention, autonomous circuit synthesis or signoff-quality generated designs.
In a Synopsys announcement, MediaTek vice president Ching San Wu describes continuing collaboration on the Agentic AI AMS Platform for creating, optimizing and implementing analog/mixed-signal designs. He distinguishes this work from an earlier deployment of SmartFloorplanning. The release schedules broader AgentEngineer and Autopilot availability for the end of 2026. This records a named customer-side statement about collaboration, not completed deployment of the announced AMS platform or measured company-wide design productivity.
Cadence posted Mixed-Signal Systems and Verification Engineer R55855. The assigned work develops accurate, simulation-efficient SystemVerilog analog/RF behavioral models, verifies them against analog schematics, integrates them with RTL, and checks analog functionality against specifications using testbenches, scenarios and assertions. Qualifications name RNM, UDN/UDT/UDR, wreal, Verilog-AMS and analog assertion-based verification. Modeling and verification results are documented for formal review. This records an engineering hiring mandate rather than a product release or a reported customer deployment.
A Texas Instruments Battery Charging Products job posting describes AMS verification of battery-management ICs. Its responsibilities include Verilog-A/AMS and wreal RNM behavioral models for top-level simulation, testbenches combining schematics, models and RTL, analog checks during simulation and after processing, RTL and gate-level regressions, and functional coverage through tape-out. UVM, scripting and interest in AI-based verification automation are preferred qualifications. A preserved copy identifies Santa Clara requisition 25018210 and a September 25, 2026 posting timestamp.
NXP posted Toulouse internship R-10066989 on September 23 for AI-agent behavioral-model migration and mixed-signal stimuli/testbench generation, using Verilog/SystemVerilog and Verilog-AMS. Evaluation covers code quality, test-scenario coverage, automation rate, time savings and robustness, with regression checks and documented limitations. October 5 role R-10067009 covers AI-generated HDL AMS models and an oscillator/ADC/supply Golden Library. Related October 6 Design Enablement role R-10067212 assigns Python agents, LLM/RAG and surrogate-model generation, verification and qualification; its model language is unspecified. These grouped research advertisements propose evaluation work rather than demonstrate successful deployment.
On September 23, NXP listed a Toulouse internship to prototype and evaluate AI-assisted verification-component generation for digitally controlled mixed-signal IP, particularly DC/DC converters. The project analyzes specifications for interfaces, control sequences and faults, generates reusable SystemVerilog/UVM components and coverage, and proposes assertions for protocols, timing, forbidden states and fault responses. Generated components are to be integrated and tested on representative examples, with robustness and limitations evaluated.
Apple posted Analog Mixed-Signal Design Software Engineer role 200684916 on September 22, assigning agentic-AI orchestration for analog design data and a registry for agent versioning, rollback and audits, with human approval of agent changes. Related September 30 CAD role 200686566 assigns agent tuning, evaluation data, quality metrics and EDA integration across custom/analog design and other chip-design flows. These are advertised design-platform responsibilities, not evidence of autonomous analog architecture or behavioral-model generation; the postings do not establish a shared team.
On September 22, NXP listed a six-month internship starting in the first quarter of 2027 within its Sophia Antipolis Secure Transactions and Identification verification team. The project concerns NFC SoC power management, including power gating, reset, clocking and wreal analog representations. It assigns SystemVerilog test scenarios, SVA, coverage analysis and Jasper formal property verification, alongside investigation of AI/ML approaches for analog and mixed-signal verification. The AI work is exploratory.
An employer-supplied Allegro MicroSystems recruiting job posting dated September 21 describes top-level AMS testbenches, Verilog-AMS/RNM/wreal models, and checks of power transitions, brownouts, POR, POK and UVLO over voltage and temperature corners. A related Richardson team-lead posting checked on October 5 assigns Power IC verification strategy, reusable SystemVerilog/UVM infrastructure, behavioral-model development, requirements-to-test traceability, safety checks and exploration of AI automation. Both are public hiring mandates.
Apple posted a Digital/Mixed Signal Modeling/Verification Engineer role for analog and RF blocks within a large SoC. The description assigns SystemVerilog RNM models with built-in checks, selecting the necessary modeling accuracy for each verification objective, assertions that define analog/digital specification checks and digital verification pass criteria, AMS environment setup with analog designers, and debugging digital-on-top chip testbenches. The scope includes power regulators, bandgaps, data converters, RF blocks and PLLs.
As observed September 14, Cirrus Logic listed an Analog Mixed Signal Modeling & Verification Engineer role for Austin, Chandler and Greensboro. It assigns equivalent models reused across analog design, UVM verification and HW/SW validation; SV-RNM, SV-UDT and Verilog-AMS; DMS/AMS plans and platforms; regression debug; and verification-component reuse in AMS-UVM. The original UL-01 page is now unavailable. Related current UL-02 role, observed October 25, repeats those duties and adds architectural exploration and design-partitioning input. The postings establish a reusable-model methodology hiring mandate, not measured deployment. No reliable first-publication date is exposed, so the September observation date remains.
Micron advertised Richardson internship JR110765 in its HBM Architecture team, with a retained listing dated September 14. The role evaluates clock distribution, WDQS timing, PLL concepts, jitter, noise sensitivity and IO timing margins, compares alternative clock architectures and supports architecture-level decisions. It assigns LLM/GenAI engineering workflows for analysis and data evaluation, and links AI assistance to design exploration. This is an advertised analysis mandate, not proof of AI topology synthesis or HDL model generation.
Synopsys posted a Bengaluru product-engineering role for customer simulation and verification engagements. The position covers regression throughput, compilation and elaboration bottlenecks, debug, assertions, coverage and reference flows for block through full-chip verification. When needed, its AMS responsibilities include analog/digital co-simulation, behavioral models, Verilog-AMS integration and convergence trade-offs. AMS experience, including balancing accuracy and performance, is a preferred qualification. This is a customer-support mandate rather than evidence of a particular customer deployment.
The DVCon Japan program lists a tutorial by COSEDA presenters Thilo Vörtler and Karsten Einwich on SystemC and SystemC-AMS virtual prototypes. Its published scope covers executable specifications for heterogeneous systems, analog/digital/software test development and reference models for implementation verification. The tutorial also previews future SystemC-AMS standardization; a preview is not a formally issued standard.
The DVCon Japan program lists an SV-MSI update by Abhijit Madhu Kumar, identified as a Cadence Principal Solutions Engineer. It describes proposed interoperability between logic nets and RNM/nettype representations toward IEEE 1800-2028, alongside the SV-AMS and UVM-MS roadmap. These are presented proposals and roadmap directions, not already published standard requirements or released functionality.
Infineon posted Graduate - Analog Mixed-Signal Design Verification Engineer role HRC1763746 with an official September 9, 2026 date. It assigns Verilog-AMS/SystemVerilog model generation and maintenance, testbenches, nominal/corner simulation, fault injection and regressions. Related Andover and Shanghai internships observed October 5 cover behavioral models, AMS IP/SoC environments, RTL/model integration and model-quality checks. January/summer 2027 are planned employment starts. The official graduate date is the earliest verified publication among these grouped roles; the internships' first publication dates remain unconfirmed. These are hiring requirements, not deployed practices.
The MLCAD 2026 program lists LOADBench with Stefan Uhlich, Lorenzo Servadei and university coauthors in the September 9 analog-design session. The work provides more than 100 SkyWater130 op-amp topologies, annotations and ngspice testbenches, with benchmarks including structural circuit generation and topology selection as well as sizing. The program lists Sony Semiconductor Solutions Europe and Sony AI; the later manuscript uses SonyAI affiliation labels. The October 15 arXiv upload supports this September research milestone and is not treated as a second Event or the first public presentation.
ADI posted Staff Systems Design Engineer R264626 for San Jose or Colorado Springs, spanning analog, digital, firmware and system architecture for mixed-signal ICs such as power management, sensor interfaces and data converters. The posting says its team uses agentic AI and LLM workflows for design, verification and process migration and requires willingness to adopt AI-assisted methods. AI-driven design exploration and automated verification are preferred experience. This records the team’s stated workflow and hiring requirements, without independently establishing deployment outcomes or AI-generated circuit architectures.
A Broadcom Senior Digital / Mixed-Signal IC Design or Verification Engineer posting for Data Center Enterprise Storage, indexed as posted September 8, 2026 under requisition R026970, describes a methodology leader and technical bridge across US and Asia design centers. Its verification scope includes UVM-based block- and system-level testbenches, functional and code coverage closure, SVA and UVM/OVM methodology, event-driven analog-boundary modeling, and AI-assisted workflows for testbench generation and debug. A separate Broadcom careers posting, R025692, describes a closely related DMS verification methodology-leader role with the same cross-site and AI-assisted-automation themes; the postings do not establish that the two requisitions belong to the same team or define a company-wide standard.
Analog Devices CSS authors published an industrial case study of a synthesizable fixed-point SystemVerilog model for a Voice Coil Motor driver, derived from analog equations and deployed on FPGA for real-time emulation. The paper compares the implementation with an earlier automated real-number RTL generation flow using the SVREAL library, reports reduced FPGA resource use for the manual fixed-point implementation, and validates model fidelity against the reference analog behavioral model.
ams OSRAM posted a Bucharest ASIC Analog Mixed-Signal Verification Engineer role in its Light Sensors & Photonics business unit. The position defines verification strategies and plans, develops and validates analog and real-number behavioral models, integrates analog models into UVM mixed-signal testbenches, and executes top-level AMS verification with automatic checks. The qualifications name SystemVerilog RNM, Verilog-AMS, analog checkers, reusable verification components and scripting.
Infineon advertised an Andover Regional Graduate Program – Engineer Verification and Validation role for computing power-management products, with a retained September 3 listing. It assigns AI-based verification-flow improvement for coverage and documentation, alongside Verilog-AMS/SystemVerilog behavioral models, schematic correlation, targeted testbenches and analog/digital integration debug. The AI duty is an assigned methodology task; the posting does not say that AI generates those models. This is distinct from the later general AMS internship advertisements.
Infineon posted a Bengaluru Staff Engineer Design role whose description calls for developing RNM with SystemVerilog and svreal, building FPGA prototypes for SoC and system validation, and supporting pre- and post-silicon firmware validation and hardware/software debug. The role also covers simulation and FPGA automation, continuous integration, and modeling and prototyping methodology.
Synopsys posted a Hyderabad senior staff role to own AMS verification plans, environments, coverage, and sign-off for mixed-signal IP blocks and subsystems. Its description combines SystemVerilog/UVM with Verilog-A and Verilog-AMS models and mixed-signal simulators, and calls for behavioral models and monitors to be reused across IP families. Requested circuit knowledge includes bias circuits, regulators, PLLs, ADCs, and DACs. A September 28 posting repeats this IP-verification mandate and is grouped with the September 3 listing.
A University of Pittsburgh recruiting job posting dated September 3 advertises a Texas Instruments Design Verification Engineering internship. The employer description includes SystemVerilog coverage for voltages, currents and real values alongside digital coverage, constrained-random analog stimulus and automatic result checking. It also assigns RTL and gate-level simulations with SDF for timing between analog and digital circuits, regression scripting, verification planning and improvements to verification methods.
Arago posted a senior mixed-signal verification role in Paris or Tel Aviv to own methodology and verification of digital-to-analog interfaces in its SoCs. The responsibilities include block, subsystem, and SoC environments, behavioral and real-number models, assertions, coverage, and sign-off. SystemVerilog and UVM or an equivalent methodology are requested; SystemVerilog RNM, wreal, and Verilog-AMS appear among preferred experience.
TU Wien's repository made available Augusto Mafra and Haniel Barbosa's FMCAD paper on formal verification of SystemVerilog RNM by extending Yosys and Pono. The study uses 31 benchmarks: 17 public GPL-3.0 benchmarks and 14 built from proprietary Cadence models/testbenches. It compares real-arithmetic and IEEE floating-point SMT interpretations, whose semantics can produce different verification results. The v2.0.5 public implementation provides benchmarks, results and fixed revisions of Yosys, Pono and smt-switch. This is a research flow, not a claimed Jasper product feature; September 2 dates the paper's repository availability.
The DVCon India 2026 Day 2 agenda lists two AMS & Low Power Design presentations co-authored by Amit Singh: “Left-Shift Power Estimation in SoC Design: Verification-Integrated Framework for Early Power Estimation Using Digital Mixed-Signal Simulation” with Isha Sharma, and “Design-Focused Feedforward Behavioural Modeling of PLL IPs for Fast SoC Verification” with Preeti Shukla. Public profiles identify Sharma and Shukla with STMicroelectronics. This Event records the two public technical disclosures without asserting unexposed accuracy, runtime, or deployment results.
Enphase listed Staff and Sr. Staff processor-verification roles for a custom RISC-V VLIW processor used in energy-conversion control. The descriptions combine RTL simulation, SystemVerilog Real Number Modeling, analog simulation platforms such as NL5, C/C++ power-conversion and plant models, and Python automation in system-level mixed-signal verification, with validation of closed-loop behavior, deterministic timing, fault handling, and interactions between digital control algorithms and analog power stages.
Qualcomm Canada ULC listed a Cross-Functional Engineer, Staff role for high-speed SerDes work. The description assigns oversight of analog and mixed-signal behavioral-model development and verification, higher-abstraction analog verification, system verification with digital-verification and firmware teams, calibration, power modeling, and correlation of pre-silicon models and predicted power with post-silicon measurements. It asks for 106 Gbps-and-higher SerDes experience and SystemVerilog behavioral modeling, and names clock generation and distribution, VCOs, phase interpolators, PLLs, ADCs, and DACs among relevant circuit experience.
Astera Labs posted a principal SerDes/PHY verification role for PCIe Gen6/7, UCIe, UALink, and Ethernet interfaces. The description calls for UVM environments, RNM and behavioral-model collaboration with analog designers, CDR and training checks, and analog handoff validation. It also assigns methodology decisions across AMS co-simulation, gate-level simulation, and emulation, and prefers emulator familiarity and pre/post-silicon correlation experience. A related tech-lead listing checked on October 5 repeats this SerDes/PHY verification scope.
On August 30, 2026, MediaTek's careers site listed roles in dedicated AMS modeling and verification methodology groups responsible for modeling and verification platforms, coding and validation processes, experiments, deployment, UVM, assertions, coverage closure, and automation. A related modeling role calls for SystemVerilog RNM models of oscillators, voltage references and meters, LDOs, and temperature sensors, with model-versus-schematic verification, coverage, assertions, and Python.
Apple posted related CAD Automation and Mixed-Signal Simulation Engineer roles in Austin and Sunnyvale. The senior description assigns ownership of AMS simulation methodology across analog, RF, interconnect, PMIC, and memory teams, spanning circuit and RTL simulation, behavioral modeling, co-simulation, logic equivalence, sign-off, and automation. Preferred experience includes discipline resolution, binding/IE setup, connect modules, AMSD blocks, wreal, RNM, UDN, and SystemVerilog/Verilog-A/Verilog-AMS. Both roles mention applying LLMs or AI agents to CAD software, test generation, and debug among preferred qualifications, with leadership of that work requested in the senior role.
Qorvo posted a manager role to grow and direct a mixed-signal verification team for power-loss protection, PMIC, motor-control, and battery-management products. Its responsibilities include metric-driven plans, constrained-random tests and automated checkers in a UVM environment, RNM or Verilog-AMS models, methodology improvement, and verification automation; SV-UDN/EEnet and AI-workflow familiarity are preferred. A same-day senior principal listing describes the corresponding top-level UVM and RNM/Verilog-AMS work. These postings describe hiring mandates.
Cadence posted a Milan internship role that proposes investigating generative AI on industry cases, validating AI flows, and using Model in Minutes in the Virtuoso environment to build real-number models. This is an exploratory internship mandate and product-evaluation signal, not proof of a deployed customer methodology or validated productivity result.
Stefan Uhlich, Lorenzo Servadei and coauthors publish LLM-SPICEMixer, combining evolutionary circuit synthesis with an LLM operator that proposes new SPICE netlists from promising candidates. SPICE evaluation, rather than the language model, supplies the circuit reward. The task synthesizes transistor-level analog discriminant circuits. Author affiliations distinguish Sony AI in Switzerland, Sony Semiconductor Solutions in Japan and university collaborators. This is simulated topology-generation research, not fixed-topology sizing alone or evidence of production deployment.
Blue Origin advertised TeraWave AMS Design Verification Engineer R65544 to lead mixed-mode verification methodology. The role defines the co-simulation EDA environment with analog and digital teams, creates Verilog/SystemVerilog testbenches and analog/mixed-signal behavioral models, and develops block- and chip-level verification methods. An August 21 recruiting-board copy predates the current official Workday September 15 date. The earlier retained public posting dates this Event; the role establishes a hiring mandate for model and verification infrastructure, without an assigned AI-verification task.
onsemi posted a Principal AMS Verification Engineer role for new power-management products including DC-DC PMIC and point-of-load devices, multiphase controllers, DrMOS, AC-DC converters, LED and SiC drivers, switches, and eFuses. The role covers complete product verification ownership, behavioral-model requirements, SystemVerilog real, Verilog-AMS and Verilog-A models, configurable testbenches, checkers and coverage, and work in the methodology team to streamline AMS development and integration flows. This is a hiring mandate, not a claim that the methods are deployed across every product.
A Samsung careers posting in Bengaluru seeks an AMS verification engineer to create behavioral real-number models for converters and LDOs and work on PMIC verification using UVM, assertions, and automation. This is evidence of a public hiring mandate and its requested scope, not proof that every listed technique was already deployed on a shipped design.
Skyworks listed a Cedar Rapids AI/software-workflow co-op on August 20 and a central automation role on August 24 for an agentic AMS design/verification platform. The latter assigns encoding analog/RF practice into tool-connected flows and engineering distributed simulation/verification data; Verilog-A/SV-RNM model creation and validation are desired experience. September 24 Irvine co-op 78496 assigns agent tool use, retrieval and evaluation against real testbenches, logs, waveforms and coverage to support mixed-signal debug and closure. These platform-development advertisements do not establish deployment or a shared team across roles.
Renesas posted related Senior Principal roles for Automotive PMIC verification, covering RNM/AMS model integration, RTL-to-GLS correlation, PVT analysis, switched-mode regulators/LDOs, cross-team handoffs and methodology leadership. The Chandler role also assigns evaluation of emerging verification technologies and AI-based solutions. A related Staff description requires PMIC RNM/AMS environment architecture and Verilog/SystemVerilog proficiency. These grouped requirements include exploratory AI evaluation, not proof of AI-generated models, deployed tools or measured benefits; the original August 19 Event date is retained.
AMD posted a Rochester ASIC Design Verification Engineer role to own verification strategy and coverage closure for mixed-signal power-management IP. Responsibilities include full-SoC SystemVerilog/UVM tests, firmware/RTL co-simulation, analog-macro RNM bring-up and correlation with analog behavior, and relating post-silicon behavior to pre-silicon tests. Preferred experience names wreal, nettype real, and Verilog-AMS.
On August 14, 2026, NVIDIA posted a role to develop behavioral models and verification environments for custom mixed-signal cells used across NVIDIA products. The listing names Verilog, SystemVerilog, Perl, and Python, and covers cells including PLLs and high-speed interconnects, emulation and prototyping, and library- and chip-level integration.
Siemens published a technical overview of Symphony Pro's Mixed-Signal Visualizer for AMS verification. It describes linked hierarchy, netlist, source, and variable views; generated schematics for checking connectivity and port mapping; and paired analog/digital signal representations for inspecting A2D/D2A conversion and boundary elements.
SNUG Taiwan 2026 proceedings list a Credo presentation by Yenlin Lee and Sung En Wang titled “Time-effective Mixed-Signal PLL Verifications with RTVS Cosim and CTLE BER Analysis with Matlab for TSMC 2nm Design.” Synopsys names it a Best Presentation Award winner. The public record establishes the stated mixed-signal PLL/co-simulation and MATLAB CTLE BER-analysis scope for a TSMC 2 nm design; it does not expose the gated presentation’s measured runtime, correlation, or sign-off results.
ADI posted Wilmington Advanced Data-converter Group role R263851 on August 4 for analog circuit/system models, mixed-signal SoC connectivity/functional verification and usage-scenario testbenches, requesting SystemVerilog RNM, Verilog-AMS or SystemC. Related Austin/Durham Senior AMS Design Verification role R266818, dated October 13, assigns reusable SystemVerilog/UVM/RNM architecture, behavioral-model validation and fidelity/performance tradeoffs, requirements-traceable coverage, calibration/power-mode checks and regression/triage infrastructure. The later role is grouped with this existing AMS model-verification hiring milestone; a shared team is not established. Neither description assigns AI/ML modeling.
Ayar Labs listed related Bengaluru analog/mixed-signal modeling and verification roles. Their descriptions call for capturing significant first- and second-order circuit effects in SystemVerilog RNM, comparing models with schematics, signing off models, and integrating them into full-chip digital verification. The senior staff role adds model ownership through the product lifecycle. The postings name UVM and Verilog-AMS and include wreal/EEnet and optical simulation tools among preferred experience.
At DAC 2026, Analog Port and Siemens EDA authors described a top-down mixed-signal verification methodology for a 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface. The flow extends a UVM-based digital verification environment into the mixed-signal domain, using SPICE simulation for critical analog blocks and high-performance digital simulation for the broader system. The authors report up to 26x memory savings and more than 3x performance gain for the presented RX and TX simulations; these are case-specific presentation results.
A DAC 2026 abstract by EKEPOWER's Irving Hsu and Siemens' Lih-Jen Hou describes a Solido flow combining transient, RF, and mixed-signal analysis for printing ICs with motor/printhead drivers, timing references, and RF sensors. The authors report up to 7.6x speed improvement over their conventional methods and an AI-assisted trimming flow that reduces top-level voltage variation; these are presentation-reported results.
A Microchip and Siemens DAC 2026 presentation reports a digital-on-top mixed-signal flow combining selected SPICE blocks with RTL and UPF power intent. The presentation describes AI-accelerated Solido analysis and reports more than 22× acceleration for the presented case. This preserves the customer/vendor presentation modality and does not imply the result applies to every Microchip design.
At DAC 2026, Microchip and Siemens authors described full-chip analog mixed-signal verification of FPGA I/O PVT calibration spanning distributed I/O banks. The presented calibration combines a SAR-based digital block with analog circuitry that manages reference currents and voltages. The authors report that Siemens Symphony Pro reduced simulation time by about 3x and memory usage by about 2-3x while supporting regression across multiple I/O standards and extreme PVT conditions; these are presentation-reported results for the described case.
The DAC 2026 program lists ANA-MODELGEN by Aadhar Sharma and Texas Instruments coauthors. Its abstract describes automated generation of analog IP behavioral models and validation testbenches, with equivalence checks against SPICE references. The authors report use in production SoC verification flows and improvements in execution speed and functional coverage. This records the presented method and author-reported application; the public abstract does not establish use of an LLM or disclose independently verified results. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.
Maieutic's company account announces Rakesh Kumar's DAC 2026 presentation, GenAI Powered Circuits: Beyond Parametric Tuning, in a Silicon Integration Initiative session. The company's public materials position its analog-design work around generative circuit design rather than parameter adjustment alone. The date is the explicitly advertised July 27 session, not the relative age of the LinkedIn post. This records the named presentation and advertised scope, not independently verified design results or a customer deployment.
An NVIDIA Senior ASIC Design Verification Engineer posting for its Circuit Solutions Group describes custom IP spanning clocking, voltage regulation, and silicon correlation. It asks the role to help develop and deploy agentic-AI frameworks for stimulus generation, regression triage, debug, and root-cause analysis, while listing real-number modeling of low-level digital or mixed-signal designs and VCS-XA co-simulation as differentiating experience. This is evidence of a public hiring mandate, not proof of the capability or measured effect of a completed framework.
A Texas Instruments DAC 2026 presentation reports a UVM-MS-based flow in which verification components drive and monitor analog signals without traditional connect modules. The authors describe reusable analog VIP and report improvements in simulation runtime and verification coverage for the presented use cases. The record supports this reported TI application, not universal adoption across the company. In an August 25 public post, Aadhar Sharma confirmed presenting this work at DAC and described plans to apply the conference takeaways to ongoing TI workflows; the post does not quantify additional deployment results.
IBM Research lists HRL-Topo by Prashanth Vijayaraghavan, Xin Zhang and coauthors as a DAC 2026 publication dated July 26. The work combines language-model circuit guidance with hierarchical reinforcement learning to construct analog circuit topologies and evaluate them through simulation. This records a topology-synthesis research publication, rather than fixed-topology sizing alone or deployment across IBM design teams. The date is IBM's publication-record date, not a separately verified presentation time.
Bosch Sensortec posted a Dresden PhD role to develop agentic-AI software for accelerating ASIC design, verification, and test. The posting explicitly includes mixed-signal verification and testing and names coverage-driven regression optimization, AMS testbench generation, and closed-loop test-case evaluation and optimization among its example use cases.
CadenceLIVE Japan lists a presentation by 田所 晴子 of Cadence Japan on ViraStack, a natural-language-operated AI agent for analog and custom design in Virtuoso. Its advertised scope spans circuit design, layout and verification rather than layout automation alone. The speaker biography identifies application-engineering work on Virtuoso ADE and Spectre since 2005. This records the scheduled technical presentation and public abstract, not customer adoption, measured productivity gains or responsibility for developing the product.
Apple listed Wireless Silicon Digital Mixed-Signal Modeling Engineer roles in the San Francisco Bay Area and Beaverton on July 16. Related October 16 role 200689643 assigns accurate, simulation-efficient SystemVerilog models for analog/RF blocks, reusable monitors/checkers, test-plan execution, debug and flow automation. It explicitly develops emulation-ready models and requests understanding of synthesis-ready mixed-signal model requirements, with SystemC/C++ and high-level synthesis among preferred skills. These related postings are grouped with the existing wireless modeling mandate; the later role does not establish successful emulator execution or change the July Event date.
Guanglei Zhou, Xin Zhang and coauthors publish EXPLORE, combining an autoregressive circuit language model with Monte Carlo tree search and simulation feedback to explore analog circuit topologies. The manuscript lists Duke University, MIT-IBM Watson AI Lab and IBM Research affiliations. It concerns generating circuit structure as well as optimizing candidate designs. July 15 is the initial arXiv publication date; later MLCAD presentation is supporting context for the same research, not evidence of production adoption.
Broadcom posted an Analog/Mixed Signal Verilog Modeling Design Engineer role for touch-controller, wireless-power, health-sensing, and satellite analog front ends. The description calls for SystemVerilog DMS models, UDT/UDR nettypes including wreal or EEnet, model-versus-schematic verification, and experience using Cursor or chipAgents to generate analog SystemVerilog models and testbenches.
Semtech posted Digital Design Verification Trainee REQ3462 in Aguascalientes for the Signal Integrity Product Business Unit’s Digital Design group, which develops mixed-signal ICs for data communications and video broadcast. The description allocates 50% of responsibilities to constrained-random digital verification, 10% to analog behavioral modeling and analog/digital mixed-level simulation, and 10% to verification-methodology improvement. SystemVerilog is preferred in the qualifications. This is a training and hiring mandate, not evidence of completed deployment or a specified RNM implementation.
Skyworks posted a Director, Central AMS Verification role to found and lead a central AMS SoC verification team. The mandate includes an enterprise-wide UVM/RNM/AMS platform, common model and verification-IP libraries, coverage, assertions, convergence, and automation. Prabal K. Bhattacharya's public profile identifies him as leading global EDA at Skyworks, and his public post says he is hiring for this role to raise AMS verification across the company. These records establish the leadership connection and hiring mandate, not that the team is staffed or the platform deployed.
A SMACD 2026 keynote by an Infineon principal engineer describes industrial experience connecting AI assistants, retrieval-augmented knowledge systems, and EDA tools through APIs, along with a current focus on an AI-based verification methodology. Its concrete example generates SystemVerilog real-number models from schematics, specifications, or other source models while emphasizing domain knowledge, guardrails, compliance, and human review. This Event records the scope described by the keynote, not a measured deployment result.
Micron advertised HBM Staff Design Verification Engineer/Architect role JR94769 in Richardson. It assigns GenAI verification-methodology development aligned with HBM design cycles and AI-assisted root-cause analysis of pre-silicon as well as post-silicon issues. The role accepts digital, FastSPICE analog or mixed-signal co-simulation/real-number-modeling experience and spans IP/SoC verification architecture. Its scope is broader than dedicated AMS verification; it does not assign every GenAI task to RNM. A retained July listing predates the current September Workday date.
AMD posted a role for a silicon design engineer that describes leading verification of complex PLLs across RTL, gate-level, and analog/mixed-signal simulation, with UVM, coverage, co-simulation, planning, and technical leadership responsibilities. This is evidence of a public hiring mandate, not proof that every requested flow was already deployed across AMD.
Broadcom posted a Digital Mixed-Signal Lead role for the digital control infrastructure of PLL, FLL, and DLL clocking subsystems. The description assigns partnership with verification teams to drive mixed-signal-verification and real-number-modeling strategies for high-coverage loop simulations and also names full-chip CDC and RDC sign-off for the clocking network. This is evidence of a public hiring mandate, not proof that the listed verification strategies were already deployed across Broadcom.
Micron posted a Staff Engineer role for a high-speed DDR and ONFI PHY team whose description calls for reusable SystemVerilog/UVM environments with mixed-signal simulators and fast behavioral models using SystemVerilog EEnet or wreal, or Verilog-AMS, in place of SPICE subcircuits. It also covers full-chip gate-level, power-aware, and mixed-signal co-simulation plus model validation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
Texas Instruments posted an AMS verification engineer/lead role describing a high-voltage power team being built in Bengaluru for AC/DC controllers, isolated DC/DC converters, and GaN-integrated power stages. The role calls for SV-RNM and Verilog-AMS wreal/electrical models, system-level AMS tests, SystemVerilog/UVM testbenches, assertions and coverage, methodology development, and participation in post-silicon validation and debug.
In a June 17 public post, Srinivasan Venkataramanan reported that AsFigo's Ajeetha Kumari was deploying UVM-MS v1.0 on customer projects and had reviewed DVCon India papers from users of the standard. He shared a digest attributed to UVM-AMS working-group chair Evgeny Vlasov describing feedback from companies using v1.0 and proposals for driver/proxy/core communication while defining possible v2.0 scope. These are attributed reports of customer work and standards discussions, without named customers, independently verified adoption results or an issued v2.0 release. June 17 dates Venkataramanan's post, not the underlying meetings.
Renesas posted a Mixed Signal Verification Architect role to define scalable verification and validation for digital power products used in AI, datacenter, and high-performance computing applications. The mandate connects requirements, behavioral models, RTL, AMS simulation, emulation, bench validation, and silicon through measurable criteria, coverage expectations, correlation methods, automation, and reusable evidence.
Microchip posted a Technical Staff Engineer role for system-level AMS verification and power and signal integrity on SoCs and chiplet platforms. The description covers subsystem, full-chip, and cross-chiplet AMS and SPICE simulation, mature-node analog integrated with advanced-node digital, multi-voltage domains, methodology development, silicon bring-up, and simulation-to-silicon correlation.
ADI’s June 11 Staff Design Verification Engineer posting R263414 assigns AI/ML failure clustering, regression triage, anomaly detection and coverage optimization in mixed-signal/UVM verification. Related Shanghai role R262078, dated July 14, explicitly includes analog behavioral models and digital/analog interface checks, with Verilog-AMS/RNM familiarity. Graduate role R266482, dated September 22, assigns agentic AI to testbench development, debug and regression analysis with engineer review; Shanghai preferences include AMS co-simulation. These related hiring mandates are grouped without assuming a shared team or demonstrated production deployment.
An Arizona State University recruiting listing dated June 11 advertised an MPS Analog Mixed Signal Verification Intern role in San Jose for a 20–24 week Summer/Fall 2026 placement. The employer description assigns chip-top verification planning and AMS simulation for full-custom precision analog signal-chain ASICs, behavioral models ranging from RNM and logical models to Verilog-AMS electrical/wreal and schematic models, register and trim-mode debug with analog schematics and post-layout RTL, and regression and infrastructure support. June 11 is the university listing's recruitment date; the listed application deadline was June 19.
Celera announced its acquisition of SiliconGate, an analog design business with teams in Lisbon and Porto. The release describes prior collaboration in power-management design and plans to expand the Portuguese engineering team. Helen Song, identified as vice president of design, links the team and technology integration to expanding custom analog capacity and advancing AI-assisted product development. This records the completed acquisition and stated integration plans, not delivery of fully autonomous analog design.
Marvell posted a Senior Staff Engineer role in its Central Engineering AMS IP team with end-to-end verification ownership for SerDes and other AMS or mixed-signal IP across 5 nm, 3 nm, and 2 nm nodes. The mandate covers calibration, link training, power modes, analog-digital and firmware interactions, coverage, regression, sign-off, and reusable automation using SystemVerilog and UVM. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
Siemens published a Ubitium case-study abstract describing real-number models of analog blocks integrated into Veloce Strato hardware emulation. Its PLL example operates in a RISC-V system environment, and the abstract reports acceleration while retaining correlation with traditional simulation.
Skyworks posted related AMS verification roles whose descriptions cover Verilog-A and SystemVerilog RNM behavioral models, model-versus-schematic equivalence, AMS and DMS verification, and block-to-full-chip RFIC work. The roles name PLLs, ADCs, DACs, LDOs, oscillators, power-aware verification, and flow automation, while emphasizing scalable, reusable, and portable environments.
A Synopsys careers posting seeks a senior verification manager to lead and grow distributed SERDES PHY mixed-signal verification work spanning UVM, co-simulation, emulation, and laboratory correlation. It also asks the manager to drive AI-assisted regression triage where measurable. This is evidence of a public leadership and hiring mandate, not proof that all listed methods or AI-assisted triage were already deployed.
A ChipAgents-authored technical post describes an agentic workflow for PLL, ADC, DAC, and LDO behavioral models: create reference data with a full-physics simulator, generate Verilog-A models, validate waveforms and operating behavior against golden simulation data using the same or reserved stimulus sets, detect gaps, select new simulations through active learning, retrain, and integrate models through Verilog-A, SystemVerilog, or C++ DPI interfaces. The post says the company's platform produces tests, comparison results, and plots for human review. This records the company's own platform description, not independent evidence of model accuracy or customer deployment.
Davide Turossi reported defending his doctoral thesis at the University of Milano-Bicocca on June 4, 2026 and explicitly thanked Infineon for hosting and supporting the research. The university abstract describes a SystemC-AMS/COSIDE framework modeling automatic test equipment, devices under test and probe-card circuitry. Its gate-driver cases address over-current protection and output peak-current measurement, comparing virtual test solutions with measurements on manufactured hardware. This records the thesis and acknowledged research support, not company-wide adoption.
Marvell posted Analog Modeling & Testing Engineer Intern 2602068 for its Central Engineering team at the Córdoba design center. The training mandate includes modeling analog circuits in SystemVerilog, comparing SV and SPICE simulations, running digital/analog co-simulation and improving analog-IC design flows, alongside Python/firmware-based circuit testing. These are advertised assignments rather than a report of completed work. The named Córdoba modeling program is distinct from the Singapore amplifier-verification internship.
Texas Instruments posted Bengaluru role 25010677, Analog Circuit Design Engineer – AI/ML methodology. It assigns analog IC definition, modeling and schematic design, plus use of AI/ML-enabled tools and flows to accelerate development and create novel circuits. The engineer is also to drive adoption of those methods across product teams. Example circuit experience includes references, ADCs/DACs, amplifiers, oscillators and power-management blocks. This is a hiring mandate beyond device sizing alone; it does not demonstrate autonomous topology generation or measured design improvements.
onsemi posted a Mixed-Signal Verification Engineer role for analog IP integrated into digital-on-top SoCs on its 65 nm Treo BCD platform. The position owns SystemVerilog and UVM testbenches, real-number and Verilog-A/AMS behavioral models for PLLs, LDOs, DC-DC converters, and oscillators, executable plans, assertions, coverage and checkers, regression debug, and model-validation strategies. This is evidence of a public hiring mandate, not proof of completed verification outcomes. A Spring 2027 internship listing dated September 29 describes possible assignments in Treo digital-on-top verification, assertions, coverage, behavioral models and exploration of AI-assisted design.
Apple listed Mixed-Signal Verification Engineer roles for RF and mixed-signal blocks and interfaces in wireless SoCs. The descriptions assign verification planning, mixed-signal and digital UVM testbenches, reusable monitors and checkers, coverage closure, automation, and methodology improvement using AI; real-numbered SystemVerilog behavioral-model experience appears as a preferred qualification.
At User2User Europe 2026, HMT Microelectronic's Vincent Camus presented a requirement-driven mixed-signal ASIC verification workflow. The public session description connects Siemens Polarion requirements to VIP-based SystemVerilog testbenches, SVA assertions and chip-level mixed-signal validation. It describes automated pass/fail reporting and centralized model hierarchy, simulation configuration and version management. Simulator independence and functional-safety compliance are claims in the presentation description; no third-party certification or quantified verification result was established.
A Cadence official blog introduces Verilog-A teaching material for circuit and functional blocks, including ADCs, DACs, operational transconductance amplifiers, phase detectors and signal sources. It discusses Laplace- and Z-transform modeling for transfer functions. The Event dates the blog introduction, not the initial publication of every linked video, and is limited to circuit-block modeling rather than the device examples also mentioned in the article.
Cirrus Logic's company account advertised a Fall 2026 Mixed Signal Modeling & Verification Engineer co-op in Austin on May 2. The preserved job description assigns top-down SystemVerilog model development and validation, AMS/UVM verification planning for audio-processing ASICs, behavioral models using SV-RNM, SystemVerilog user-defined types and Verilog-AMS, schematic abstraction, and regression and flow support. The advertised student placement lasts 12–14 weeks. The Event date is the employer's public announcement, not the Fall work term or an inferred first posting date.
An Infineon Automotive Power paper at ETS 2026 describes retargeting IJTAG/IEEE P1687.2 test-case descriptions through a renderer and a pin-level time-stamp/value transport such as STIL into top-level SystemVerilog UVM testbenches for pre-silicon functional verification of automotive smart-power devices. Its SoC DUT combines digital RTL with analog behavioral models, while UVM-compatible agents apply external analog and supply stimuli. The paper illustrates replay of a measured noisy supply waveform and shows a charge-pump voltage (VDD CP) response to supply interruptions followed by an SPI diagnostic readout. These are paper-reported verification results, not measured silicon performance or evidence of wider adoption.
Apple posted PMU Digital Mixed Signal Modeling role 200659736, assigning SystemVerilog RNM, model-versus-schematic simulation, standalone validation, full-chip integration, reusable libraries, model accuracy metrics, regression and Python automation. The description states typical RNM closed-loop simulations exceed schematic speed by 100 times. Preferred experience includes LLM/AI-assisted coding for model or RTL development. This is a qualification signal, not an assigned AI model-generation workflow or independently verified speedup.
At SystemC Evolution Fika, Alexandra Küster of Bosch Sensortec presented an evaluation of solver efficiency in heterogeneous SystemC-AMS virtual prototypes. The slides compare PRECALC and SEGMENT approaches, adaptive time steps, feedback and discrete-event handling using MEMS and capacitance-to-voltage (C2V) models under repeated-shock conditions. This Event records the 2026 presentation, rather than the first publication of the underlying solver research.
Martin Barnasconi, identified with NXP and as Accellera SystemC Technical Committee chair, presented the SystemC-AMS standardization status at SystemC Evolution Fika. The slides report preparation for the next IEEE 1666.1 revision and work toward a public regression-test repository. Accellera coordinates this standardization work; it is not an NXP product release. The presentation does not announce a newly issued standard or the first public regression suite: a 2023 presentation already links a regression-test tar archive.
Apple posted a PMU Analog & Mixed-Signal Design Verification role for Cupertino and Austin covering full-chip mixed-signal verification, analog/RTL co-simulation, verification planning, assertions, coverage, and sign-off. Selcuk Talay publicly shared the role and described it as hiring for "my AMS design verification team," directly connecting him to the recruiting team.
Renesas listed PMIC verification roles for battery chargers, switching regulators and analog power IP. The descriptions cover chip-level AMS and full-chip DMS, SystemVerilog RNM and Verilog-AMS models integrated with RTL and UVM, model correlation to specifications and schematics, coverage closure, sign-off and silicon bench correlation. A later Kodaira staff listing assigns reusable UVM environments, assertions, checkers and coverage, and requests RNM/Verilog-AMS modeling experience for bias networks, regulators, bandgaps, amplifiers, comparators, converters and other mixed-signal blocks. Its requisition carries August 27, while its page's JobPosting datePosted is September 17; it does not establish an August public-posting date.
Apple posted an Analog Mixed-Signal Modeling Software Engineer role whose description covers multi-simulator platforms, scientific-software and automation frameworks, custom model libraries, simulation frameworks, domain-specific languages, and web interfaces for AMS circuit design.
A TechWorks presentation by Cirrus Logic engineer Gautham Sathyan describes a top-down mixed-signal verification approach spanning early architectural modeling, analog/digital boundary definition, DMS bring-up, SystemVerilog real-number models for lower-level analog cells, and chip-level AMS simulation. His public event biography identifies him with Cirrus Logic's Newbury Mixed-Signal Modeling and Verification group.
The DESN program lists Konstantinos Glaros, also introduced as Kostas Glaros, as EnSilica associate director of analogue IC design. His talk addresses AMS and DMS verification where multiple analog channels operate alongside complex digital signal processing, and traceable requirements compliance in industrial and automotive ASICs. This records a named technical presentation and its published scope; the public abstract does not identify a specific modeling language or quantified verification result.
ams OSRAM posted a Senior Principal Mixed-Signal Verification Engineer role to lead a distributed verification team and own an AMS/DMS methodology roadmap. The mandate covers reusable EEnet/UDN model libraries, DMS-to-Spectre correlation, SystemVerilog/UVM-MS environments, assertions, coverage, regression, sign-off criteria, and Python automation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed across the organization.
Synopsys announced the Ansys 2026 R1 release with a photonic circuit-design flow connecting OptoCompiler and Lumerical. The release notes describe CML Compiler generating photonic Verilog-A models for PrimeSim HSPICE/SPICE from component data including scattering parameters produced by FDTD, MODE and Multiphysics, enabling electro-optical circuit simulation in OptoCompiler. This records the announced circuit-model flow, rather than a device compact model or a later patch release.
A Micron careers posting for an AMS verification role describes full-chip analog, digital, and firmware interaction, behavioral models, power-cycle verification, and use of AI-assisted coding to automate design and analysis work. This is evidence of the capabilities requested in a public hiring mandate, not proof that a specific AI-assisted flow was already deployed or measured.
A Cadence DVCon U.S. 2026 paper applies metamorphic testing to a SystemVerilog real-number model of a receiver baseband, ADC, and automatic-gain-control system where a detailed test oracle is impractical. It defines relations for doubled or halved input, constant ADC magnitude, and plus-or-minus 6 dB RSSI changes and exercises them with randomized stimuli. This is a reported case study, not an AI method or a company-wide deployment claim.
A Siemens EDA customer story reports that AnalogPort applied UVM to a 32 Gbps full-duplex die-to-die interface with 16 transmitters and 16 receivers. The story describes using Symphony Pro with Questa digital simulation and Solido SPICE simulation, automated boundary insertion, selective data recording, and MS Visualizer; this is a vendor-published customer report.
Eliyan posted verification roles that pair organization-level AMS methodology with hands-on SerDes model ownership. The director role covers RNM, SV-AMS co-simulation, behavioral-model integration, UCIe and Ethernet PHYs, PLLs, CDRs, and SerDes analog front ends; the staff role develops SystemVerilog RNM directly from schematics and verifies those models with UVM tests and assertions. These are public hiring mandates, not evidence that every flow was already deployed.
STMicroelectronics posted a Master Thesis / Working Student Mixed-Signal Modelling and Design Verification role in Munich. The Power Management IC Design Verification Team assigns IC top-level verification, verification-flow development and analog behavioral models, with IEEE/Accellera standards and EDA reference flows. The qualifications include Verilog/SystemVerilog, Python, analog circuits and Cadence flows, with Virtuoso SKILL as a plus. The official JobPosting metadata identifies February 16 as datePosted for job 10540; the role does not identify a particular RNM implementation or a completed automation result.
A Renesas requisition dated February 9 advertised a Summer 2026 Design Verification Intern role in Morrisville for DDR5 IC development. The student works with analog and digital designers on simulation verification and silicon debugging, develops infrastructure using Verilog, SystemVerilog, UVM, Python and Perl, and maintains verification environments and self-testing testbenches. The advertised work period was May 26 through August 14; this Event uses the date embedded in official requisition 20025372 rather than the internship start date. The official page now marks the vacancy expired.
A Discover Technata recruiting listing dated February 7 advertised an NXP Analog Mixed-Signal Design Co-Op for early-career engineers. The role supports analog/digital integration, schematic and netlist views, connectivity checks, Verilog-AMS and wreal view generation, simple RTL wrappers and digital-on-top build checks. It also assigns block- and top-level Spectre/Xcelium/AMS Designer simulations, testbench and model packaging work, and automated lab measurements including power-up sequences. The listing is no longer accepting applications; its date is the recruiting board's posting date.
Jim Caravella posted a public invitation to join the first phase of a new MCU team using analog/mixed-signal IP, sharing NXP’s Catania MCX recruitment. A related Junior Mixed-Signal Verification Engineer posting assigns SystemVerilog RNM and Verilog-AMS analog models, verification coverage, robustness, test modes and DFT in new full-product teams. An October 2 Catania internship separately names an AMS Verification Team and proposes behavioral models, assertions, debug and coverage; its direct membership in the MCX team is not established. These sources record team-building and hiring, not completed technology deployment or NXP’s first presence in Catania.
An Apple careers posting for an experienced AMS design-verification engineer says the role will help build a new team in London. It lists SystemVerilog and UVM verification, performance and power analysis, early power estimation, and research and innovation; AI and machine-learning experience appears as a desired qualification. This is evidence of a public hiring mandate, not proof that AI/ML or every requested method was already deployed.
The US12524593B2 grant publication names Charles McClish as inventor and Microchip Technology as assignee. It describes Analog Information Model (AIM) SystemVerilog classes carrying analog properties such as voltage, current and resistance, with connected model instances exchanging and resolving information. This Event dates the grant publication, separate from the earlier AIM paper; it does not establish that AIM was first invented or newly deployed in 2026.
An Indeed-hosted copy of an AMD Fellow-level pre-silicon verification posting describes a mixed-signal IP organization and asks the role to integrate UVM with real-number modeling and AMS co-simulation, modernize regression, debug, and coverage analytics, and define an AI-assisted strategy spanning intelligent test generation, regression triage, and coverage-gap prediction. This is evidence of a public hiring mandate, not proof that these methods were already deployed across AMD.
Synopsys AMS SIG India 2026 lists a Broadcom user presentation by Jeevan Ramaswamy titled “High-Capacity Macro Verification: A Unified AMS-SDF Approach using VCS PrimeSim AMS.” The public agenda and proceedings establish a Broadcom-authored macro-verification flow combining AMS and SDF in VCS PrimeSim AMS. Because the presentation deck is gated, this Event does not assert implementation details, capacity results, speedup, or deployment scope beyond the published title.
A Google careers posting for a senior verification engineer in Israel lists ownership of verification for 112G and 224G high-speed PHY signal-processing designs. The role calls for RNM or SystemVerilog-AMS flows across analog-front-end and digital-DSP boundaries, with specialized testbenches for adaptive algorithms such as LMS and Zero-Forcing covering stability, convergence time, and tracking across process-voltage-temperature corners. It also calls for link bring-up, auto-negotiation and error-recovery tests and for channel loss, crosstalk, and reflections to be represented in the DV environment. This is evidence of a public hiring requirement, not proof of a deployed internal methodology.
An Intel AMS Verification Engineer posting describes SystemVerilog behavioral models for SerDes, PMU, and DC-DC circuits, integration with digital functional verification, AMS comparison to the models, and full-chip power-up simulation. It also asks for generative-AI code generation, AI-driven debugging, automated documentation, and AI-based workflows for model development, simulation analysis, and reporting. This is evidence of a public hiring mandate, not proof that every listed AI-assisted method was already deployed or measured.
Intel posted a Senior Pre-Silicon Verification Engineer role describing functional verification of PLL and FLL clock-generator IP, SystemVerilog/UVM environments, tests, assertions and coverage, and leadership of mixed-signal validation using AMS simulations to identify and root-cause schematic bugs. This is evidence of a public hiring mandate for clock-IP verification, not proof of the completion or deployment of a particular verification flow.
Microchip’s Senior Engineer I – Verification posting R1497-26 describes full-chip SoC/mixed-signal verification with SystemVerilog/UVM, analog-IP interactions and coverage closure, plus LLM-assisted code/stimulus generation, root-cause analysis, log/waveform triage and failure clustering. A November 4 Senior Engineer II role R4346-26 names the Chennai WIPD group and adds Verilog-A/AMS and SV-RNM models, SPICE and applicable silicon correlation for ADCs/DACs, PLLs, LDOs, bandgaps and clocking circuits, alongside AI-assisted verification, modeling and debug methodology. The related mandates are grouped without assuming a shared team or completed AI deployment; the later posting does not change this Event’s original year-only date.
Monolithic Power Systems lists a Mixed-Signal Design & Verification Engineer Lead role to define and lead framework and infrastructure development for complex digital and mixed-signal ICs. The position covers behavioral modeling, analog and mixed-signal IP integration and verification, mixed-mode simulation, analog-digital interface definition, and post-silicon validation across power, sensing, motor-control, display, and audio products. This is evidence of a current hiring mandate, not proof of completed deployment.
Neurophos posted a Lead Verification Engineer role for its silicon-photonic AI platform. The position owns SoC verification strategy, UVM and constrained-random environments, SystemC model integration, regression automation, FPGA acceleration, gate-level sign-off, and development and verification of AMS and SystemVerilog models for in-house analog designs; AMS verification and RNM experience are also named as preferred skills. This is evidence of a hiring mandate, not proof of completed silicon or methodology deployment.
An NXP Careers posting for a Senior AMS Verification leader in Milan describes ownership of verification strategies, plans, environments, regressions, coverage, behavioural models, checkers, assertions, and reusable components for the Advanced Power System team, including top-level mixed-signal verification and methodology improvement. The requested experience includes Verilog, SystemVerilog, UVM, SVA, Verilog-AMS, SystemC, WREAL/RNM, and mixed-signal EDA tools. This is evidence of a public hiring mandate, not proof that every listed method is already deployed. A related Chandler PMIC leadership listing checked on October 5 adds explicit power-sequencing and fault-management checks using reusable AMS/UVM/RNM environments.
NXP posted a Principal AMS Verification Engineer role to own SerDes verification from concept through sign-off. The description covers UVM and UVM-AMS environments, RNM and Verilog-AMS model development and validation, PLL and CDR behavior, link training and adaptation, jitter and noise analysis, assertions and coverage, PVT and stress verification, and correlation among MATLAB or Python, behavioral models, and transistor-level simulation. This is evidence of a hiring mandate, not proof of project completion.
OLIX posted a Senior Mixed-Signal Verification Engineer role to own verification of high-speed I/O receive and transmit chains in its AI accelerator, including CDRs, phase interpolators, clock generation, equalization, samplers, slicers, deserializers, and digital control loops. The role defines fidelity tiers across RNM, Verilog-AMS, and transistor co-simulation, owns self-checking testbenches, coverage and sign-off, builds regression automation, and correlates models with silicon. This is evidence of a public hiring mandate, not proof of completed deployment.
Semtech posted related senior verification roles in San Diego and Hyderabad covering verification plans for mixed-signal IP, subsystems, and full ICs; SystemVerilog and UVM testbenches; RTL, gate-level, and AMS simulation; constrained-random stimulus; assertions, functional and code coverage; continuous integration and regression automation; and desired SV-RNM or Verilog behavioral modeling. The San Diego role is tied to low-power sensing ICs with ADCs. These postings evidence a hiring mandate, not completed deployment.
Cirrus Logic posted a Mixed Signal Modelling and Verification Engineer role to lead verification activities and help evolve company methodology for complex mixed-signal ICs. The position covers verification strategy, reusable testbenches, real-number modeling, SystemVerilog user-defined types and Verilog-AMS, hands-on modeling and simulation, and desired experience in UVM, assertions, functional and code coverage, and CPF or UPF power-aware verification. This is evidence of a hiring mandate, not proof that every listed practice is deployed in every project.
Carna Zivkovic presents a SystemC/SystemC-AMS model of a UWB transmitter, channel and receiver, comparing behavior with MATLAB and hardware measurements and examining how receiver gain/noise variations affect packet errors and sensitivity. The cover identifies her as an external contractor, not an NXP employee appointment. The slides credit Shrief Rizkalla as the main author of earlier work and Zivkovic as presenter. This Event records the December presentation and its statistical-model extension, not first publication of the underlying UWB research.
Alexandra Küster of Bosch Sensortec presents a COSIDE scripting flow for heterogeneous sensor virtual prototypes combining MEMS, analog, digital and firmware models. The slides contrast manual project copying and backporting with common templates, versioned building blocks, automated updates and a working top-level/testbench scaffold. Python copier, CMake and continuous integration support model reuse and maintenance. Automated test creation remains a next step. This is a reported modeling workflow, not an AI circuit-generation claim.
Guillermo Conde of Infineon presents SystemC-AMS/COSIDE models for smart gate drivers using coreless-transformer isolation. The flow combines discrete-event, timed-data-flow and electrical models with selectable RF baseband/passband abstractions. The integration example connects the RF isolation path to SPICE-level surrounding circuits for AMS verification. December 3 is the scheduled presentation date; November 27 on internal slide footers is not treated as the public presentation date. The slides describe a modeling approach, not company-wide deployment.
Souradip Poddar, Chia-Tung Ho and coauthors present HeaRT, an agentic AMS design framework that organizes circuit hierarchy, functional roles and feedback relationships to guide design changes. The work includes topology exploration as well as parameter refinement. The authors list NVIDIA, UT Austin and George Washington University affiliations. This records a research publication, not NVIDIA production deployment. The Event retains the November 24, 2025 initial-publication date; the March 26, 2026 revision is supporting evidence for the same research milestone.
Apple posted a Wireless Radio Verification Engineer role whose description covers radio digital controllers and Digital+RF subsystems spanning PLL, DAC and ADC data paths, power management, and coexistence. The hiring mandate includes UVM environments, constrained-random tests, coverage and assertions, and digital-plus-mixed-signal co-simulation integrating SystemVerilog behavioral and DMS models.
A Siemens forum recap reports two Microchip posters: mixed-signal code-coverage analysis of a temperature/voltage sensor exposed RTL bugs missed by standalone digital verification; a battery-backed SRAM case used Symphony Get Analog Value and checkpoint save/restore for analog visibility and debug. The date records publication of the vendor recap.
A Siemens EDA customer-story recap reports that TOPPAN presented a full-chip mixed-signal verification workflow for a complex CMOS image sensor integrating a microcontroller with analog blocks including LDO, PLL, and temperature sensors. Siemens reports that Symphony reduced TOPPAN's mixed-signal verification time by more than 50% without compromising accuracy; this is a vendor-published customer report.
Mythic posted a Senior Digital & Mixed-Signal Verification Engineer role responsible for making its analog flash-compute core accurately and thoroughly verifiable in digital and mixed-signal flows. The position spans RNM creation and verification, UVM, top-level algorithm verification, mixed-signal interfaces and specifications, and controller and FSM verification for data converters, PLLs, and power converters. This is evidence of a public hiring mandate, not proof of verification completion or product deployment.
Celera announced that Helen Song had joined as vice president of Product Design to lead customized analog product development. The announcement identifies her preceding role as general manager of MediaTek's Analog Design and Technology Product Group. Celera describes an AI-assisted analog development flow and a mandate to expand its engineering and reusable IP capabilities. October 28 is the announcement date, not a verified employment start date; the move does not establish transfer of MediaTek technology.
An ams OSRAM DVCon Europe 2025 paper reports using digital mixed-signal simulation for early full-chip power estimation. Analog-model states map to quiescent-current values inside a central UVM testbench spanning multiple rails and IP blocks. The authors present the method as an early-estimation aid alongside detailed verification, not as a replacement for analog sign-off.
Robert Bosch authors report a cross-level verification flow that applies the same use-case scenarios across system specifications, virtual prototypes, RTL and mixed-signal design representations, and production software. The paper describes automated signal mapping and trace comparison and presents an automotive ASIC case study intended to expose inconsistencies among parallel representations and exercise mixed-signal hardware with real-field software scenarios.
NXP and RPTU authors presented variation-aware PLL performance evaluation at DVCon Europe 2025. Public slides integrate statistical performance kernels into SystemC-AMS charge-pump and loop-filter models, preserving 23 shared variations between the blocks. They evaluate PLL lock-time distributions across 2,000 runs and compare approaches with independently modeled block distributions. Related NXP work appeared in 2023; this event records the 2025 evaluation rather than the methodology's first introduction.
An NXP DVCon Europe 2025 paper reports a gyroscope verification flow using UVM-MS, custom user-defined nets for voltage, current, resistance, and capacitance, Python through DPI, and safety-mechanism checks. In one capacitor-model comparison, the paper reports 24 seconds for a custom enet implementation, 129 seconds for EEnet, and 256 seconds for Verilog-AMS. Those timings apply only to that example and simulator setup.
An STMicroelectronics DVCon Europe 2025 paper reports a voltage-aware SRAM verification flow using SystemVerilog real-valued supply modeling and UPF supply-net types for retention memory and bias-generator behavior. For the presented case, the paper contrasts roughly two to three hours of SPICE simulation with 10 to 12 seconds in the digital flow. It also states limitations including PVT representation and simulator-specific UPF behavior.
Apple posted an Aeon Modeling Intern role in Munich on October 1, 2025 for AMS interface models, circuit/measurement comparison, automation and LLM-assisted development. Related role 200690119, posted October 19, 2026, assigns Python/C++ models for SerDes, PLLs, memory interfaces and converters; ML surrogate models trained on circuit simulations and silicon measurements; LLM/agent workflows for specification-to-model generation, code translation, tests and documentation; and automated accuracy checks against SPICE and measurements. It also proposes GPU/parallel acceleration and model-order reduction, with documented accuracy bounds and engineer ownership of correctness. The later recruitment is grouped with the existing Aeon mandate, without changing its original date or asserting completed AI-modeling results.
A KIOXIA SNUG Japan presentation reports that flash-memory control uses many analog circuits and is repeatedly verified with SPICE simulation including AMS co-simulation. It describes applying PrimeSim HT and a VC Execution Manager utility in product development to reduce verification time and optimize simulation-job execution within limited computing resources.
Mariam Maurice, Rich Edelman, Mohamed Dessouky, and Ashraf Salem published an Integration paper applying constrained-random stimulus, functional coverage, assertions, and a UVM testbench to an analog PLL real-number model. The paper varies loop-filter parameters, charge-pump current, and VCO gain, and compares modeled outputs with a reference model. Its first-online date is September 12, 2025, although the journal volume is dated 2026; the reported DUT is an RNM model.
The official DVCon India 2025 agenda lists an Infineon presentation titled 'Scalable and cost-effective mixed signal modelling using AI with SV-RNM' by Sathyanarayana Ramamoorthy, Rutvikkumar Patel, Anand Rahul, Kranthi Kiran, and Hareesh Perumal. The public agenda establishes the presentation and its stated topic; without a retained paper, this Event does not assert a specific model-generation method, result, or deployment scope.
A DVCon Japan 2025 presentation by COSEDA Technologies authors describes a pure-C++ assertion library for SystemC AMS using templates and operator overloading to provide SVA-like expression of temporal properties, including support for timed-data-flow models. This records a presented library and its stated capabilities, not a semiconductor-customer deployment.
A 3.0 revision was publicly demonstrated in August 2025. The update extends motion and adds additional expression states during real-time operation, increasing the range of observable behavior while retaining the earlier interactive form.
Yashaswini Mudda publicly reported completing a two-month Analog Design Verification internship at Texas Instruments in Bangalore. Her account describes SystemVerilog verification and testbench-flow automation, UVM exposure, work involving RC/LC and glitch filters and analog multiplexers, and SV-RNM logic for handling multiple testbench drivers without contention. She names Balaji Ammineni as manager and Mrinav Saxena as mentor. This is a participant’s report of a completed placement, not an independently measured result or company-wide methodology claim; the date is the post’s publication, not a reconstructed internship start or end.
SiTime posted a verification role whose responsibilities included developing SystemVerilog real-number models, a digital-top SystemVerilog verification plan, UVM scoreboards, monitors, and sequencers, SVA, functional coverage, simulation debug, and tape-out sign-off. The listing named wreal/V-AMS, UVM-AMS, and formal property verification as relevant experience. A Munich listing checked in September 2026 repeats this responsibility and qualification pattern.
At Verification Futures UK 2025, Renesas engineer Steve Holloway presented a concrete example of creating a DAC verification component using the new UVM-MS methodology. The published session description identifies the verification-component architecture and code snippets as key content. This is a public UVM-MS implementation example from a Renesas engineer, not evidence of company-wide or product-wide deployment.
A Texas Instruments DAC 2025 presentation describes an Analog Assertion and Coverage Toolbox that checks range, frequency, ramp, and glitch behavior and identifies stimulus gaps across SPICE and behavioral-model verification. The record supports the presented checker and coverage workflow; it does not establish use on every TI program.
A Texas Instruments and Cadence DAC 2025 presentation reports an EEnet-based analog test-bus method for checking voltage, current, loading, and coupling behavior. The authors describe using the real-number abstraction to reduce reliance on AMS simulation for the presented verification tasks. This is a reported customer/vendor method, not a claim that EEnet replaces circuit-level verification.
Renesas posted a senior staff AMS verification role to support top-down design and full-custom ASIC verification. The position covers Verilog-AMS and SystemVerilog behavioral models, real-number modeling, self-checking mixed-signal simulation, verification planning and regressions, chip-level integration, and Python and Cadence SKILL automation for project and verification flows. This is evidence of a public hiring mandate, not proof that every listed method was deployed across Renesas.
Apple listed Mixed-Signal Model Verification Engineer roles whose description includes self-checking SystemVerilog testbenches that compare behavioral models with source circuits, functional checks against specifications, assertions, formal logical equivalence, lint and timing checks, and flow automation across mixed-signal design teams.
Elias Väänänen’s University of Oulu thesis reports work conducted at Robert Bosch Oy within Bosch Sensortec to improve discrete-time delta-sigma modulator design and mixed-signal verification. It develops SystemVerilog and Simulink behavioral models with nonlinearity and noise, selecting an impulse-invariant approach after comparison with EEnet modeling. The work reports simulation studies, but explicitly leaves transistor-level performance matching, including SNDR, and incremental reset operation untested. It therefore does not establish silicon correlation or sign-off accuracy. The date is the repository’s public-availability date, following its May 15 issue date.
U.S. patent application US20250117560A1, assigned to Texas Instruments, describes obtaining analog-simulation logs, training a neural network, deriving a mathematical transfer function, and producing a SystemVerilog-compatible simulation kernel for real-number modeling. This Event records a published patent disclosure; publication does not establish product implementation, internal deployment, or the scope of any deployed flow.
Silicon Labs posted a Staff or Senior Staff AMS Verification role whose description covers functional, performance, and power sign-off for next-generation IP and SoCs using RNM models. The role includes Verilog-D, Verilog-A or Verilog-AMS behavioral modeling, block- and chip-level verification, self-checking regressions, model validation, silicon correlation, and SystemVerilog/UVM experience. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
Paul Graykowski, identified as a Cadence product-marketing director, describes SystemVerilog real-number modeling of photonic components with PhotoNet and electrical circuits with EEnet in Xcelium. The sponsored technical article targets verification of multi-chip systems containing photonics, analog electronics and digital controllers, and references associated models and adoption examples. March 27 is the article publication date, not a verified initial library release date. It does not identify a customer deployment or establish that the author implemented the libraries.
Charles Dančak of Betasoft Consulting presents an AMS assertion method for the op-amp bias line of the LDO regulator studied in his earlier UVM testbench paper. XMODEL represents the analog signal as piecewise mathematical expressions; meas_max and meas_min compute extrema over measurement intervals, which SVA/PSL properties can check for spikes missed by point sampling. Assertion evaluation remains clocked and detection depends on the model and measurement setup. This is a presented verification technique, not a general guarantee for arbitrary physical waveforms.
A DVCon U.S. 2025 paper by Cirrus Logic and MathWorks authors describes generating SystemVerilog DPI-C components from system-level models for reuse in mixed-signal verification. A reported test ran in 30 seconds with DPI-C versus 51 seconds with a user-defined nettype and 54 seconds with Verilog-AMS. The paper also contrasts two projects whose closed-loop verification began 18 and 43 weeks after RTL availability; those project timings are not presented as a controlled comparison.
A DVCon U.S. 2025 paper by Ulkasemi and Designer's Guide Consulting authors reports an object-oriented UVM utility for mixed-signal verification that manages temperature, model parameters, fault injection, and reporting. The paper demonstrates PLL and temperature-sensor use cases and reports a roughly two-minute simulation for the presented setup. Although the paper discusses broader automation trends, it does not establish an AI-based implementation.
Samsung authors present a configurable analog front-end behavioral and channel model in a UVM testbench for 16.0-GT/s PCIe receiver digital logic. Randomizable offsets and FIR channel coefficients exercise eye monitoring, offset calibration, DFE adaptation and margin logic, including deliberately out-of-range conditions that expose retry and timeout bugs. For the reported regression, time to 100% digital code coverage falls from 54.26 to 16.13 hours. The conventional comparison uses an XMODEL analog behavioral model; this does not establish Scientific Analog coauthorship or collaboration. The authors retain conventional circuit-reflecting models for verification requiring actual AFE/channel behavior.
On February 4, 2025, Accellera released UVM-MS 1.0, defining mixed-signal bridge and proxy components for driving and monitoring mixed-signal nets. The standard's participant list names active contributors from Cadence, Intel, Siemens EDA, Synopsys, NXP, Qualcomm, and Renesas; participation in the standard does not by itself establish deployment at those companies.
At ASP-DAC 2025, Jaeha Kim, affiliated with Seoul National University and Scientific Analog, presents an invited paper on SystemVerilog/XMODEL simulation of silicon-photonic systems. The conference abstract describes mapping photonic elements to equivalent multi-port transmission lines and event-driven simulation of 5-Gb/s, three-channel WDM links using micro-ring, Mach-Zehnder and electro-absorption modulators. It reports 4.2, 8.3 and 8.3 simulated symbols per second for those examples. These are model-simulation results, not measured link throughput or demonstrated silicon correlation. January 21 is the scheduled presentation date; the publisher proceedings date is later.
A DVCon Europe 2025 paper by ams OSRAM authors describes collecting analog-IP functional coverage from the same UVM top-level testbench for real-number models and transistor-level schematics. A common real-valued reference and mixed-signal sampler supported both modes; the authors report that AMS runs exposed effects such as glitch filtering that the real-number model did not reproduce.
Apple posted a Mixed-Signal Behavioral Modeling Engineer role whose description includes SystemVerilog models that capture functional and non-ideal behavior, circuit-simulation and formal-equivalence checks, reusable modeling methodology, functional coverage, and automation for PLL/DLL, SerDes, sensor, and data-converter circuits.
An Infineon job record for its central design-flow department in Dresden describes developing and integrating methods and software extensions for analog and mixed-signal verification automation, including SPICE simulation, reliability, optimization, and regression tooling. The role also lists AI/ML knowledge as an advantage. This is evidence of a public hiring mandate, not proof that a specific automated or AI-assisted flow was already deployed.
An Infineon job record for a Senior Engineer Verification role lists Verilog, wreal, or SV-RNM behavioral modeling; AMS verification for SoCs or IPs; test planning and debug; and independent mixed-signal-verification project and methodology-improvement responsibilities. It also names Verilog-AMS, SystemVerilog/UVM, and Cadence, Synopsys, and Mentor AMS tools. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
A Sony Semiconductor Solutions SNUG Japan presentation describes applying PrimeSim Custom Fault to analog circuits in automotive image sensors, which the session abstract identifies as mixed-signal ICs. It reports deriving fault-detection rates from the fault-injection verification and feeding the results back into the design to improve the detection rate.
A Texas Instruments DVCon India 2024 paper reports a compact Verilog-AMS checker and assertion library for adaptive detection of kickback and frequency glitches across SPICE and behavioral-model verification. The paper describes automated checker insertion and execution-flow optimization. The word intelligent appears in the paper title, but the supported implementation is an adaptive checker flow rather than a demonstrated generative-AI system.
At DAC 2024, Samsung authors presented a digital mixed-signal verification approach that combines lower-level behavioral models with a SystemVerilog user-defined EEnet to represent electrical loading in power-management IC verification. The presentation describes extending the DMS verification checklist to performance and loading behaviors beyond voltage-only interfaces.
An initial real-time representation of Lunlun was publicly demonstrated in June 2024. The session exposes continuously observable motion, expression changes, and interactive response, providing a behavioral baseline for later revisions.
At Siemens User2User North America 2024, a customer-presented SiTime session described using Analog FastSPICE, Symphony, and Solido Design Environment to integrate analog and digital components and accelerate verification of high-precision MEMS-based oscillator SoCs.
A DVCon U.S. 2024 paper by InnoPhase and Designer's Guide Consulting authors reports a Python and Jinja flow that generates UVM testbench infrastructure from a DUT port list, including analog interfaces and agents plus register-abstraction integration. The paper presents deterministic template-based automation; it does not describe an AI-generated testbench flow.
At DVCon U.S. 2024, Meta Reality Labs' Sandeep Sharma presented a UVM-based AMS co-simulation methodology that dynamically switches between real-number and SPICE representations while reusing digital mixed-signal checks, assertions, and random stimulus. The paper reports a nightly flow in which one AMS/SPICE test verified seven ADC configurations over a week.
At DVCon U.S., Siemens EDA's Mariam Maurice presented methods for verifying ADC and DAC real-number models with randomized stimulus, functional coverage, assertions, and UVM. The paper includes constrained variation of reference and supply voltages and coverage of real-valued signal ranges. Its verification targets are modeled analog devices and their specified behavior.
A DVCon U.S. 2024 paper by Ulkasemi and Designer's Guide Consulting authors describes validating analog behavioral models against schematics and then integrating them into a full-chip UVM environment. The paper discusses complementary AMS and digital mixed-signal tradeoffs and presents the method as a reusable verification architecture, not as proof that behavioral abstraction replaces circuit-level verification.
Charles Dančak of Betasoft Consulting presents a UVM testbench for a programmable 45-nm CMOS LDO. MODELZEN extracts a SystemVerilog/XMODEL model from its Virtuoso schematic. Eight directed tests cover regulation, transients, operating modes and supply rejection; a randsequence alternates line and load transients while carrying circuit conditions between tests. A UVM event pool coordinates stimulus and measurements. One Xcelium run with seed 3947 reports four failing transient tests out of ten, including a 279-mV overshoot. These are modeled testbench results, not measured silicon or a universal coverage guarantee. This is the regulator-testbench work referenced by the later voltage-spike assertion paper.
Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.
Accellera formed the SystemVerilog Mixed-Signal Interface Types Working Group to define SystemVerilog-compatible interconnect, conversion and resolution among dissimilar net types, including bidirectional connections between logic or user-defined nets and analog, electrical or real signals. Accellera said work in the UVM-MS and SystemVerilog-AMS groups had exposed a fundamental need for this capability within IEEE 1800 and that earlier approaches outside IEEE 1800, such as Verilog-AMS connect modules, had not met the complexity and usability requirements of typical SoCs. Peter Grove was named co-chair of the new working group.
A public NVIDIA recruiting post by Yvonne Chen advertised a Taiwan Senior Mixed-Signal Design Engineer role in the high-speed I/O SerDes group. The role works with analog designers on SystemVerilog models of closed-loop PLLs, receive CTLEs, SAR ADCs and optical components, and with system architects and digital designers on architecture specifications and adaptation algorithms. The post also assigns reusable scripting and silicon bring-up work. It establishes a recruiting mandate, not deployed modeling results; the recruiter is not identified as a technical team lead.
AMD authors report a flow that reads a Standard Delay Format file, generates a SystemVerilog specify block for analog-boundary IOPATH delays, and instantiates it in an analog behavioral model for back-annotated mixed-signal gate simulation. In two reported IP cases with about 40 analog-interface signals, the automated approach reduced manual effort and annotated all paths; the paper also reports uncovering a constraint issue in one project after complete delay annotation.
A DVCon Europe 2024 paper by University College Cork and Analog Devices authors evaluates an experimental workflow that learns from analog simulation data and generates a SystemVerilog inference model. For an RC demonstration, the paper reports 16 seconds for analog simulation, 15 seconds for a non-AI SystemVerilog model, and 14 seconds for the AI model, and says the approach was evaluated at ADI with promising results. It does not establish production deployment.
A DVCon Europe paper by Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker describes svreal extensions that detect range violations and precision loss in simulation by comparing fixed-point calculations with a shadow SystemVerilog real representation. Its Integrated Fixedpoint Analyzer interprets fixed-point signal values during FPGA debug. A buck-converter model illustrates the flow between host simulation and FPGA emulation.
An NXP-authored paper reports reusing pre-silicon AMS functional tests in post-silicon validation with matching stimulus timing and side-by-side waveform visualization. The methodology uses Jupyter and Python around a reusable environment for product variants; the authors report deployment across multiple projects and products and one-day silicon bring-up.
A DVCon Europe 2024 paper by Samsung authors describes reusing a configurable digital mixed-signal UVM environment for a selected set of analog/mixed-signal tests coupled to a SPICE simulator. In the display-PMIC case, the authors report finding critical schematic issues before tapeout and correlating verification results with silicon measurements.
Samsung Foundry authors report a SystemVerilog embedded-MRAM behavior model that incorporates write-time and write-voltage variation into bit-cell test behavior. The reported simulations exercise random write time and voltage-dependent intended write failures, and the authors state that the variation-aware operation was verified with the Digital Nonvolatile-memory Assist IP used to control the MRAM for IP validation.
Two U.S. patent applications assigned to Texas Instruments disclose complementary machine-learning techniques for analog or hybrid analog/digital integrated circuits. US20230409789A1 describes learning from simulated signal values and comparing predicted outputs with actual IC outputs for validation; US20230409790A1 describes inverse models that infer inaccessible internal signals or state-machine states from top-level inputs and outputs for debug. The documents also describe simulation-test selection using coverage metrics. These are patent disclosures, not evidence of product implementation or a deployed verification service.
Two Renesas-authored papers presented in one DVCon Europe session report SystemVerilog UDN techniques for real-number modeling. One says Renesas had used Voltage-Current-Resistance UDNs for current-limited LDOs, smart chargers, and DCDC converters, then introduces a Voltage-Charge-Capacitance form for a switched-capacitor crystal oscillator and reports a 90,000x simulation-speed boost benefiting block design and chip-level integration verification. The companion paper models an LDO with current limiting and load capacitance using a self-triggering VIR-UDN mechanism and reports 84x fewer events for similar behavior, or about 778x at a coarser voltage step.
A DVCon Europe 2023 paper by SolidVue and Sungkyunkwan University authors with Scientific Analog coauthor Jaemin Park reports a SystemVerilog/XMODEL simulation platform for a SPAD-based time-of-flight sensor. Poisson-based photon and dark-count models include detection probability and dead time, and connect 64 SPADs and analog front ends to a TDC, histogram counter and timing controller. The paper shows histogram responses under varied sensor and illumination parameters and reports approximately 4.6 minutes for a 1.5-m proximity-sensor simulation. The testbench uses a 600-MHz eight-phase PLL clock with 6-ps RMS jitter. These are system-model results; measured-silicon correlation was not demonstrated.
U.S. patent US11797742B1, assigned to Synopsys, describes power-aware real-number modeling for dynamic mixed-signal verification. The disclosure detects mismatches between power-supply network and RTL HDL descriptions, generates runtime value converters for RNM analog boundaries, and can insert assertions to detect inconsistent supply values. This Event records a patent disclosure; publication does not establish customer use or product deployment.
Mariam Maurice, Mohamed Dessouky, and Ashraf Salem published an IEEE Access paper on analog PLL modeling in an event-driven simulator. It uses piecewise-linear value/slope representations with SystemVerilog user-defined types and nets for higher-order loop filters, models fractional division and phase noise, and represents output loading with resolved nets. The paper compares modeled PLL outputs with transistor-level simulation.
Keiichi Kajino's public professional profile dates the start of his SiTime Manager of Verification role to July 2023 and identifies him as Manager, Japan Verification. His profile separately describes mixed-signal verification experience including mixed-mode simulation, analog and digital assertions, Verilog-A/Verilog-AMS, SystemVerilog RNM, and UVM-based mixed-signal testbenches.
Scientific Analog hosts Jaeha Kim’s UCIe PHY Modeling and Simulation with XMODEL webinar. The resource page describes SystemVerilog models of PLL, DLL, duty-cycle correction, phase interpolation and transmitter/receiver circuits interacting with logical-layer FSMs. Training examples adjust reference voltages, clock/data timing, lane skew and link data rate using pseudo-random data; FSM coverage can be inspected in SystemVerilog. The materials include a recording, slides and a model package. The stated 4–32-GT/s range concerns model/design requirements, not a measured silicon implementation or UCIe compliance certification.
At Verification Futures UK 2023, Renesas engineers Peter Grove and Steven Holloway presented a submission to the Accellera UVM-AMS Working Group showing how an MS Bridge module could apply UVM to both AMS and DMS verification. The presentation covered simulator initialization and synchronization, stimulus and monitoring differences, a known limitation and possible solutions, and application to a mixed-signal block. The speakers said the presentation and example code had been shared with the EDA community to feed into a working-group white paper and cautioned that the implementation was not final before an official UVM-AMS release.
Apple posted a Digital-Mixed-Signal Verification Engineer role for cellular RF work whose description covers SystemVerilog behavioral models for LNA, PLL, ADC, DAC, and mixer blocks at multiple abstraction levels, matching models to schematic specifications, assertions, and UVM-based sub-system and system verification.
A Sony Semiconductor Solutions feature profiles an Automotive Business Division engineer whose work included developing analog models and system simulators to test SPAD ToF depth-sensor circuit and signal-processing designs. The profile says she designed and verified an analog sensor circuit in 2022 and moved into sensor-circuit evaluation in 2023.
A Texas Instruments ISQED 2023 paper evaluates a machine-learning behavioral-model method for time-domain waveform prediction using feature extraction, waveform segmentation, and circuit partitioning. In an operational-amplifier proof of concept, the authors report an average output-prediction signal-to-noise ratio of 32 dB. The result is an evaluated proof of concept, not evidence of production deployment.
Analog Devices authors report a Python flow that generates SystemVerilog connectivity tests from a human-readable spreadsheet for system-in-package analog/mixed-signal verification. On the reported Pin Driver ATE project, it generated checkers for more than 2,000 interface pins and completed almost 600 checks; the authors report reducing test creation from days to minutes while retaining reusable, hierarchy-aware checks.
Jaeha Kim presents a reactive UVM testbench for high-speed wireline receiver jitter tolerance at DVCon U.S. 2023. The slides identify Seoul National University and Scientific Analog affiliations and place the SystemVerilog/XMODEL transceiver, jitter stimulus and statistical BER instrumentation inside a fixture. Standard UVM components use prior BER results to select the next sinusoidal-jitter amplitude, with linear and binary searches for the pass/fail boundary. The example reports 106 trials at 20 jitter frequencies in 41 minutes for a target BER below 10^-12. The BER comes from statistical model instrumentation, not a measured silicon run or counting 10^12 received bits.
At DVCon U.S. on February 27, 2023, Siemens EDA presented a workshop describing digital-centric mixed-signal verification methods. Its program covers real-number modeling, constrained-random verification, assertions, functional coverage, formal techniques, low-power verification, and automated debug; the evidence documents vendor methodology advocacy rather than customer adoption.
A Microchip-authored paper introduces an Analog Information Model that separates real-number model functionality from the SystemVerilog mechanism used to transport analog information. The proposed nodes and connectors provide a common interface across user-defined nets, UPF-based nets, and wreal, allowing stimulus and checking components to be reused while the underlying transport representation changes.
A Renesas-authored paper compares AMS, open-loop RNM, closed-loop RNM without EEnet, and closed-loop RNM with EEnet representations of a PLL. It reports generating model testbenches from spreadsheet and symbol data with SKILL, a two-DUT mode for model-versus-schematic or model-versus-model comparison, and SystemVerilog stimulus and checkers alongside a Verilog-AMS hardware module.
A DVCon Europe 2023 paper by Samsung authors reports a UVM-based mixed-signal verification environment for an OLED display power-management IC. The authors describe 45 validated wreal models, 142 tests, assertions and automated checks, a fifteen-week turnaround, resolution of multiple port-direction issues, and pin-connectivity checks designed to guard against mismatches.
A Sony Semiconductor Solutions recruiting interview describes building an H timing-assertion mechanism to exhaustively design-verify operating conditions for signals controlling image-sensor pixels and analog circuitry. The engineer presents the mechanism as a response to control signals that the prior design approach made difficult to verify.
A Synopsys publication reports that four years of DARPA POSH work produced an AMS emulation prototype capable of running digital logic, real-number analog models, and software together. It reports a 97-fold speedup over simulation on one customer design and says commercialization was planned for 2023; it does not establish that the planned product release occurred.
An Apple Cellular and Connectivity team member publicly advertised a Digital Mixed-Signal Design/Verification Engineer role in Munich, one of four analog and mixed-signal design, validation, and verification openings in the hiring notice.
A Sony Semiconductor Solutions DVCon Japan presentation reports a CIS verification flow that models analog circuits as SystemVerilog Real Number Models to check analog/digital specification consistency early. The presentation reports a 3000x speedup compared with conventional SPICE and logic-simulator co-simulation.
Scientific Analog announces that it joined Accellera Systems Initiative as of January 15, 2022. Its January 18 announcement connects participation to its SystemVerilog analog-verification products and interoperability goals. Accellera’s August 2022 newsletter independently welcomes Scientific Analog among new members. Membership alone does not establish a particular working-group contribution, standard release, or customer adoption.
An Analog Devices-authored paper reports using DMS for full-chip functional verification and AMS for performance and detailed analog verification under a UVM-based approach. The paper states that model availability and quality determine partitioning between the flows and analyzes the coverage and bug classes each flow contributed.
A DVCon U.S. paper by Charles Dančak of Betasoft Consulting extends an object-oriented testbench into UVM for a digitally programmable analog bandpass filter. A fixture encapsulates the DUT and XMODEL stimulus/measurement primitives, while UVM components randomize frequencies and modes, compare transfer gain with HSPICE reference tables and collect functional coverage. SystemVerilog assertions check supply current and bias voltage during power-down. The paper reports agreement within 2% of HSPICE for the illustrated filter example; this is not a general analog-model error bound. The official proceedings archive assigns the work to 2022; conflicting secondary citations to 2021 are not used to backdate the Event.
A 2022 DVCon Europe paper by COSEDA Technologies and research-institute authors presents a heterogeneous assertion-based-verification library for mixed-signal virtual prototypes in SystemC AMS. The work-in-progress prototype targets interactions across software, transaction-level, digital, and analog domains. This records the published library and examples, not evidence of deployment by a semiconductor customer.
ROHM authors report using Model-Based Design for mixed-signal IC development and early specification verification. For MEMS and sensor IC work, they describe generating a SystemVerilog DPI-C model from a Simulink MEMS model and using it in the Cadence environment to validate an IC containing analog amplifiers, ADCs, and digital processing logic before sign-off. The article also describes an internal Model-Based Design Group that maintains reusable modeling assets and guidance.
Samsung Foundry authors report a mixed-signal IP verification method using netlist extraction, module conversion, custom testbenches, and Synopsys ESP symbolic simulation. The paper applies the method to eMRAM, eFLASH, and OTP memories to compare behavioral simulation models with schematic-derived implementations and describes the flow as extending symbolic verification to mixed-signal memory structures not natively covered by the tool.
A DVCon Europe 2022 paper by Samsung authors describes SystemVerilog real-number modeling for verification of a complex SSD power-management IC. The flow combined 25 models, randomized I2C programming, Python-based register checks, and 68 tests; the authors report a six-week implementation effort and simulation speedups of 100x to 1,000x over the referenced schematic simulations.
A DVCon U.S. 2022 paper by Siemens EDA's Mariam Maurice describes a SystemVerilog resolved-net model carrying voltage, previous voltage, current, capacitance, and resistance. It illustrates loading and filtering effects, real/logic boundary conversion, and interconnect debugging, with ADC, DAC, LDO, and image-sensor examples. The paper identifies UVM, assertions, and functional coverage as future verification work.
Toshiba Electronic Devices & Storage published an automotive verification case using its Accu-ROM reduced-order modeling method to derive a VHDL-AMS model from SPICE behavior for an electric-power-steering system. Toshiba reports reducing the reference simulation from 32 hours 51 minutes to 3 hours 27 minutes while reproducing the compared motor-current, temperature, and electromagnetic-interference behavior.
In an IEEE Silicon Valley SSCS-sponsored webinar, Jaeha Kim explains automatic SystemVerilog model extraction using a pipelined ADC example. Structural modeling maps circuit devices and connectivity into models, retaining a low abstraction level that limits speed improvement. Functional modeling maps selected circuit regions to predefined templates and requires manual input. The resource record lists a recording and slides. This is a demonstrated modeling workflow, not evidence of fully automatic abstraction of arbitrary analog circuits or deployment at a named customer.
Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, and Mark Horowitz published a framework combining msdsl model generation, svreal synthesizable fixed- and floating-point representations, and anasymod FPGA build and control automation. The paper demonstrates a DragonPHY receiver, a firmware-controlled flyback converter, and an NFC-powered chip. Stanford dates publication to August 4, 2021; the TCAD journal issue is dated July 2022.
A DATE 2021 paper reports metamorphic testing of an industrial partner's SystemC-AMS PLL model. A relation between scaled reference and divided-feedback frequencies exposed a PFD dead-zone bug missed by existing tests: changing the reference from 1 MHz to 1.01 MHz produced 50 kHz feedback. The authors report restoring the relation after adding delay in the PFD reset path. This concerns a system-level model rather than a demonstrated silicon defect; the industrial partner is unnamed.
A DVCon 2021 paper by Analog Devices authors describes combining SystemVerilog real-number models, RTL, and Unified Power Format for low-power digital mixed-signal verification. The environment checked supplies, isolation, level shifting, and power sequencing, and the authors report that it exposed a power-domain defect involving memory built-in self-test and a test-data register.
A Microchip-authored paper reports bidirectional UVM agents for SystemVerilog user-defined nettypes and UPF supply-net pins. The agents generate static and time-varying analog stimulus, monitor values, and are configured through reusable objects; the paper reports using the approach with the three largest simulators and discusses portability differences among them.
Samsung Semiconductor India authors report an in-house parameterized channel model integrated into a DDR-PHY verification environment for DDR4-3DS memory. The model injects routing and board delays, skew, crosstalk distortion, duty-cycle variation, setup and hold stress, and glitches; the paper says it enabled RTL-level training-algorithm checks and led to RTL and specification updates in reported cases.
A CadenceLIVE presentation by TI's Jun Yan describes running C++ automatic-test-equipment test logic in analog fault simulation through the SystemVerilog DPI-C interface. The flow runs faults at sub-block level, parses simulation logs, presents pass-or-fail results in the Cadence environment, and is described as a joint effort among design verification, ATE, and design teams.
Texas Instruments authors present a SystemVerilog EEnet model of a charge-pump regulator that represents voltage, current, and resistance and includes analog impedance interactions. The poster reports matching the schematic at 1 mA, 2 mA, 3 mA, and 4 mA load-current steps, a model runtime of 10.36 seconds, and a tenfold speedup over the schematic simulation used for comparison.
Scientific Analog announces acceptance at ICCAD 2020 of Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations, identifying researchers affiliated with Seoul National University and Samsung. The announcement describes SystemVerilog/XMODEL models tracking cell threshold voltages while exercising read, program and erase algorithms. It reports a 40-microsecond incremental-step-pulse-programming simulation of a 12-Kb single-level-cell block in under two minutes, without specifying the host setup. September 1 is the announcement date; a November 3 conference presentation was planned. Full paper access was unavailable in this check, so author details, silicon correlation and broader performance are not asserted. Scientific Analog is the announcing tool vendor, not an identified research-author affiliation.
A 2020 CadenceLIVE paper by Dialog Semiconductor's Yi Wang describes a programmable Verilog-AMS testbench with SystemVerilog Assertions and an asynchronous state machine for chip-level analog regressions. The paper reports more than 30 scenarios and 156 runs completing in 9.5 hours for daily signoff; Cadence's conference repository says the simulated results were subsequently supported by silicon measurements.
At CadenceLIVE Europe 2020, Dialog Semiconductor's Peter Grove described work with Cadence R&D on a unified testbench and an LRM-compliant SystemVerilog netlister spanning RTL, digital mixed-signal, and analog/mixed-signal simulation. This is a dated Dialog Semiconductor record and does not imply methodology transfer to Grove's later affiliations.
A DVCon Europe paper led by Gabriel Rutsch reports two FPGA prototypes for automotive magnetic sensors, using msdsl to generate synthesizable analog functional models and anasymod for FPGA build and control. One prototype supports real-time hardware-in-the-loop and customer integration; the other accelerates regression testing. The paper describes their use across product definition, verification, and design-in.
Accellera formed the UVM-AMS Working Group on November 19, 2019 after a proposed-working-group phase that began with a May 2019 meeting in Munich, naming Patrick Lynch as chair. The charter targeted a unified UVM-based analog/mixed-signal verification methodology, including standardized driving and monitoring of mixed-signal nets, stimulus, scoreboarding and analysis, plus a framework for reusable analog/mixed-signal verification components derived from digital-centric verification IP. Accellera said the planned standard was intended to support ready-to-use analog/mixed-signal verification IP from tool and IP providers.
A JKU/Infineon paper presented a virtual ATE flow that executes production-style test programs against a SystemC/SystemC-AMS virtual DUT before first silicon. In an Infineon ASIC case study, the same test program was run on the virtual ATE and later on a Teradyne UltraFLEX system, exposing the same register-test error; the authors report that this enabled test-program checks months earlier than the conventional flow.
A paper by Subhranshu Shekhar Padhee and Thapar’s Anil Arora reports LDO functional verification with a self-checking SystemVerilog/UVM testbench, Cadence Incisive and Synopsys VCS, including code, functional and cross coverage. The author biography identifies Padhee as an intern in STMicroelectronics’ Greater Noida Technology Designing Platform team working on analog and mixed-signal IP verification. This records the published internship-related technical work and contemporaneous company affiliation, not a current organization chart or adoption of the later UVM-MS standard.
An Analog Devices-authored presentation reports power-aware RNM models used with UVM supply and interrupt agents and assertions. It describes validating models against schematics, scripting chip-top connectivity, and running RNM with RTL; the authors report finding isolation and sequencing bugs and closing coverage without mixed-signal co-simulation for those full-chip tests.
A Broadcom-authored paper reports a full-chip, coverage-driven constrained-random UVM environment for mixed-signal SoCs. It describes selectable analog abstraction through SystemVerilog user-defined nettypes, Verilog-AMS, transistor-level, or mixed views, with interface UVCs, scoreboards, assertions, checkers, and coverage reused across configurations; the authors also report analog-digital and schematic bug findings.
Intel of Canada authors report a UVM verification framework for a SerDes physical-media-attachment layer that spans fast, accurate, and AMS-mode behavioral models. The presented framework uses translator blocks between real and logic data, layered adapter sequences, common end-to-end checkers, and configurable NRZ/PAM4 stimulus, with the authors reporting reuse across model modes and improved verification of pre-emphasis and equalization behavior.
A DVCon 2019 paper by Roche Sequencing Solutions authors presents a structured SystemVerilog user-defined nettype with runtime port resolution and waveform-viewer support. In a SAR ADC case, the authors report 1,183.3 seconds for the referenced SPICE simulation versus 4.7 seconds for the real-number model and say the flow exposed an incorrect MSB capacitor-switch polarity.
A DVCon 2019 paper by Texas Instruments authors describes using a SystemVerilog user-defined EEnet to model voltage, current, and resistance loading in power-regulation verification. The UVM-based flow randomized supplies, loads, and system states, supported reusable DMS and AMS environments, and extended verification to loading effects that simple voltage-only real-number interfaces could not represent.
At DVCon Europe 2018, NXP and Infineon presented company practices for extending UVM into mixed-signal verification. NXP described analog/mixed-signal verification-component and UVC concepts and identified a need for flexible APIs between physical and signal layers, including a common interface for third-party VIP; Infineon presented its A-UVM analog extension with real-valued transactions, constrained-random stimulus, automated analog checks, waveform comparison, functional coverage, and an IGBT gate-driver application. The tutorial explicitly asked whether an Accellera UVM-AMS working group should be created, and Accellera later stated that DVCon Europe discussions resulted in creation of the proposed working group.
Toshi Kawashima's public professional profile dates the start of his Apple role as Manager, DMS (Digital Mixed-Signal) Design Verification to October 2018 and says he leads a team responsible for DMS and AMS verification and methodology work across mixed-signal LSI projects.
Scientific Analog announces that the official XMODEL 2018.03 release integrates GLISTER features into Cadence Virtuoso Analog Design Environment. The announced interface supports composing testbenches, generating netlists and launching XMODEL simulations through ADE menus and commands. The company attributes the integration to its partnership with Cadence through the Connections EDA Program. March 31 is the announcement date; the version label does not establish another release day. The announcement establishes workflow integration, not functional equivalence with SPICE or a customer performance result.
A DVCon 2018 paper by Infineon authors describes a meta-model-driven flow that automatically generates real-number models and UVM-MS testbench components. In its mixed-signal ADC case, the generated RNM ran in 4.5 seconds versus 74.1 seconds for the referenced VHDL model, and the generated testbench exposed a deadlock in the analog implementation.
An NXP-authored paper reports verifying an IEEE 802.3bw 100BASE-T1 PHY with one UVM environment extended to handle its analog interface. The environment adds analog source and probe components, error injection, and analog-domain coverage while retaining the digital UVM register-model environment; the authors demonstrate the approach on a released automotive Ethernet PHY.
A 2018 DAC Designer/IP Track case study concerns analog/mixed-signal verification of DRAM peripherals with automatically generated SystemVerilog models. Scientific Analog’s announcement identifies joint work with SK hynix and Seoul National University, describes MODELZEN model generation followed by XMODEL simulation, and schedules a June 27 poster. SNU’s laboratory publication list independently records the 2018 work. The accessible sources establish the modeling flow and participants, but do not establish quantitative accuracy, speedup, silicon correlation or company-wide deployment. The Event retains year precision rather than treating the advance announcement as proof of the actual presentation day.
An Analog Devices-authored paper reports verification of a 2.4 GHz BLE and proprietary-mode transceiver SoC using UVM RF agents, real-number models, randomized packet parameters and blockers, and full-system pads-to-RTL simulation. The paper also describes Veri-DSP, an internal flow that generated UVM block testbenches and integrated Python post-processing for DSP verification.
A Cadence-authored paper reports reusing a digital UVM environment for mixed-signal verification of a Type-C USB and SerDes design. It describes analog-parameter agents, scoreboards and checkers, and added functional coverage and verification-plan content; the evidence documents a vendor-authored methodology rather than customer adoption.
Two TI-authored 2017 papers report methods for analog and mixed-signal verification. One binds assertions directly to electrical ports in a schematic; the other applies support vector machines and active learning to adaptively explore process, voltage, and temperature space for coverage and worst-case conditions.
Dialog Semiconductor's Carsten Wegener, listed with PMIC Analog in Germering, presents a model-validation process for analog behavioral models used in event-driven chip-level mixed-signal verification. The paper argues that modeling requires an associated validation process and demonstrates the approach on a mixed-signal digital I/O buffer treated as a 1-bit DAC and ADC, using post-handoff model bugs and issues as one measure of model quality.
Scientific Analog reports an August 8, 2016 announcement by Seoul National University’s MICS Group of an Analog Cell Library and reference flow released through IDEC. The flow uses XMODEL for PLL behavior/performance simulation and Synopsys IC Compiler for physical implementation. The reported Samsung 65-nm library supports an 8-GHz LC-oscillator PLL or 1–2-GHz ring-oscillator PLL and is restricted to research groups with appropriate technology access and NDA. The October 4 report quotes MICS director and Scientific Analog founder Jaeha Kim. SNU/IDEC are the library’s releasing/distributing organizations; the named tool vendors and technology provider are not thereby coauthors of every design. The source does not establish unrestricted public library availability.
A DVCon 2016 paper by Analog Devices authors reports automatically generating schematic-consistent, high-fidelity real-number abstractions for mixed-signal SoC verification. The authors describe deployment across several ADI SoC tapeouts, detection of subtle design bugs, and circuit-simulation speedups greater than 1,000x while preserving the analog-function accuracy needed for the reported verification cases.
An Analog Devices-authored paper reports a block-level UVM constrained-random testbench run against both an SV-RNM behavioral model and the analog netlist. The same stimuli and checks provide one-to-one comparison, the tests can run in regular or nightly regressions, and the paper describes reusing the block-level agents in system-level verification.
A DVCon 2016 paper by Infineon's Silvia Strähle describes UVM-based verification of an automotive mixed-signal design with more than 1,000 requirements. The environment could exchange a VHDL behavioral model for a transistor-level netlist where needed and checked analog quantities and operating conditions including temperature, overcurrent, and overtemperature behavior.
An NXP-authored paper reports low-power mixed-signal IoT case studies using CPF power intent, assertions, formal and connectivity checks, and self-checking verification while moving a verification database through Verilog, wreal, and Verilog-AMS abstraction levels. The examples include PMU, brownout detector, and LDO behavior at full-chip scope. The paper identifies evaluating UVM as a next step rather than reporting UVM deployment.
A TI-authored paper proposes an Analog Coverage Collector through which analog designers mark internal schematic and device threshold information for use by chip-level verification engineers. The paper describes turning that information into top-level covergroups and coverage data to coordinate analog design and verification work.
A DVCon 2016 paper by Texas Instruments and Cadence authors reports applying Common Power Format power intent to a complex industrial mixed-signal SoC. The flow generated power-smart interface elements, matched results from the authors' traditional inherited-interface-element method, and reduced the reported setup time from several weeks to less than two days.
A joint FH Technikum Wien/Infineon Technologies Austria paper presented a bidirectional pre/post-silicon bridge for Infineon's mixed-signal verification flow. It used a common platform-independent human-readable scripting test description, implemented with Perl, while environment-specific interpreters mapped the same test intent into the AGENtiX SystemC simulation environment or the JAZZ/lab-instrument post-silicon environment.
A Cadence press release reports that Hitachi used Virtuoso AMS Designer with real-number modeling to simulate the entire design of a backplane signal-conditioner mixed-signal chip, reducing verification from days to 30 minutes. Cadence says Hitachi presented the design and RNM results at ISSCC 2015 on February 23; this is a vendor-published customer report.
A Bosch Sensortec and Cadence DVCon Europe paper reports extending an existing digital UVM verification environment to address analog and full-chip verification in one mixed-signal testbench. The paper describes the architecture and implementation of the reusable approach and explicitly identifies wreal as part of the methodology.
A DVCon 2015 paper by Hewlett-Packard authors describes extending a mature digital UVM testbench to next-generation SerDes mixed-signal verification. The methodology supports model swapping and progressive refinement, allowing early link-training and equalization verification with behavioral models and later integration of schematics without refactoring the testbench.
A DVCon 2015 paper by Xilinx authors describes a mixed-signal verification flow combining automatically generated netlist real-number models, Octave signal processing, and a UVM environment with random stimulus and coverage. In one reported analog-multiplexer case, handwritten model content was limited to 10% of modules and 4% of lines; the paper also reports direct Octave FFT integration running 1.58x faster than its file-based comparison.
An Istanbul Technical University seminar listing dated December 2, 2014 identifies Selcuk Talay of Dialog Semiconductor as AMS Toplevel Design and Verification Lead. The record establishes his publicly identified role at that time; it does not establish when the role began.
Two Analog Devices-affiliated 2014 papers report distinct deployments. The LMA team described its local organization's first heavily analog project staffed with dedicated DV engineers, using verification planning, self-checking and constrained-random testbenches, regressions, SPICE co-simulation, and SystemVerilog RNM. A Beijing ASSP team described UVM, assertions, real-number functional coverage, regression, and metric sign-off for a Cortex-M3 mixed-signal device.
Two Infineon DVCon 2014 papers describe an Analog UVM library for constrained-random analog transactions and automated comparison of analog behaviors. The model-validation flow uses an earth mover's distance implementation connected through SystemVerilog and C to convert waveform comparison into regression pass/fail results, reducing reliance on manual waveform inspection.
A DVCon 2014 paper by Infineon and Mentor Graphics authors reports applying UPF with RTL and SPICE content to power-aware mixed-signal verification of a tire-pressure-monitoring sensor SoC. The paper says the flow exposed power blackouts, sequencing errors, missing level shifters, and incorrect isolation polarity before gate-level verification.
A DVCon 2014 paper by STMicroelectronics and Mentor Graphics authors describes a verification-plan-driven equivalence-validation component that applies common tests to analog implementations and behavioral models, produces pass/fail results and waivers, and can be reused across projects. The paper reports use by ST's high-speed serial-links group across HDMI, USB, and D-PHY work and says it exposed functional, connectivity, and test-mode differences before models were delivered to SoC teams.
A DVCon 2014 paper by Texas Instruments, IIT, and Cadence authors compares connect-module and interface-element methods for analog/mixed-signal boundaries and describes automation for true supply sensitivity. The authors state that the methods were applied on several commercial mixed-signal SoCs and present practical tradeoffs and guidelines for automating supply-sensitive interface handling.
A DVCon 2014 paper by Texas Instruments authors reports a specification-driven flow that automatically generated mixed-signal testbench elements, RTL, assertions, and results infrastructure. In a power-management case study, the authors say the approach enabled analog IP-level SPICE simulation almost three months earlier than comparable prior executions within an approximately twelve-month development cycle.
Two TI-authored 2014 papers report mixed-signal SoC verification using higher-level analog abstractions. One describes wreal models and digital-regression reuse on a 45 nm secure SoC, including functional and design-for-test integration issues; the other describes a UVM environment for an RF transceiver SoC using wreal and Verilog-AMS models, constrained-random stimulus, assertions, coverage, and a MATLAB reference-model checker.
A DVCon 2013 paper by IBM and Cadence authors reports that IBM created and deployed Verilog-AMS wreal models on a mixed-signal project. The authors describe correlation against circuit-level simulations, approximately 40x simulation speedup for a representative case, and digital mixed-signal regressions that could run overnight.
Cadence’s account of DAC 2012 identifies STMicroelectronics’ Pierluigi Daglio and Marco Carlini as authors of “Metric Driven Verification Approach for Analog/Mixed Signal IPs.” The account dates the presentation at the EDA360 Theater in San Francisco to June 5 at 4 p.m. The account was published on August 27, 2012.
At DVCon 2012, Cadence's Prabal K. Bhattacharya, Intel's Scott Little, and coauthors proposed extending SystemVerilog coverpoints to accept real-valued data for analog and mixed-signal functional coverage. The work reports a prototype following a year-long Cadence research-and-development effort and addresses real-valued bins and ranges, range precision, coverage scoring, cross coverage, and remaining floating-point issues. The affiliations are specific to this paper and do not imply methodology transfer between the companies.
A DVCon 2012 paper by Maxim Integrated and Cadence authors reports applying a UVM-MS methodology to a complex noise-cancelling receiver SoC. The case study describes an executable verification plan, wreal behavioral models, constrained-random stimulus, assertions, functional coverage, and verification closure supporting first-pass success.
An Infineon-authored paper described linking Markov-based mixed-signal constrained-random test generation to an Executable Verification Plan (XVP) so test cases could be transferred to Cadence simulators and MATLAB/Simulink for simulation and to PXI and ATE for post-silicon verification. The paper also reports applying generated tests on mixed VHDL-AMS/Verilog models and post-silicon PXI/ATE systems and identifying mixed-signal design issues.
Tomokatsu Mizukusa's public professional profile describes his 2011–2014 Renesas role as developing EDA and design methodology for mixed-signal and analog systems. It specifically reports MCU and SoC whole-chip mixed-signal functional and connectivity verification using Verilog Wreal, along with SystemVerilog discrete-real modeling and UVM-AMS.
At FMCAD 2011, John Havlicek and Freescale Semiconductor's Scott Little presented syntax and semantics for realtime regular expressions that extend SystemVerilog Assertion-style regular expressions to describe continuous-time analog and mixed-signal properties. The paper says the work was influenced by the Accellera analog-assertions effort; it does not claim an internal Freescale deployment.
A 2011 DVCon paper by LSI and Cadence authors describes real-number models for mixed-signal verification of a hard-disk-drive preamplifier and reports roughly 24x speedup over the referenced SPICE simulation with about 0.3% gain inaccuracy. A later Cadence-authored report describes LSI applying the models in mixed-signal SoC verification, reporting roughly 600x speedup, 95% accuracy, full functional coverage, and no functional bugs in first silicon. These performance and outcome statements retain their respective paper and vendor-report modalities.
A DVCon 2011 paper by Medtronic's Gregg Sarkinen reports applying an integrated analog/digital verification environment to a mixed-signal medical-device IC prototype. The flow used a verification plan, constrained-random stimulus, checkers, reusable models, and coverage closure. The paper reports more than 3,000 mixed-signal simulations with automated pass/fail results.
A 2010 journal paper coauthored by Freescale Semiconductor's Scott Little proposes automatically generating abstraction models from transistor-level simulation traces for formal verification and system simulation. The paper demonstrates the approach on a switched-capacitor integrator and a PLL phase detector and evaluates how the generated models reproduce the observed circuit behaviors.
Intel authors report a full-chip mixed-signal validation strategy that represents top-level analog ports as real-valued signals, reuses a SystemVerilog real-port testbench from top-down development through bottom-up implementation, and selectively replaces analog blocks with behavioral models. The paper says the tool-independent method was applied to three successive Intel SoC projects with open- and closed-loop mixed-signal networks and includes behavioral-model equivalence checking.
A PRIME-09 paper by University of Trieste researchers and Infineon Technologies authors Giuseppe Bernacchia and Emanuele Bodano, affiliated with Padova, describes a discrete-time buck-converter model implemented in Verilog HDL. The model combines the switching network, output inductor and capacitor, including parasitic effects. The authors compare simulated electrical waveforms with an experimental prototype in PWM continuous-conduction, discontinuous-conduction and pulse-frequency-modulation modes, and investigate controller behavior during mode transitions.