As observed on September 14, 2026, Cirrus Logic's official careers site listed an Analog Mixed Signal Modeling & Verification Engineer role for Austin, Chandler, and Greensboro. The posting says the team generates and verifies analog circuit equivalent models for analog design, UVM verification, and HW/SW validation; develops SV-RNM, SV-UDT, and Verilog-AMS models; builds DMS and AMS test plans and platforms; supports chip-level integration and regression debug; and works with UVM verification engineers so verification components are used in an AMS-UVM flow. It also names collaboration spanning pre-silicon verification and post-silicon validation plus automation for design, verification, and modeling. The public page does not expose a reliable creation date, so this Event records the observation date rather than claiming when the role was first posted.
The DVCon Japan 2026 SystemVerilog Mixed-Signal Interface Types BoF describes Accellera work to standardize connections among dissimilar SystemVerilog net types, including seamless logic-to-nettype/RNM connections that tools have historically handled with ad hoc mechanisms. The program says this foundation is expected to be incorporated into IEEE 1800/SystemVerilog-2028 and that the resulting semantics are also intended for use by the Accellera SystemVerilog-AMS and UVM-MS efforts. This records the publicly stated standards direction, not a completed IEEE revision or released SV-MSI standard.
A Broadcom Senior Digital / Mixed-Signal IC Design or Verification Engineer posting for Data Center Enterprise Storage, indexed as posted September 8, 2026 under requisition R026970, describes a methodology leader and technical bridge across US and Asia design centers. Its verification scope includes UVM-based block- and system-level testbenches, functional and code coverage closure, SVA and UVM/OVM methodology, event-driven analog-boundary modeling, and AI-assisted workflows for testbench generation and debug. A separate Broadcom careers posting, R025692, describes a closely related DMS verification methodology-leader role with the same cross-site and AI-assisted-automation themes; the postings do not establish that the two requisitions belong to the same team or define a company-wide standard.
The official DVCon Taiwan 2026 program lists a Marvell presentation by Tiger Chen titled 'From RTL+Design Spec to Cycle-True C: An AI-Assisted Bit-Match Verification Flow for TX DAC CAL'. The public program establishes an AI-assisted verification flow whose stated inputs are RTL and a design specification and whose stated reference artifact is a cycle-true C model for TX DAC calibration bit matching. Without retained paper or slides, this Event does not assert a particular generation method, accuracy result, or production-deployment scope.
Infineon posted a Bengaluru Staff Engineer Design role whose description calls for developing RNM with SystemVerilog and svreal, building FPGA prototypes for SoC and system validation, and supporting pre- and post-silicon firmware validation and hardware/software debug. The role also covers simulation and FPGA automation, continuous integration, and modeling and prototyping methodology.
Synopsys posted a Hyderabad senior staff role to own AMS verification plans, environments, coverage, and sign-off for mixed-signal IP blocks and subsystems. Its description combines SystemVerilog/UVM with Verilog-A and Verilog-AMS models and mixed-signal simulators, and calls for behavioral models and monitors to be reused across IP families. Requested circuit knowledge includes bias circuits, regulators, PLLs, ADCs, and DACs.
Arago posted a senior mixed-signal verification role in Paris or Tel Aviv to own methodology and verification of digital-to-analog interfaces in its SoCs. The responsibilities include block, subsystem, and SoC environments, behavioral and real-number models, assertions, coverage, and sign-off. SystemVerilog and UVM or an equivalent methodology are requested; SystemVerilog RNM, wreal, and Verilog-AMS appear among preferred experience.
TU Wien's repository made available an FMCAD 2026 paper by Augusto Mafra and Haniel Barbosa describing a formal-verification flow for SystemVerilog real-number models built by extending Yosys and Pono. The paper compares SMT model checking with real-arithmetic and IEEE floating-point interpretations on 31 mixed-signal benchmarks, documenting performance and semantic tradeoffs.
The official DVCon India 2026 Day 2 agenda lists “SpecPro Modeller: An AI-Driven Framework for Automated Analog Behavioural Model Generation” by Sainath Karlapalem, Atish Savale, and Vihan Shukla. Public profiles identify Karlapalem and Savale with NXP Semiconductors. The public material establishes the presentation and its stated AI-driven analog behavioral-model-generation scope, but does not expose enough detail to assert the generation algorithm, supported model languages, accuracy, or production deployment.
The DVCon India 2026 Day 2 agenda lists two AMS & Low Power Design presentations co-authored by Amit Singh: “Left-Shift Power Estimation in SoC Design: Verification-Integrated Framework for Early Power Estimation Using Digital Mixed-Signal Simulation” with Isha Sharma, and “Design-Focused Feedforward Behavioural Modeling of PLL IPs for Fast SoC Verification” with Preeti Shukla. Public profiles identify Sharma and Shukla with STMicroelectronics. This Event records the two public technical disclosures without asserting unexposed accuracy, runtime, or deployment results.
TCS and the official DVCon India 2026 agenda list an Amarnath D technical paper on a verification and reliability framework for analog compute-in-memory using GenAI-driven Portable Stimulus, presented on September 2. The public sources establish the stated framework and presentation; they do not disclose enough technical detail to assert a particular generated-test architecture, coverage gain, reliability result, or production-deployment scope.
Astera Labs posted a principal SerDes/PHY verification role for PCIe Gen6/7, UCIe, UALink, and Ethernet interfaces. The description calls for UVM environments, RNM and behavioral-model collaboration with analog designers, CDR and training checks, and analog handoff validation. It also assigns methodology decisions across AMS co-simulation, gate-level simulation, and emulation, and prefers emulator familiarity and pre/post-silicon correlation experience.
Accellera listed the Portable Stimulus Standard Draft 3.1 for public review on August 31, 2026, with comments open through September 30. Accellera describes 3.1 as a focused update to PSS 3.0 covering a stronger constraint language, more reusable libraries, greater control over generated target code, and improved address-space/register modeling.
On August 30, 2026, MediaTek's careers site listed roles in dedicated AMS modeling and verification methodology groups responsible for modeling and verification platforms, coding and validation processes, experiments, deployment, UVM, assertions, coverage closure, and automation. A related modeling role calls for SystemVerilog RNM models of oscillators, voltage references and meters, LDOs, and temperature sensors, with model-versus-schematic verification, coverage, assertions, and Python.
Apple posted related CAD Automation and Mixed-Signal Simulation Engineer roles in Austin and Sunnyvale. The senior description assigns ownership of AMS simulation methodology across analog, RF, interconnect, PMIC, and memory teams, spanning circuit and RTL simulation, behavioral modeling, co-simulation, logic equivalence, sign-off, and automation. Preferred experience includes discipline resolution, binding/IE setup, connect modules, AMSD blocks, wreal, RNM, UDN, and SystemVerilog/Verilog-A/Verilog-AMS. Both roles mention applying LLMs or AI agents to CAD software, test generation, and debug among preferred qualifications, with leadership of that work requested in the senior role.
Qorvo posted a manager role to grow and direct a mixed-signal verification team for power-loss protection, PMIC, motor-control, and battery-management products. Its responsibilities include metric-driven plans, constrained-random tests and automated checkers in a UVM environment, RNM or Verilog-AMS models, methodology improvement, and verification automation; SV-UDN/EEnet and AI-workflow familiarity are preferred. A same-day senior principal listing describes the corresponding top-level UVM and RNM/Verilog-AMS work. These postings describe hiring mandates.
Cadence posted a Milan internship role that proposes investigating generative AI on industry cases, validating AI flows, and using Model in Minutes in the Virtuoso environment to build real-number models. This is an exploratory internship mandate and product-evaluation signal, not proof of a deployed customer methodology or validated productivity result.
Skyworks posted a design-automation role whose description says a central engineering team is building an AI-enabled analog and mixed-signal design and verification platform. The role covers agentic connections to EDA simulation, DRC, LVS, electromigration, and compute schedulers, a self-evolving flow, and support for real-number-modeling workflows.
onsemi posted a Principal AMS Verification Engineer role for new power-management products including DC-DC PMIC and point-of-load devices, multiphase controllers, DrMOS, AC-DC converters, LED and SiC drivers, switches, and eFuses. The role covers complete product verification ownership, behavioral-model requirements, SystemVerilog real, Verilog-AMS and Verilog-A models, configurable testbenches, checkers and coverage, and work in the methodology team to streamline AMS development and integration flows. This is a hiring mandate, not a claim that the methods are deployed across every product.
A Samsung careers posting in Bengaluru seeks an AMS verification engineer to create behavioral real-number models for converters and LDOs and work on PMIC verification using UVM, assertions, and automation. This is evidence of a public hiring mandate and its requested scope, not proof that every listed technique was already deployed on a shipped design.
AMD posted a Rochester ASIC Design Verification Engineer role to own verification strategy and coverage closure for mixed-signal power-management IP. Responsibilities include full-SoC SystemVerilog/UVM tests, firmware/RTL co-simulation, analog-macro RNM bring-up and correlation with analog behavior, and relating post-silicon behavior to pre-silicon tests. Preferred experience names wreal, nettype real, and Verilog-AMS.
On August 14, 2026, NVIDIA posted a role to develop behavioral models and verification environments for custom mixed-signal cells used across NVIDIA products. The listing names Verilog, SystemVerilog, Perl, and Python, and covers cells including PLLs and high-speed interconnects, emulation and prototyping, and library- and chip-level integration.
Siemens published a technical overview of Symphony Pro's Mixed-Signal Visualizer for AMS verification. It describes linked hierarchy, netlist, source, and variable views; generated schematics for checking connectivity and port mapping; and paired analog/digital signal representations for inspecting A2D/D2A conversion and boundary elements.
SNUG Taiwan 2026 proceedings list a Credo presentation by Yenlin Lee and Sung En Wang titled “Time-effective Mixed-Signal PLL Verifications with RTVS Cosim and CTLE BER Analysis with Matlab for TSMC 2nm Design.” Synopsys names it a Best Presentation Award winner. The public record establishes the stated mixed-signal PLL/co-simulation and MATLAB CTLE BER-analysis scope for a TSMC 2 nm design; it does not expose the gated presentation’s measured runtime, correlation, or sign-off results.
Ayar Labs listed related Bengaluru analog/mixed-signal modeling and verification roles. Their descriptions call for capturing significant first- and second-order circuit effects in SystemVerilog RNM, comparing models with schematics, signing off models, and integrating them into full-chip digital verification. The senior staff role adds model ownership through the product lifecycle. The postings name UVM and Verilog-AMS and include wreal/EEnet and optical simulation tools among preferred experience.
Accellera lists UVM 2020-3.2 as its August 2026 reference-implementation release for IEEE 1800.2-2020. The distributed README documents fixes to register-model name lookup, object-printer cycles, compatibility APIs, and core initialization callbacks. This is a UVM library update, not a new edition of IEEE 1800.2 or UVM-MS.
At DAC 2026, ADI's Nimay Shah described a buy-plus-build approach: partner with ChipAgents for the platform while retaining domain intelligence internally. He identified an analog circuit optimizer using reinforcement learning and deep neural networks, and a coverage-closure solution, as ADI-built examples. He also described declining debug quality when moving from IP to subsystem and SoC scale. These statements are documented in the recording's English automatic captions; the cited excerpts do not identify use of ChipAgents' AMS Behavioral Modeling or AMS Layout product lines.
A DAC 2026 abstract by EKEPOWER's Irving Hsu and Siemens' Lih-Jen Hou describes a Solido flow combining transient, RF, and mixed-signal analysis for printing ICs with motor/printhead drivers, timing references, and RF sensors. The authors report up to 7.6x speed improvement over their conventional methods and an AI-assisted trimming flow that reduces top-level voltage variation; these are presentation-reported results.
An Intel and Siemens DAC 2026 presentation reports an adaptive-AI flow that identifies worst-case corners and applies brute-force-accurate high-sigma verification only where needed. For the presented level-shifter cases, the authors report 3× faster 3-sigma single-cell validation, a 10× overall runtime reduction across 256 cells at 6 sigma, and more than 14× reduction for targeted multibit glitch-height analysis. These metrics remain bounded to the reported cases and do not establish a company-wide Intel methodology.
A Microchip and Siemens DAC 2026 presentation reports a digital-on-top mixed-signal flow combining selected SPICE blocks with RTL and UPF power intent. The presentation describes AI-accelerated Solido analysis and reports more than 22× acceleration for the presented case. This preserves the customer/vendor presentation modality and does not imply the result applies to every Microchip design.
An NXP and Siemens DAC 2026 presentation reports an adaptive AI/ML verification flow that moves from a bandgap reference to an LDO case and compares the modeled results with production-silicon measurements. For the presented cases, the authors report more than 64,000× acceleration relative to brute-force simulation. The result is a bounded customer/vendor case study, not a general claim about all NXP verification.
An Impinj and Siemens DAC 2026 presentation reports a RAIN RFID verification flow in which Solido PVTMC identifies worst-case process, voltage, and temperature corners at higher sigma levels and Solido SPICE performs the corresponding simulations. The authors say the collaboration reduced required simulations and accelerated verification while meeting the presented accuracy and reliability targets. This is a bounded customer/vendor case study, not a general claim about all Impinj verification.
A Texas Instruments DAC 2026 presentation describes ANA-MODELGEN, an automated flow that generates analog behavioral models and self-checking testbenches from specifications, then checks model equivalence against SPICE. The presentation says the flow was deployed in production SoC verification flows. This records the authors' reported deployment and scope; it does not generalize the result beyond the presented TI flow.
Keysight authors at DAC 2026 report a neural-network behavioral model of a power-amplifier circuit whose training data is generated through SystemVue and ADS co-simulation. The presented model covers transient behavior and a broad power range and can be imported into system-level simulation for performance verification and design; this records the reported method, not an independent validation of its accuracy or deployment scope.
At DAC 2026, Micron's Alon Shtepel identified his ASIC organization as focused on data-center SSDs. He described collaboration with ChipAgents on dashboards, metrics, root-cause analysis, and security features, and referred to analog flows being brought up. In discussing agentic tools, he reported benefits for relatively simple IP and remaining context, speed, and accuracy problems at full-chip scale, as well as inconsistent results across engineers and model choices. These statements are documented in the recording's English automatic captions; the cited excerpts do not identify an analog block, model language, or completed production deployment of an AMS modeling product.
An NVIDIA Senior ASIC Design Verification Engineer posting for its Circuit Solutions Group describes custom IP spanning clocking, voltage regulation, and silicon correlation. It asks the role to help develop and deploy agentic-AI frameworks for stimulus generation, regression triage, debug, and root-cause analysis, while listing real-number modeling of low-level digital or mixed-signal designs and VCS-XA co-simulation as differentiating experience. This is evidence of a public hiring mandate, not proof of the capability or measured effect of a completed framework.
A Texas Instruments DAC 2026 presentation reports a UVM-MS-based flow in which verification components drive and monitor analog signals without traditional connect modules. The authors describe reusable analog VIP and report improvements in simulation runtime and verification coverage for the presented use cases. The record supports this reported TI application, not universal adoption across the company.
Bosch Sensortec posted a Dresden PhD role to develop agentic-AI software for accelerating ASIC design, verification, and test. The posting explicitly includes mixed-signal verification and testing and names coverage-driven regression optimization, AMS testbench generation, and closed-loop test-case evaluation and optimization among its example use cases.
Apple listed multiple Digital Mixed-Signal Modeling Engineer roles in its wireless silicon development team in the San Francisco Bay Area and Beaverton. The descriptions state that the roles model and verify analog, RF, mixed-signal blocks, and SoCs using SystemVerilog behavioral models and testbenches.
Broadcom posted an Analog/Mixed Signal Verilog Modeling Design Engineer role for touch-controller, wireless-power, health-sensing, and satellite analog front ends. The description calls for SystemVerilog DMS models, UDT/UDR nettypes including wreal or EEnet, model-versus-schematic verification, and experience using Cursor or chipAgents to generate analog SystemVerilog models and testbenches.
Skyworks posted a Director, Central AMS Verification role to found and lead a central AMS SoC verification team. The mandate includes an enterprise-wide UVM/RNM/AMS platform, common model and verification-IP libraries, coverage, assertions, convergence, and automation. Prabal K. Bhattacharya's public profile identifies him as leading global EDA at Skyworks, and his public post says he is hiring for this role to raise AMS verification across the company. These records establish the leadership connection and hiring mandate, not that the team is staffed or the platform deployed.
A SMACD 2026 keynote by an Infineon principal engineer describes industrial experience connecting AI assistants, retrieval-augmented knowledge systems, and EDA tools through APIs, along with a current focus on an AI-based verification methodology. Its concrete example generates SystemVerilog real-number models from schematics, specifications, or other source models while emphasizing domain knowledge, guardrails, compliance, and human review. This Event records the scope described by the keynote, not a measured deployment result.
AMD posted a role for a silicon design engineer that describes leading verification of complex PLLs across RTL, gate-level, and analog/mixed-signal simulation, with UVM, coverage, co-simulation, planning, and technical leadership responsibilities. This is evidence of a public hiring mandate, not proof that every requested flow was already deployed across AMD.
Broadcom posted a Digital Mixed-Signal Lead role for the digital control infrastructure of PLL, FLL, and DLL clocking subsystems. The description assigns partnership with verification teams to drive mixed-signal-verification and real-number-modeling strategies for high-coverage loop simulations and also names full-chip CDC and RDC sign-off for the clocking network. This is evidence of a public hiring mandate, not proof that the listed verification strategies were already deployed across Broadcom.
Micron posted a Staff Engineer role for a high-speed DDR and ONFI PHY team whose description calls for reusable SystemVerilog/UVM environments with mixed-signal simulators and fast behavioral models using SystemVerilog EEnet or wreal, or Verilog-AMS, in place of SPICE subcircuits. It also covers full-chip gate-level, power-aware, and mixed-signal co-simulation plus model validation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
Stijn Ringeling's Eindhoven University of Technology thesis reports model-based methods for nonlinear discrete- and continuous-time sigma-delta modulators with a 5,000× evaluation acceleration in the behavioral-model studies. It also reports a machine-learning behavioral model and transfer learning to transistor-level data across supply variations using 20 circuit simulations, a dataset 50× smaller than the behavioral-model dataset. No company deployment is claimed.
Texas Instruments posted an AMS verification engineer/lead role describing a high-voltage power team being built in Bengaluru for AC/DC controllers, isolated DC/DC converters, and GaN-integrated power stages. The role calls for SV-RNM and Verilog-AMS wreal/electrical models, system-level AMS tests, SystemVerilog/UVM testbenches, assertions and coverage, methodology development, and participation in post-silicon validation and debug.
Renesas posted a Mixed Signal Verification Architect role to define scalable verification and validation for digital power products used in AI, datacenter, and high-performance computing applications. The mandate connects requirements, behavioral models, RTL, AMS simulation, emulation, bench validation, and silicon through measurable criteria, coverage expectations, correlation methods, automation, and reusable evidence.
Microchip posted a Technical Staff Engineer role for system-level AMS verification and power and signal integrity on SoCs and chiplet platforms. The description covers subsystem, full-chip, and cross-chiplet AMS and SPICE simulation, mature-node analog integrated with advanced-node digital, multi-voltage domains, methodology development, silicon bring-up, and simulation-to-silicon correlation.
Analog Devices posted a role for a Staff Design Verification Engineer that asks for applying AI/ML to failure clustering, regression triage, anomaly detection, and coverage optimization in mixed-signal and UVM verification across business units. This is evidence of an explicit public hiring mandate to investigate and apply those methods, not proof of existing production deployment or measured benefit.
Marvell posted a Senior Staff Engineer role in its Central Engineering AMS IP team with end-to-end verification ownership for SerDes and other AMS or mixed-signal IP across 5 nm, 3 nm, and 2 nm nodes. The mandate covers calibration, link training, power modes, analog-digital and firmware interactions, coverage, regression, sign-off, and reusable automation using SystemVerilog and UVM. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
Siemens published a Ubitium case-study abstract describing real-number models of analog blocks integrated into Veloce Strato hardware emulation. Its PLL example operates in a RISC-V system environment, and the abstract reports acceleration while retaining correlation with traditional simulation.
Skyworks posted related AMS verification roles whose descriptions cover Verilog-A and SystemVerilog RNM behavioral models, model-versus-schematic equivalence, AMS and DMS verification, and block-to-full-chip RFIC work. The roles name PLLs, ADCs, DACs, LDOs, oscillators, power-aware verification, and flow automation, while emphasizing scalable, reusable, and portable environments.
A Synopsys careers posting seeks a senior verification manager to lead and grow distributed SERDES PHY mixed-signal verification work spanning UVM, co-simulation, emulation, and laboratory correlation. It also asks the manager to drive AI-assisted regression triage where measurable. This is evidence of a public leadership and hiring mandate, not proof that all listed methods or AI-assisted triage were already deployed.
A ChipAgents-authored technical post describes an agentic workflow for PLL, ADC, DAC, and LDO behavioral models: create reference data with a full-physics simulator, generate Verilog-A models, validate waveforms and operating behavior against golden simulation data using the same or reserved stimulus sets, detect gaps, select new simulations through active learning, retrain, and integrate models through Verilog-A, SystemVerilog, or C++ DPI interfaces. The post says the company's platform produces tests, comparison results, and plots for human review. This records the company's own platform description, not independent evidence of model accuracy or customer deployment.
onsemi posted a Mixed-Signal Verification Engineer role for analog IP integrated into digital-on-top SoCs on its 65 nm Treo BCD platform. The position owns SystemVerilog and UVM testbenches, real-number and Verilog-A/AMS behavioral models for PLLs, LDOs, DC-DC converters, and oscillators, executable plans, assertions, coverage and checkers, regression debug, and model-validation strategies. This is evidence of a public hiring mandate, not proof of completed verification outcomes.
Apple listed Mixed-Signal Verification Engineer roles for RF and mixed-signal blocks and interfaces in wireless SoCs. The descriptions assign verification planning, mixed-signal and digital UVM testbenches, reusable monitors and checkers, coverage closure, automation, and methodology improvement using AI; real-numbered SystemVerilog behavioral-model experience appears as a preferred qualification.
An Infineon Automotive Power paper at ETS 2026 described retargeting IJTAG/IEEE P1687.2 test-case descriptions into top-level SystemVerilog UVM testbenches as a shift-left path for automotive smart-power devices. The reported framework uses a renderer and a lower-level pin-level time-stamp/value transport such as STIL, and the paper presents first device results.
Apple posted a PMU modeling role whose description lists SystemVerilog real-number modeling, model-versus-schematic simulation, standalone model validation, full-chip DMS integration, model-library reuse, model accuracy metrics, regression, Python automation, and correlation with transistor-level simulation and silicon bring-up. The posting says RNM-based closed-loop simulations typically run more than 100 times faster than schematic-based simulations.
Apple posted a PMU Analog & Mixed-Signal Design Verification role for Cupertino and Austin covering full-chip mixed-signal verification, analog/RTL co-simulation, verification planning, assertions, coverage, and sign-off. Selcuk Talay publicly shared the role and described it as hiring for "my AMS design verification team," directly connecting him to the recruiting team.
Renesas listed related PMIC verification roles for battery chargers, switching regulators, and analog power IP. The descriptions cover chip-level AMS and full-chip DMS, SystemVerilog RNM and Verilog-AMS models integrated with RTL and UVM, model correlation to specifications and schematics, coverage closure and sign-off, and support for correlation to silicon bench measurements.
Apple posted an Analog Mixed-Signal Modeling Software Engineer role whose description covers multi-simulator platforms, scientific-software and automation frameworks, custom model libraries, simulation frameworks, domain-specific languages, and web interfaces for AMS circuit design.
A TechWorks presentation by Cirrus Logic engineer Gautham Sathyan describes a top-down mixed-signal verification approach spanning early architectural modeling, analog/digital boundary definition, DMS bring-up, SystemVerilog real-number models for lower-level analog cells, and chip-level AMS simulation. His public event biography identifies him with Cirrus Logic's Newbury Mixed-Signal Modeling and Verification group.
ams OSRAM posted a Senior Principal Mixed-Signal Verification Engineer role to lead a distributed verification team and own an AMS/DMS methodology roadmap. The mandate covers reusable EEnet/UDN model libraries, DMS-to-Spectre correlation, SystemVerilog/UVM-MS environments, assertions, coverage, regression, sign-off criteria, and Python automation. This is evidence of a public hiring mandate, not proof that every listed method was already deployed across the organization.
A Micron careers posting for an AMS verification role describes full-chip analog, digital, and firmware interaction, behavioral models, power-cycle verification, and use of AI-assisted coding to automate design and analysis work. This is evidence of the capabilities requested in a public hiring mandate, not proof that a specific AI-assisted flow was already deployed or measured.
A Cadence DVCon U.S. 2026 paper applies metamorphic testing to a SystemVerilog real-number model of a receiver baseband, ADC, and automatic-gain-control system where a detailed test oracle is impractical. It defines relations for doubled or halved input, constant ADC magnitude, and plus-or-minus 6 dB RSSI changes and exercises them with randomized stimuli. This is a reported case study, not an AI method or a company-wide deployment claim.
A Samsung Electronics DVCon paper described generating a PSS modeling database from IP-XACT hierarchy, interface, signal-behavior and connectivity information to automate scenario and checker generation. In the presented example, the number of identified functional-coverage bins increased from 1,193 to 1,558 (+30.5%), including cross-function bins from 38 to 203; the paper also states that PSS mainstream adoption remains limited while many organizations remain UVM-centered.
A Siemens EDA customer story reports that AnalogPort applied UVM to a 32 Gbps full-duplex die-to-die interface with 16 transmitters and 16 receivers. The story describes using Symphony Pro with Questa digital simulation and Solido SPICE simulation, automated boundary insertion, selective data recording, and MS Visualizer; this is a vendor-published customer report.
Eliyan posted verification roles that pair organization-level AMS methodology with hands-on SerDes model ownership. The director role covers RNM, SV-AMS co-simulation, behavioral-model integration, UCIe and Ethernet PHYs, PLLs, CDRs, and SerDes analog front ends; the staff role develops SystemVerilog RNM directly from schematics and verifies those models with UVM tests and assertions. These are public hiring mandates, not evidence that every flow was already deployed.
An Apple careers posting for an experienced AMS design-verification engineer says the role will help build a new team in London. It lists SystemVerilog and UVM verification, performance and power analysis, early power estimation, and research and innovation; AI and machine-learning experience appears as a desired qualification. This is evidence of a public hiring mandate, not proof that AI/ML or every requested method was already deployed.
An Indeed-hosted copy of an AMD Fellow-level pre-silicon verification posting describes a mixed-signal IP organization and asks the role to integrate UVM with real-number modeling and AMS co-simulation, modernize regression, debug, and coverage analytics, and define an AI-assisted strategy spanning intelligent test generation, regression triage, and coverage-gap prediction. This is evidence of a public hiring mandate, not proof that these methods were already deployed across AMD.
Synopsys AMS SIG India 2026 lists a Broadcom user presentation by Jeevan Ramaswamy titled “High-Capacity Macro Verification: A Unified AMS-SDF Approach using VCS PrimeSim AMS.” The public agenda and proceedings establish a Broadcom-authored macro-verification flow combining AMS and SDF in VCS PrimeSim AMS. Because the presentation deck is gated, this Event does not assert implementation details, capacity results, speedup, or deployment scope beyond the published title.
A Google careers posting for a senior verification engineer in Israel lists ownership of verification for 112G and 224G high-speed PHY signal-processing designs. The role calls for RNM or SystemVerilog-AMS flows across analog-front-end and digital-DSP boundaries, with specialized testbenches for adaptive algorithms such as LMS and Zero-Forcing covering stability, convergence time, and tracking across process-voltage-temperature corners. It also calls for link bring-up, auto-negotiation and error-recovery tests and for channel loss, crosstalk, and reflections to be represented in the DV environment. This is evidence of a public hiring requirement, not proof of a deployed internal methodology.
An Intel AMS Verification Engineer posting describes SystemVerilog behavioral models for SerDes, PMU, and DC-DC circuits, integration with digital functional verification, AMS comparison to the models, and full-chip power-up simulation. It also asks for generative-AI code generation, AI-driven debugging, automated documentation, and AI-based workflows for model development, simulation analysis, and reporting. This is evidence of a public hiring mandate, not proof that every listed AI-assisted method was already deployed or measured.
Intel posted a Senior Pre-Silicon Verification Engineer role describing functional verification of PLL and FLL clock-generator IP, SystemVerilog/UVM environments, tests, assertions and coverage, and leadership of mixed-signal validation using AMS simulations to identify and root-cause schematic bugs. This is evidence of a public hiring mandate for clock-IP verification, not proof of the completion or deployment of a particular verification flow.
A Microchip Senior Engineer I – Verification posting describes full-chip SoC and mixed-signal verification, SystemVerilog/UVM, analog-IP interactions, coverage closure, and cross-domain debug. Its AI scope includes LLM-assisted generation of code and stimuli, root-cause analysis and scripting, plus AI-driven log analysis, waveform triage, failure clustering, and trials integrated with EDA flows. This is evidence of a public hiring mandate, not proof that the listed AI-assisted techniques were already deployed or improved measured outcomes.
Monolithic Power Systems lists a Mixed-Signal Design & Verification Engineer Lead role to define and lead framework and infrastructure development for complex digital and mixed-signal ICs. The position covers behavioral modeling, analog and mixed-signal IP integration and verification, mixed-mode simulation, analog-digital interface definition, and post-silicon validation across power, sensing, motor-control, display, and audio products. This is evidence of a current hiring mandate, not proof of completed deployment.
Neurophos posted a Lead Verification Engineer role for its silicon-photonic AI platform. The position owns SoC verification strategy, UVM and constrained-random environments, SystemC model integration, regression automation, FPGA acceleration, gate-level sign-off, and development and verification of AMS and SystemVerilog models for in-house analog designs; AMS verification and RNM experience are also named as preferred skills. This is evidence of a hiring mandate, not proof of completed silicon or methodology deployment.
An NXP Careers posting for a Senior AMS Verification leader in Milan describes ownership of verification strategies, plans, environments, regressions, coverage, behavioural models, checkers, assertions, and reusable components for the Advanced Power System team, including top-level mixed-signal verification and methodology improvement. The requested experience includes Verilog, SystemVerilog, UVM, SVA, Verilog-AMS, SystemC, WREAL/RNM, and mixed-signal EDA tools. This is evidence of a public hiring mandate, not proof that every listed method is already deployed.
NXP posted a Principal AMS Verification Engineer role to own SerDes verification from concept through sign-off. The description covers UVM and UVM-AMS environments, RNM and Verilog-AMS model development and validation, PLL and CDR behavior, link training and adaptation, jitter and noise analysis, assertions and coverage, PVT and stress verification, and correlation among MATLAB or Python, behavioral models, and transistor-level simulation. This is evidence of a hiring mandate, not proof of project completion.
OLIX posted a Senior Mixed-Signal Verification Engineer role to own verification of high-speed I/O receive and transmit chains in its AI accelerator, including CDRs, phase interpolators, clock generation, equalization, samplers, slicers, deserializers, and digital control loops. The role defines fidelity tiers across RNM, Verilog-AMS, and transistor co-simulation, owns self-checking testbenches, coverage and sign-off, builds regression automation, and correlates models with silicon. This is evidence of a public hiring mandate, not proof of completed deployment.
Semtech posted related senior verification roles in San Diego and Hyderabad covering verification plans for mixed-signal IP, subsystems, and full ICs; SystemVerilog and UVM testbenches; RTL, gate-level, and AMS simulation; constrained-random stimulus; assertions, functional and code coverage; continuous integration and regression automation; and desired SV-RNM or Verilog behavioral modeling. The San Diego role is tied to low-power sensing ICs with ADCs. These postings evidence a hiring mandate, not completed deployment.
Cirrus Logic posted a Mixed Signal Modelling and Verification Engineer role to lead verification activities and help evolve company methodology for complex mixed-signal ICs. The position covers verification strategy, reusable testbenches, real-number modeling, SystemVerilog user-defined types and Verilog-AMS, hands-on modeling and simulation, and desired experience in UVM, assertions, functional and code coverage, and CPF or UPF power-aware verification. This is evidence of a hiring mandate, not proof that every listed practice is deployed in every project.
Apple posted a Wireless Radio Verification Engineer role whose description covers radio digital controllers and Digital+RF subsystems spanning PLL, DAC and ADC data paths, power management, and coexistence. The hiring mandate includes UVM environments, constrained-random tests, coverage and assertions, and digital-plus-mixed-signal co-simulation integrating SystemVerilog behavioral and DMS models.
A Siemens forum recap reports two Microchip posters: mixed-signal code-coverage analysis of a temperature/voltage sensor exposed RTL bugs missed by standalone digital verification; a battery-backed SRAM case used Symphony Get Analog Value and checkpoint save/restore for analog visibility and debug. The date records publication of the vendor recap.
A Siemens EDA customer-story recap reports that TOPPAN presented a full-chip mixed-signal verification workflow for a complex CMOS image sensor integrating a microcontroller with analog blocks including LDO, PLL, and temperature sensors. Siemens reports that Symphony reduced TOPPAN's mixed-signal verification time by more than 50% without compromising accuracy; this is a vendor-published customer report.
Mythic posted a Senior Digital & Mixed-Signal Verification Engineer role responsible for making its analog flash-compute core accurately and thoroughly verifiable in digital and mixed-signal flows. The position spans RNM creation and verification, UVM, top-level algorithm verification, mixed-signal interfaces and specifications, and controller and FSM verification for data converters, PLLs, and power converters. This is evidence of a public hiring mandate, not proof of verification completion or product deployment.
An ams OSRAM DVCon Europe 2025 paper reports using digital mixed-signal simulation for early full-chip power estimation. Analog-model states map to quiescent-current values inside a central UVM testbench spanning multiple rails and IP blocks. The authors present the method as an early-estimation aid alongside detailed verification, not as a replacement for analog sign-off.
Robert Bosch authors report a cross-level verification flow that applies the same use-case scenarios across system specifications, virtual prototypes, RTL and mixed-signal design representations, and production software. The paper describes automated signal mapping and trace comparison and presents an automotive ASIC case study intended to expose inconsistencies among parallel representations and exercise mixed-signal hardware with real-field software scenarios.
An NXP DVCon Europe 2025 paper reports a gyroscope verification flow using UVM-MS, custom user-defined nets for voltage, current, resistance, and capacitance, Python through DPI, and safety-mechanism checks. In one capacitor-model comparison, the paper reports 24 seconds for a custom enet implementation, 129 seconds for EEnet, and 256 seconds for Verilog-AMS. Those timings apply only to that example and simulator setup.
An STMicroelectronics DVCon Europe 2025 paper reports a voltage-aware SRAM verification flow using SystemVerilog real-valued supply modeling and UPF supply-net types for retention memory and bias-generator behavior. For the presented case, the paper contrasts roughly two to three hours of SPICE simulation with 10 to 12 seconds in the digital flow. It also states limitations including PVT representation and simulator-specific UPF behavior.
Apple posted an Aeon Modeling Intern role in Munich. Its description places the internship in an AMS modeling software team and lists behavioral and electrical models for SerDes, PLLs, memory interfaces, and data converters; comparison with circuit simulations and measurements; modeling methods and automation; simulation-accuracy tradeoffs; and LLM-assisted model and software-framework development.
A KIOXIA SNUG Japan presentation reports that flash-memory control uses many analog circuits and is repeatedly verified with SPICE simulation including AMS co-simulation. It describes applying PrimeSim HT and a VC Execution Manager utility in product development to reduce verification time and optimize simulation-job execution within limited computing resources.
Mariam Maurice, Rich Edelman, Mohamed Dessouky, and Ashraf Salem published an Integration paper applying constrained-random stimulus, functional coverage, assertions, and a UVM testbench to an analog PLL real-number model. The paper varies loop-filter parameters, charge-pump current, and VCO gain, and compares modeled outputs with a reference model. Its first-online date is September 12, 2025, although the journal volume is dated 2026; the reported DUT is an RNM model.
The official DVCon India 2025 agenda lists an Infineon presentation titled 'Scalable and cost-effective mixed signal modelling using AI with SV-RNM' by Sathyanarayana Ramamoorthy, Rutvikkumar Patel, Anand Rahul, Kranthi Kiran, and Hareesh Perumal. The public agenda establishes the presentation and its stated topic; without a retained paper, this Event does not assert a specific model-generation method, result, or deployment scope.
A DVCon Japan 2025 presentation by COSEDA Technologies authors describes a pure-C++ assertion library for SystemC AMS using templates and operator overloading to provide SVA-like expression of temporal properties, including support for timed-data-flow models. This records a presented library and its stated capabilities, not a semiconductor-customer deployment.
A 3.0 revision was publicly demonstrated in August 2025. The update extends motion and adds additional expression states during real-time operation, increasing the range of observable behavior while retaining the earlier interactive form.
SiTime posted a verification role whose responsibilities included developing SystemVerilog real-number models, a digital-top SystemVerilog verification plan, UVM scoreboards, monitors, and sequencers, SVA, functional coverage, simulation debug, and tape-out sign-off. The listing named wreal/V-AMS, UVM-AMS, and formal property verification as relevant experience. A Munich listing checked in September 2026 repeats this responsibility and qualification pattern.
At Verification Futures UK 2025, Renesas engineer Steve Holloway presented a concrete example of creating a DAC verification component using the new UVM-MS methodology. The published session description identifies the verification-component architecture and code snippets as key content. This is a public UVM-MS implementation example from a Renesas engineer, not evidence of company-wide or product-wide deployment.
A Texas Instruments DAC 2025 presentation describes an Analog Assertion and Coverage Toolbox that checks range, frequency, ramp, and glitch behavior and identifies stimulus gaps across SPICE and behavioral-model verification. The record supports the presented checker and coverage workflow; it does not establish use on every TI program.
An STMicroelectronics and Synopsys DAC 2025 presentation reports full-chip SPICE simulation of a design exceeding 100 million transistors with PrimeSim XA. The authors describe finding current-consumption and functional issues in the presented case. This preserves the customer/vendor presentation modality and does not generalize the result to all ST designs.
A Microsoft and Siemens DAC 2025 presentation reports additive-AI verification of a 17,000-device bandgap design to five sigma. For the presented case, the authors report 40.4× fewer simulations and 19.4× lower wall-clock time, from about six hours to 18 minutes. The result remains a bounded customer/vendor case and is not generalized to other designs.
Two adjacent DAC 2025 presentations by STMicroelectronics and Cadence authors report bounded AI-assisted high-sigma cases. A delta-sigma-converter study reports 9× fewer samples, 90 dB SFDR, and a 4× DAC-area reduction in its presented flow; a bandgap-reference study reports 36× turnaround improvement by reducing one million samples to about 2,600 at 4.2 sigma. The metrics remain tied to their respective cases and do not establish a company-wide methodology.
A Texas Instruments and Cadence DAC 2025 presentation reports an EEnet-based analog test-bus method for checking voltage, current, loading, and coupling behavior. The authors describe using the real-number abstraction to reduce reliance on AMS simulation for the presented verification tasks. This is a reported customer/vendor method, not a claim that EEnet replaces circuit-level verification.
A THine Electronics and Siemens DAC 2025 presentation reports AI-accelerated four-sigma verification for 8×8 phase interpolators across 64 process modes. The authors contrast thousands of guided simulations with at least ten million brute-force samples and report a 100× simulation-count reduction for the presented case. The metric is specific to this customer/vendor study.
Renesas posted a senior staff AMS verification role to support top-down design and full-custom ASIC verification. The position covers Verilog-AMS and SystemVerilog behavioral models, real-number modeling, self-checking mixed-signal simulation, verification planning and regressions, chip-level integration, and Python and Cadence SKILL automation for project and verification flows. This is evidence of a public hiring mandate, not proof that every listed method was deployed across Renesas.
Apple listed Mixed-Signal Model Verification Engineer roles whose description includes self-checking SystemVerilog testbenches that compare behavioral models with source circuits, functional checks against specifications, assertions, formal logical equivalence, lint and timing checks, and flow automation across mixed-signal design teams.
An ISCAS 2025 paper by Eindhoven University of Technology and NXP authors reports a model-based method for evaluating fourth-order sigma-delta-modulator linearity in Simulink. For the presented study, the authors report comparable linearity accuracy using 5,000× fewer bitstream samples and describe the resulting gain in statistical coverage. This is a bounded joint research result, not evidence of deployment across NXP programs.
U.S. patent application US20250117560A1, assigned to Texas Instruments, describes obtaining analog-simulation logs, training a neural network, deriving a mathematical transfer function, and producing a SystemVerilog-compatible simulation kernel for real-number modeling. This Event records a published patent disclosure; publication does not establish product implementation, internal deployment, or the scope of any deployed flow.
Silicon Labs posted a Staff or Senior Staff AMS Verification role whose description covers functional, performance, and power sign-off for next-generation IP and SoCs using RNM models. The role includes Verilog-D, Verilog-A or Verilog-AMS behavioral modeling, block- and chip-level verification, self-checking regressions, model validation, silicon correlation, and SystemVerilog/UVM experience. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
A DVCon U.S. 2025 paper by Ulkasemi and Designer's Guide Consulting authors reports an object-oriented UVM utility for mixed-signal verification that manages temperature, model parameters, fault injection, and reporting. The paper demonstrates PLL and temperature-sensor use cases and reports a roughly two-minute simulation for the presented setup. Although the paper discusses broader automation trends, it does not establish an AI-based implementation.
At DVCon U.S. 2025, Qualcomm, Advantest and Cadence presented a unified device-sign-off flow that hands PSS-based tests from design verification to a silicon-validation bench through an FDAT functional-test container. The concrete use case used a parameterized CPU-binning test, native binary execution, runtime parameters and PSS coverage/debug; the presenters reported a 5x PSS productivity gain and hours saved per DV-SV iteration by avoiding pattern conversion.
On February 4, 2025, Accellera released UVM-MS 1.0, defining mixed-signal bridge and proxy components for driving and monitoring mixed-signal nets. The standard's participant list names active contributors from Cadence, Intel, Siemens EDA, Synopsys, NXP, Qualcomm, and Renesas; participation in the standard does not by itself establish deployment at those companies.
A DVCon Europe 2025 paper by ams OSRAM authors describes collecting analog-IP functional coverage from the same UVM top-level testbench for real-number models and transistor-level schematics. A common real-valued reference and mixed-signal sampler supported both modes; the authors report that AMS runs exposed effects such as glitch filtering that the real-number model did not reproduce.
A DVCon U.S. 2025 paper by Cirrus Logic and MathWorks authors describes generating SystemVerilog DPI-C components from system-level models for reuse in mixed-signal verification. A reported test ran in 30 seconds with DPI-C versus 51 seconds with a user-defined nettype and 54 seconds with Verilog-AMS. The paper also contrasts two projects whose closed-loop verification began 18 and 43 weeks after RTL availability; those project timings are not presented as a controlled comparison.
Apple posted a Mixed-Signal Behavioral Modeling Engineer role whose description includes SystemVerilog models that capture functional and non-ideal behavior, circuit-simulation and formal-equivalence checks, reusable modeling methodology, functional coverage, and automation for PLL/DLL, SerDes, sensor, and data-converter circuits.
An Infineon job record for its central design-flow department in Dresden describes developing and integrating methods and software extensions for analog and mixed-signal verification automation, including SPICE simulation, reliability, optimization, and regression tooling. The role also lists AI/ML knowledge as an advantage. This is evidence of a public hiring mandate, not proof that a specific automated or AI-assisted flow was already deployed.
An Infineon job record for a Senior Engineer Verification role lists Verilog, wreal, or SV-RNM behavioral modeling; AMS verification for SoCs or IPs; test planning and debug; and independent mixed-signal-verification project and methodology-improvement responsibilities. It also names Verilog-AMS, SystemVerilog/UVM, and Cadence, Synopsys, and Mentor AMS tools. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
An Infineon ITC 2024 poster described an industrial application of IEEE P1687.2 for post-silicon verification of a smart-power device. The work used IJTAG chip-level PDL to simplify test implementation in the laboratory and framed the approach as a way to improve reuse where lab flows had limited reuse of test cases and patterns from pre-silicon verification or test engineering.
A Sony Semiconductor Solutions SNUG Japan presentation describes applying PrimeSim Custom Fault to analog circuits in automotive image sensors, which the session abstract identifies as mixed-signal ICs. It reports deriving fault-detection rates from the fault-injection verification and feeding the results back into the design to improve the detection rate.
A Texas Instruments DVCon India 2024 paper reports a compact Verilog-AMS checker and assertion library for adaptive detection of kickback and frequency glitches across SPICE and behavioral-model verification. The paper describes automated checker insertion and execution-flow optimization. The word intelligent appears in the paper title, but the supported implementation is an adaptive checker flow rather than a demonstrated generative-AI system.
Accellera announced board approval and immediate availability of Portable Test and Stimulus Standard 3.0. Its principal addition is behavioral coverage, which specifies action-order and data combinations that generated scenarios should exercise. The release also adds cooperative multitasking, address-space groups, and mapping of PSS lists to SystemVerilog.
At DAC 2024, Samsung authors presented a digital mixed-signal verification approach that combines lower-level behavioral models with a SystemVerilog user-defined EEnet to represent electrical loading in power-management IC verification. The presentation describes extending the DMS verification checklist to performance and loading behaviors beyond voltage-only interfaces.
An initial real-time representation of Lunlun was publicly demonstrated in June 2024. The session exposes continuously observable motion, expression changes, and interactive response, providing a behavioral baseline for later revisions.
A DVCon U.S. 2024 paper by InnoPhase and Designer's Guide Consulting authors reports a Python and Jinja flow that generates UVM testbench infrastructure from a DUT port list, including analog interfaces and agents plus register-abstraction integration. The paper presents deterministic template-based automation; it does not describe an AI-generated testbench flow.
At DVCon U.S. 2024, Meta Reality Labs' Sandeep Sharma presented a UVM-based AMS co-simulation methodology that dynamically switches between real-number and SPICE representations while reusing digital mixed-signal checks, assertions, and random stimulus. The paper reports a nightly flow in which one AMS/SPICE test verified seven ADC configurations over a week.
At DVCon U.S., Siemens EDA's Mariam Maurice presented methods for verifying ADC and DAC real-number models with randomized stimulus, functional coverage, assertions, and UVM. The paper includes constrained variation of reference and supply voltages and coverage of real-valued signal ranges. Its verification targets are modeled analog devices and their specified behavior.
A DVCon U.S. 2024 paper by Ulkasemi and Designer's Guide Consulting authors describes validating analog behavioral models against schematics and then integrating them into a full-chip UVM environment. The paper discusses complementary AMS and digital mixed-signal tradeoffs and presents the method as a reusable verification architecture, not as proof that behavioral abstraction replaces circuit-level verification.
A Qualcomm Technologies DVCon paper reported using PSS to reuse constrained-random scenario specifications across verification platforms and integration levels. Its executor model maps the same scenario operations either to UVM agents or to embedded processors; the reported fast-platform initialization case changed executor constraints without changing the scenario structure and showed about a 30% average runtime improvement.
Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.
Accellera formed the SystemVerilog Mixed-Signal Interface Types Working Group to define SystemVerilog-compatible interconnect, conversion and resolution among dissimilar net types, including bidirectional connections between logic or user-defined nets and analog, electrical or real signals. Accellera said work in the UVM-MS and SystemVerilog-AMS groups had exposed a fundamental need for this capability within IEEE 1800 and that earlier approaches outside IEEE 1800, such as Verilog-AMS connect modules, had not met the complexity and usability requirements of typical SoCs. Peter Grove was named co-chair of the new working group.
AMD authors report a flow that reads a Standard Delay Format file, generates a SystemVerilog specify block for analog-boundary IOPATH delays, and instantiates it in an analog behavioral model for back-annotated mixed-signal gate simulation. In two reported IP cases with about 40 analog-interface signals, the automated approach reduced manual effort and annotated all paths; the paper also reports uncovering a constraint issue in one project after complete delay annotation.
A DVCon Europe 2024 paper by University College Cork and Analog Devices authors evaluates an experimental workflow that learns from analog simulation data and generates a SystemVerilog inference model. For an RC demonstration, the paper reports 16 seconds for analog simulation, 15 seconds for a non-AI SystemVerilog model, and 14 seconds for the AI model, and says the approach was evaluated at ADI with promising results. It does not establish production deployment.
A DVCon Europe paper by Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker describes svreal extensions that detect range violations and precision loss in simulation by comparing fixed-point calculations with a shadow SystemVerilog real representation. Its Integrated Fixedpoint Analyzer interprets fixed-point signal values during FPGA debug. A buck-converter model illustrates the flow between host simulation and FPGA emulation.
An NXP-authored paper reports reusing pre-silicon AMS functional tests in post-silicon validation with matching stimulus timing and side-by-side waveform visualization. The methodology uses Jupyter and Python around a reusable environment for product variants; the authors report deployment across multiple projects and products and one-day silicon bring-up.
A DVCon Europe 2024 paper by Samsung authors describes reusing a configurable digital mixed-signal UVM environment for a selected set of analog/mixed-signal tests coupled to a SPICE simulator. In the display-PMIC case, the authors report finding critical schematic issues before tapeout and correlating verification results with silicon measurements.
Samsung Foundry authors report a SystemVerilog embedded-MRAM behavior model that incorporates write-time and write-voltage variation into bit-cell test behavior. The reported simulations exercise random write time and voltage-dependent intended write failures, and the authors state that the variation-aware operation was verified with the Digital Nonvolatile-memory Assist IP used to control the MRAM for IP validation.
Two U.S. patent applications assigned to Texas Instruments disclose complementary machine-learning techniques for analog or hybrid analog/digital integrated circuits. US20230409789A1 describes learning from simulated signal values and comparing predicted outputs with actual IC outputs for validation; US20230409790A1 describes inverse models that infer inaccessible internal signals or state-machine states from top-level inputs and outputs for debug. The documents also describe simulation-test selection using coverage metrics. These are patent disclosures, not evidence of product implementation or a deployed verification service.
Two Renesas-authored papers presented in one DVCon Europe session report SystemVerilog UDN techniques for real-number modeling. One says Renesas had used Voltage-Current-Resistance UDNs for current-limited LDOs, smart chargers, and DCDC converters, then introduces a Voltage-Charge-Capacitance form for a switched-capacitor crystal oscillator and reports a 90,000x simulation-speed boost benefiting block design and chip-level integration verification. The companion paper models an LDO with current limiting and load capacitance using a self-triggering VIR-UDN mechanism and reports 84x fewer events for similar behavior, or about 778x at a coarser voltage step.
Cadence reported that a verification-reuse effort presented at CadenceLIVE India 2023 came from a joint Infineon, Tessolve and Cadence project. Infineon owned the DUT and verification environment, Tessolve developed and executed PSS/SLN models in Perspec, and Cadence supplied PSS methodology/tool support. Cadence's described use case ran the models with a Specman e simulation testbench and Linux at SoC level, while targeting reuse across IP, subsystem, SoC and silicon.
U.S. patent US11797742B1, assigned to Synopsys, describes power-aware real-number modeling for dynamic mixed-signal verification. The disclosure detects mismatches between power-supply network and RTL HDL descriptions, generates runtime value converters for RNM analog boundaries, and can insert assertions to detect inconsistent supply values. This Event records a patent disclosure; publication does not establish customer use or product deployment.
Mariam Maurice, Mohamed Dessouky, and Ashraf Salem published an IEEE Access paper on analog PLL modeling in an event-driven simulator. It uses piecewise-linear value/slope representations with SystemVerilog user-defined types and nets for higher-order loop filters, models fractional division and phase noise, and represents output loading with resolved nets. The paper compares modeled PLL outputs with transistor-level simulation.
Keiichi Kajino's public professional profile dates the start of his SiTime Manager of Verification role to July 2023 and identifies him as Manager, Japan Verification. His profile separately describes mixed-signal verification experience including mixed-mode simulation, analog and digital assertions, Verilog-A/Verilog-AMS, SystemVerilog RNM, and UVM-based mixed-signal testbenches.
At Verification Futures UK 2023, Renesas engineers Peter Grove and Steven Holloway presented a submission to the Accellera UVM-AMS Working Group showing how an MS Bridge module could apply UVM to both AMS and DMS verification. The presentation covered simulator initialization and synchronization, stimulus and monitoring differences, a known limitation and possible solutions, and application to a mixed-signal block. The speakers said the presentation and example code had been shared with the EDA community to feed into a working-group white paper and cautioned that the implementation was not final before an official UVM-AMS release.
Apple posted a Digital-Mixed-Signal Verification Engineer role for cellular RF work whose description covers SystemVerilog behavioral models for LNA, PLL, ADC, DAC, and mixer blocks at multiple abstraction levels, matching models to schematic specifications, assertions, and UVM-based sub-system and system verification.
A Sony Semiconductor Solutions feature profiles an Automotive Business Division engineer whose work included developing analog models and system simulators to test SPAD ToF depth-sensor circuit and signal-processing designs. The profile says she designed and verified an analog sensor circuit in 2022 and moved into sensor-circuit evaluation in 2023.
An Infineon Automotive Power ETS paper described a MATLAB/Simulink virtual prototype for an automotive mixed-signal gate-driver IC, combining a digital FSM/SPI register model with analog modules including PMU, charge pump and gate-control circuitry. The prototype reused pre-silicon top-level models and was fully controlled from the existing lab automation environment used later for post-silicon verification, with measurement-hardware limitations modeled in the virtual setup.
A Texas Instruments ISQED 2023 paper evaluates a machine-learning behavioral-model method for time-domain waveform prediction using feature extraction, waveform segmentation, and circuit partitioning. In an operational-amplifier proof of concept, the authors report an average output-prediction signal-to-noise ratio of 32 dB. The result is an evaluated proof of concept, not evidence of production deployment.
Analog Devices authors report a Python flow that generates SystemVerilog connectivity tests from a human-readable spreadsheet for system-in-package analog/mixed-signal verification. On the reported Pin Driver ATE project, it generated checkers for more than 2,000 interface pins and completed almost 600 checks; the authors report reducing test creation from days to minutes while retaining reusable, hierarchy-aware checks.
At DVCon U.S. on February 27, 2023, Siemens EDA presented a workshop describing digital-centric mixed-signal verification methods. Its program covers real-number modeling, constrained-random verification, assertions, functional coverage, formal techniques, low-power verification, and automated debug; the evidence documents vendor methodology advocacy rather than customer adoption.
A Microchip-authored paper introduces an Analog Information Model that separates real-number model functionality from the SystemVerilog mechanism used to transport analog information. The proposed nodes and connectors provide a common interface across user-defined nets, UPF-based nets, and wreal, allowing stimulus and checking components to be reused while the underlying transport representation changes.
A Renesas-authored paper compares AMS, open-loop RNM, closed-loop RNM without EEnet, and closed-loop RNM with EEnet representations of a PLL. It reports generating model testbenches from spreadsheet and symbol data with SKILL, a two-DUT mode for model-versus-schematic or model-versus-model comparison, and SystemVerilog stimulus and checkers alongside a Verilog-AMS hardware module.
A DVCon Europe 2023 paper by Samsung authors reports a UVM-based mixed-signal verification environment for an OLED display power-management IC. The authors describe 45 validated wreal models, 142 tests, assertions and automated checks, a fifteen-week turnaround, resolution of multiple port-direction issues, and pin-connectivity checks designed to guard against mismatches.
A Sony Semiconductor Solutions recruiting interview describes building an H timing-assertion mechanism to exhaustively design-verify operating conditions for signals controlling image-sensor pixels and analog circuitry. The engineer presents the mechanism as a response to control signals that the prior design approach made difficult to verify.
A Synopsys publication reports that four years of DARPA POSH work produced an AMS emulation prototype capable of running digital logic, real-number analog models, and software together. It reports a 97-fold speedup over simulation on one customer design and says commercialization was planned for 2023; it does not establish that the planned product release occurred.
An Apple Cellular and Connectivity team member publicly advertised a Digital Mixed-Signal Design/Verification Engineer role in Munich, one of four analog and mixed-signal design, validation, and verification openings in the hiring notice.
A Sony Semiconductor Solutions DVCon Japan presentation reports a CIS verification flow that models analog circuits as SystemVerilog Real Number Models to check analog/digital specification consistency early. The presentation reports a 3000x speedup compared with conventional SPICE and logic-simulator co-simulation.
An Analog Devices-authored paper reports using DMS for full-chip functional verification and AMS for performance and detailed analog verification under a UVM-based approach. The paper states that model availability and quality determine partitioning between the flows and analyzes the coverage and bug classes each flow contributed.
A 2022 DVCon Europe paper by COSEDA Technologies and research-institute authors presents a heterogeneous assertion-based-verification library for mixed-signal virtual prototypes in SystemC AMS. The work-in-progress prototype targets interactions across software, transaction-level, digital, and analog domains. This records the published library and examples, not evidence of deployment by a semiconductor customer.
ROHM authors report using Model-Based Design for mixed-signal IC development and early specification verification. For MEMS and sensor IC work, they describe generating a SystemVerilog DPI-C model from a Simulink MEMS model and using it in the Cadence environment to validate an IC containing analog amplifiers, ADCs, and digital processing logic before sign-off. The article also describes an internal Model-Based Design Group that maintains reusable modeling assets and guidance.
Samsung Foundry authors report a mixed-signal IP verification method using netlist extraction, module conversion, custom testbenches, and Synopsys ESP symbolic simulation. The paper applies the method to eMRAM, eFLASH, and OTP memories to compare behavioral simulation models with schematic-derived implementations and describes the flow as extending symbolic verification to mixed-signal memory structures not natively covered by the tool.
A DVCon Europe 2022 paper by Samsung authors describes SystemVerilog real-number modeling for verification of a complex SSD power-management IC. The flow combined 25 models, randomized I2C programming, Python-based register checks, and 68 tests; the authors report a six-week implementation effort and simulation speedups of 100x to 1,000x over the referenced schematic simulations.
A DVCon U.S. 2022 paper by Siemens EDA's Mariam Maurice describes a SystemVerilog resolved-net model carrying voltage, previous voltage, current, capacitance, and resistance. It illustrates loading and filtering effects, real/logic boundary conversion, and interconnect debugging, with ADC, DAC, LDO, and image-sensor examples. The paper identifies UVM, assertions, and functional coverage as future verification work.
Toshiba Electronic Devices & Storage published an automotive verification case using its Accu-ROM reduced-order modeling method to derive a VHDL-AMS model from SPICE behavior for an electric-power-steering system. Toshiba reports reducing the reference simulation from 32 hours 51 minutes to 3 hours 27 minutes while reproducing the compared motor-current, temperature, and electromagnetic-interference behavior.
Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, and Mark Horowitz published a framework combining msdsl model generation, svreal synthesizable fixed- and floating-point representations, and anasymod FPGA build and control automation. The paper demonstrates a DragonPHY receiver, a firmware-controlled flyback converter, and an NFC-powered chip. Stanford dates publication to August 4, 2021; the TCAD journal issue is dated July 2022.
A DVCon 2021 paper by Analog Devices authors describes combining SystemVerilog real-number models, RTL, and Unified Power Format for low-power digital mixed-signal verification. The environment checked supplies, isolation, level shifting, and power sequencing, and the authors report that it exposed a power-domain defect involving memory built-in self-test and a test-data register.
A Microchip-authored paper reports bidirectional UVM agents for SystemVerilog user-defined nettypes and UPF supply-net pins. The agents generate static and time-varying analog stimulus, monitor values, and are configured through reusable objects; the paper reports using the approach with the three largest simulators and discusses portability differences among them.
Samsung Semiconductor India authors report an in-house parameterized channel model integrated into a DDR-PHY verification environment for DDR4-3DS memory. The model injects routing and board delays, skew, crosstalk distortion, duty-cycle variation, setup and hold stress, and glitches; the paper says it enabled RTL-level training-algorithm checks and led to RTL and specification updates in reported cases.
A CadenceLIVE presentation by TI's Jun Yan describes running C++ automatic-test-equipment test logic in analog fault simulation through the SystemVerilog DPI-C interface. The flow runs faults at sub-block level, parses simulation logs, presents pass-or-fail results in the Cadence environment, and is described as a joint effort among design verification, ATE, and design teams.
Texas Instruments authors present a SystemVerilog EEnet model of a charge-pump regulator that represents voltage, current, and resistance and includes analog impedance interactions. The poster reports matching the schematic at 1 mA, 2 mA, 3 mA, and 4 mA load-current steps, a model runtime of 10.36 seconds, and a tenfold speedup over the schematic simulation used for comparison.
A 2020 CadenceLIVE paper by Dialog Semiconductor's Yi Wang describes a programmable Verilog-AMS testbench with SystemVerilog Assertions and an asynchronous state machine for chip-level analog regressions. The paper reports more than 30 scenarios and 156 runs completing in 9.5 hours for daily signoff; Cadence's conference repository says the simulated results were subsequently supported by silicon measurements.
At CadenceLIVE Europe 2020, Dialog Semiconductor's Peter Grove described work with Cadence R&D on a unified testbench and an LRM-compliant SystemVerilog netlister spanning RTL, digital mixed-signal, and analog/mixed-signal simulation. This is a dated Dialog Semiconductor record and does not imply methodology transfer to Grove's later affiliations.
A DVCon Europe paper led by Gabriel Rutsch reports two FPGA prototypes for automotive magnetic sensors, using msdsl to generate synthesizable analog functional models and anasymod for FPGA build and control. One prototype supports real-time hardware-in-the-loop and customer integration; the other accelerates regression testing. The paper describes their use across product definition, verification, and design-in.
Accellera formed the UVM-AMS Working Group on November 19, 2019 after a proposed-working-group phase that began with a May 2019 meeting in Munich, naming Patrick Lynch as chair. The charter targeted a unified UVM-based analog/mixed-signal verification methodology, including standardized driving and monitoring of mixed-signal nets, stimulus, scoreboarding and analysis, plus a framework for reusable analog/mixed-signal verification components derived from digital-centric verification IP. Accellera said the planned standard was intended to support ready-to-use analog/mixed-signal verification IP from tool and IP providers.
A JKU/Infineon paper presented a virtual ATE flow that executes production-style test programs against a SystemC/SystemC-AMS virtual DUT before first silicon. In an Infineon ASIC case study, the same test program was run on the virtual ATE and later on a Teradyne UltraFLEX system, exposing the same register-test error; the authors report that this enabled test-program checks months earlier than the conventional flow.
An Analog Devices-authored presentation reports power-aware RNM models used with UVM supply and interrupt agents and assertions. It describes validating models against schematics, scripting chip-top connectivity, and running RNM with RTL; the authors report finding isolation and sequencing bugs and closing coverage without mixed-signal co-simulation for those full-chip tests.
A Broadcom-authored paper reports a full-chip, coverage-driven constrained-random UVM environment for mixed-signal SoCs. It describes selectable analog abstraction through SystemVerilog user-defined nettypes, Verilog-AMS, transistor-level, or mixed views, with interface UVCs, scoreboards, assertions, checkers, and coverage reused across configurations; the authors also report analog-digital and schematic bug findings.
Intel of Canada authors report a UVM verification framework for a SerDes physical-media-attachment layer that spans fast, accurate, and AMS-mode behavioral models. The presented framework uses translator blocks between real and logic data, layered adapter sequences, common end-to-end checkers, and configurable NRZ/PAM4 stimulus, with the authors reporting reuse across model modes and improved verification of pre-emphasis and equalization behavior.
A DVCon 2019 paper by Roche Sequencing Solutions authors presents a structured SystemVerilog user-defined nettype with runtime port resolution and waveform-viewer support. In a SAR ADC case, the authors report 1,183.3 seconds for the referenced SPICE simulation versus 4.7 seconds for the real-number model and say the flow exposed an incorrect MSB capacitor-switch polarity.
A DVCon 2019 paper by Texas Instruments authors describes using a SystemVerilog user-defined EEnet to model voltage, current, and resistance loading in power-regulation verification. The UVM-based flow randomized supplies, loads, and system states, supported reusable DMS and AMS environments, and extended verification to loading effects that simple voltage-only real-number interfaces could not represent.
At DVCon Europe 2018, NXP and Infineon presented company practices for extending UVM into mixed-signal verification. NXP described analog/mixed-signal verification-component and UVC concepts and identified a need for flexible APIs between physical and signal layers, including a common interface for third-party VIP; Infineon presented its A-UVM analog extension with real-valued transactions, constrained-random stimulus, automated analog checks, waveform comparison, functional coverage, and an IGBT gate-driver application. The tutorial explicitly asked whether an Accellera UVM-AMS working group should be created, and Accellera later stated that DVCon Europe discussions resulted in creation of the proposed working group.
Toshi Kawashima's public professional profile dates the start of his Apple role as Manager, DMS (Digital Mixed-Signal) Design Verification to October 2018 and says he leads a team responsible for DMS and AMS verification and methodology work across mixed-signal LSI projects.
A DVCon 2018 paper by Infineon authors describes a meta-model-driven flow that automatically generates real-number models and UVM-MS testbench components. In its mixed-signal ADC case, the generated RNM ran in 4.5 seconds versus 74.1 seconds for the referenced VHDL model, and the generated testbench exposed a deadlock in the analog implementation.
An NXP-authored paper reports verifying an IEEE 802.3bw 100BASE-T1 PHY with one UVM environment extended to handle its analog interface. The environment adds analog source and probe components, error injection, and analog-domain coverage while retaining the digital UVM register-model environment; the authors demonstrate the approach on a released automotive Ethernet PHY.
An Analog Devices-authored paper reports verification of a 2.4 GHz BLE and proprietary-mode transceiver SoC using UVM RF agents, real-number models, randomized packet parameters and blockers, and full-system pads-to-RTL simulation. The paper also describes Veri-DSP, an internal flow that generated UVM block testbenches and integrated Python post-processing for DSP verification.
A Cadence-authored paper reports reusing a digital UVM environment for mixed-signal verification of a Type-C USB and SerDes design. It describes analog-parameter agents, scoreboards and checkers, and added functional coverage and verification-plan content; the evidence documents a vendor-authored methodology rather than customer adoption.
Two TI-authored 2017 papers report methods for analog and mixed-signal verification. One binds assertions directly to electrical ports in a schematic; the other applies support vector machines and active learning to adaptively explore process, voltage, and temperature space for coverage and worst-case conditions.
Dialog Semiconductor's Carsten Wegener, listed with PMIC Analog in Germering, presents a model-validation process for analog behavioral models used in event-driven chip-level mixed-signal verification. The paper argues that modeling requires an associated validation process and demonstrates the approach on a mixed-signal digital I/O buffer treated as a 1-bit DAC and ADC, using post-handoff model bugs and issues as one measure of model quality.
A DVCon 2016 paper by Analog Devices authors reports automatically generating schematic-consistent, high-fidelity real-number abstractions for mixed-signal SoC verification. The authors describe deployment across several ADI SoC tapeouts, detection of subtle design bugs, and circuit-simulation speedups greater than 1,000x while preserving the analog-function accuracy needed for the reported verification cases.
An Analog Devices-authored paper reports a block-level UVM constrained-random testbench run against both an SV-RNM behavioral model and the analog netlist. The same stimuli and checks provide one-to-one comparison, the tests can run in regular or nightly regressions, and the paper describes reusing the block-level agents in system-level verification.
A DVCon 2016 paper by Infineon's Silvia Strähle describes UVM-based verification of an automotive mixed-signal design with more than 1,000 requirements. The environment could exchange a VHDL behavioral model for a transistor-level netlist where needed and checked analog quantities and operating conditions including temperature, overcurrent, and overtemperature behavior.
An NXP-authored paper reports low-power mixed-signal IoT case studies using CPF power intent, assertions, formal and connectivity checks, and self-checking verification while moving a verification database through Verilog, wreal, and Verilog-AMS abstraction levels. The examples include PMU, brownout detector, and LDO behavior at full-chip scope. The paper identifies evaluating UVM as a next step rather than reporting UVM deployment.
A TI-authored paper proposes an Analog Coverage Collector through which analog designers mark internal schematic and device threshold information for use by chip-level verification engineers. The paper describes turning that information into top-level covergroups and coverage data to coordinate analog design and verification work.
A DVCon 2016 paper by Texas Instruments and Cadence authors reports applying Common Power Format power intent to a complex industrial mixed-signal SoC. The flow generated power-smart interface elements, matched results from the authors' traditional inherited-interface-element method, and reduced the reported setup time from several weeks to less than two days.
A joint FH Technikum Wien/Infineon Technologies Austria paper presented a bidirectional pre/post-silicon bridge for Infineon's mixed-signal verification flow. It used a common platform-independent human-readable scripting test description, implemented with Perl, while environment-specific interpreters mapped the same test intent into the AGENtiX SystemC simulation environment or the JAZZ/lab-instrument post-silicon environment.
A Cadence press release reports that Hitachi used Virtuoso AMS Designer with real-number modeling to simulate the entire design of a backplane signal-conditioner mixed-signal chip, reducing verification from days to 30 minutes. Cadence says Hitachi presented the design and RNM results at ISSCC 2015 on February 23; this is a vendor-published customer report.
A Bosch Sensortec and Cadence DVCon Europe paper reports extending an existing digital UVM verification environment to address analog and full-chip verification in one mixed-signal testbench. The paper describes the architecture and implementation of the reusable approach and explicitly identifies wreal as part of the methodology.
A DVCon 2015 paper by Hewlett-Packard authors describes extending a mature digital UVM testbench to next-generation SerDes mixed-signal verification. The methodology supports model swapping and progressive refinement, allowing early link-training and equalization verification with behavioral models and later integration of schematics without refactoring the testbench.
A DVCon 2015 paper by Xilinx authors describes a mixed-signal verification flow combining automatically generated netlist real-number models, Octave signal processing, and a UVM environment with random stimulus and coverage. In one reported analog-multiplexer case, handwritten model content was limited to 10% of modules and 4% of lines; the paper also reports direct Octave FFT integration running 1.58x faster than its file-based comparison.
An Istanbul Technical University seminar listing dated December 2, 2014 identifies Selcuk Talay of Dialog Semiconductor as AMS Toplevel Design and Verification Lead. The record establishes his publicly identified role at that time; it does not establish when the role began.
Two Analog Devices-affiliated 2014 papers report distinct deployments. The LMA team described its local organization's first heavily analog project staffed with dedicated DV engineers, using verification planning, self-checking and constrained-random testbenches, regressions, SPICE co-simulation, and SystemVerilog RNM. A Beijing ASSP team described UVM, assertions, real-number functional coverage, regression, and metric sign-off for a Cortex-M3 mixed-signal device.
Two Infineon DVCon 2014 papers describe an Analog UVM library for constrained-random analog transactions and automated comparison of analog behaviors. The model-validation flow uses an earth mover's distance implementation connected through SystemVerilog and C to convert waveform comparison into regression pass/fail results, reducing reliance on manual waveform inspection.
A DVCon 2014 paper by Infineon and Mentor Graphics authors reports applying UPF with RTL and SPICE content to power-aware mixed-signal verification of a tire-pressure-monitoring sensor SoC. The paper says the flow exposed power blackouts, sequencing errors, missing level shifters, and incorrect isolation polarity before gate-level verification.
A DVCon 2014 paper by STMicroelectronics and Mentor Graphics authors describes a verification-plan-driven equivalence-validation component that applies common tests to analog implementations and behavioral models, produces pass/fail results and waivers, and can be reused across projects. The paper reports use by ST's high-speed serial-links group across HDMI, USB, and D-PHY work and says it exposed functional, connectivity, and test-mode differences before models were delivered to SoC teams.
A DVCon 2014 paper by Texas Instruments, IIT, and Cadence authors compares connect-module and interface-element methods for analog/mixed-signal boundaries and describes automation for true supply sensitivity. The authors state that the methods were applied on several commercial mixed-signal SoCs and present practical tradeoffs and guidelines for automating supply-sensitive interface handling.
A DVCon 2014 paper by Texas Instruments authors reports a specification-driven flow that automatically generated mixed-signal testbench elements, RTL, assertions, and results infrastructure. In a power-management case study, the authors say the approach enabled analog IP-level SPICE simulation almost three months earlier than comparable prior executions within an approximately twelve-month development cycle.
Two TI-authored 2014 papers report mixed-signal SoC verification using higher-level analog abstractions. One describes wreal models and digital-regression reuse on a 45 nm secure SoC, including functional and design-for-test integration issues; the other describes a UVM environment for an RF transceiver SoC using wreal and Verilog-AMS models, constrained-random stimulus, assertions, coverage, and a MATLAB reference-model checker.
A DVCon 2013 paper by IBM and Cadence authors reports that IBM created and deployed Verilog-AMS wreal models on a mixed-signal project. The authors describe correlation against circuit-level simulations, approximately 40x simulation speedup for a representative case, and digital mixed-signal regressions that could run overnight.
At DVCon 2012, Cadence's Prabal K. Bhattacharya, Intel's Scott Little, and coauthors proposed extending SystemVerilog coverpoints to accept real-valued data for analog and mixed-signal functional coverage. The work reports a prototype following a year-long Cadence research-and-development effort and addresses real-valued bins and ranges, range precision, coverage scoring, cross coverage, and remaining floating-point issues. The affiliations are specific to this paper and do not imply methodology transfer between the companies.
A DVCon 2012 paper by Maxim Integrated and Cadence authors reports applying a UVM-MS methodology to a complex noise-cancelling receiver SoC. The case study describes an executable verification plan, wreal behavioral models, constrained-random stimulus, assertions, functional coverage, and verification closure supporting first-pass success.
An Infineon-authored paper described linking Markov-based mixed-signal constrained-random test generation to an Executable Verification Plan (XVP) so test cases could be transferred to Cadence simulators and MATLAB/Simulink for simulation and to PXI and ATE for post-silicon verification. The paper also reports applying generated tests on mixed VHDL-AMS/Verilog models and post-silicon PXI/ATE systems and identifying mixed-signal design issues.
Tomokatsu Mizukusa's public professional profile describes his 2011–2014 Renesas role as developing EDA and design methodology for mixed-signal and analog systems. It specifically reports MCU and SoC whole-chip mixed-signal functional and connectivity verification using Verilog Wreal, along with SystemVerilog discrete-real modeling and UVM-AMS.
At FMCAD 2011, John Havlicek and Freescale Semiconductor's Scott Little presented syntax and semantics for realtime regular expressions that extend SystemVerilog Assertion-style regular expressions to describe continuous-time analog and mixed-signal properties. The paper says the work was influenced by the Accellera analog-assertions effort; it does not claim an internal Freescale deployment.
A 2011 DVCon paper by LSI and Cadence authors describes real-number models for mixed-signal verification of a hard-disk-drive preamplifier and reports roughly 24x speedup over the referenced SPICE simulation with about 0.3% gain inaccuracy. A later Cadence-authored report describes LSI applying the models in mixed-signal SoC verification, reporting roughly 600x speedup, 95% accuracy, full functional coverage, and no functional bugs in first silicon. These performance and outcome statements retain their respective paper and vendor-report modalities.
A DVCon 2011 paper by Medtronic's Gregg Sarkinen reports applying an integrated analog/digital verification environment to a mixed-signal medical-device IC prototype. The flow used a verification plan, constrained-random stimulus, checkers, reusable models, and coverage closure. The paper reports more than 3,000 mixed-signal simulations with automated pass/fail results.
A 2010 journal paper coauthored by Freescale Semiconductor's Scott Little proposes automatically generating abstraction models from transistor-level simulation traces for formal verification and system simulation. The paper demonstrates the approach on a switched-capacitor integrator and a PLL phase detector and evaluates how the generated models reproduce the observed circuit behaviors.
Intel authors report a full-chip mixed-signal validation strategy that represents top-level analog ports as real-valued signals, reuses a SystemVerilog real-port testbench from top-down development through bottom-up implementation, and selectively replaces analog blocks with behavioral models. The paper says the tool-independent method was applied to three successive Intel SoC projects with open- and closed-loop mixed-signal networks and includes behavioral-model equivalence checking.
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