Analog Devices authors report UPF-based low-power verification in a digital mixed-signal flow

A DVCon 2021 paper by Analog Devices authors describes combining SystemVerilog real-number models, RTL, and Unified Power Format for low-power digital mixed-signal verification. The environment checked supplies, isolation, level shifting, and power sequencing, and the authors report that it exposed a power-domain defect involving memory built-in self-test and a test-data register.