ADI authors report automated SystemVerilog connectivity-test generation for a mixed-signal SiP

Analog Devices authors report a Python flow that generates SystemVerilog connectivity tests from a human-readable spreadsheet for system-in-package analog/mixed-signal verification. On the reported Pin Driver ATE project, it generated checkers for more than 2,000 interface pins and completed almost 600 checks; the authors report reducing test creation from days to minutes while retaining reusable, hierarchy-aware checks.