Analog Devices and university authors evaluate an AI-generated SystemVerilog model in an AMS workflow
A DVCon Europe 2024 paper by University College Cork and Analog Devices authors evaluates an experimental workflow that learns from analog simulation data and generates a SystemVerilog inference model. For an RC demonstration, the paper reports 16 seconds for analog simulation, 15 seconds for a non-AI SystemVerilog model, and 14 seconds for the AI model, and says the approach was evaluated at ADI with promising results. It does not establish production deployment.
Evidence
A New Approach to Integrating AI into Analog/Mixed-Signal Verification Workflow ↗
DVCon's record identifies the University College Cork and Analog Devices experimental AI-assisted AMS verification paper.
A New Approach to Integrating AI into Analog/Mixed-Signal Verification Workflow — paper ↗
The paper describes the learned SystemVerilog model, RC timing comparison, and experimental evaluation wording.