Arago posts mixed-signal verification role for its optical/CMOS computing SoCs

Arago posted a senior mixed-signal verification role in Paris or Tel Aviv to own methodology and verification of digital-to-analog interfaces in its SoCs. The responsibilities include block, subsystem, and SoC environments, behavioral and real-number models, assertions, coverage, and sign-off. SystemVerilog and UVM or an equivalent methodology are requested; SystemVerilog RNM, wreal, and Verilog-AMS appear among preferred experience.