Cadence advertises SystemVerilog RNM model qualification against schematics and analog assertions

Cadence posted Mixed-Signal Systems and Verification Engineer R55855. The assigned work develops accurate, simulation-efficient SystemVerilog analog/RF behavioral models, verifies them against analog schematics, integrates them with RTL, and checks analog functionality against specifications using testbenches, scenarios and assertions. Qualifications name RNM, UDN/UDT/UDR, wreal, Verilog-AMS and analog assertion-based verification. Modeling and verification results are documented for formal review. This records an engineering hiring mandate rather than a product release or a reported customer deployment.