Cirrus Logic role covers mixed-signal verification strategy, reusable testbenches, and RNM models

Cirrus Logic posted a Mixed Signal Modelling and Verification Engineer role to lead verification activities and help evolve company methodology for complex mixed-signal ICs. The position covers verification strategy, reusable testbenches, real-number modeling, SystemVerilog user-defined types and Verilog-AMS, hands-on modeling and simulation, and desired experience in UVM, assertions, functional and code coverage, and CPF or UPF power-aware verification. This is evidence of a hiring mandate, not proof that every listed practice is deployed in every project.