Cirrus Logic and MathWorks authors report reusing system models in mixed-signal verification
A DVCon U.S. 2025 paper by Cirrus Logic and MathWorks authors describes generating SystemVerilog DPI-C components from system-level models for reuse in mixed-signal verification. A reported test ran in 30 seconds with DPI-C versus 51 seconds with a user-defined nettype and 54 seconds with Verilog-AMS. The paper also contrasts two projects whose closed-loop verification began 18 and 43 weeks after RTL availability; those project timings are not presented as a controlled comparison.
Evidence
Reuse of System-Level Circuit Models in Mixed-Signal Verification ↗
DVCon's record identifies the Cirrus Logic and MathWorks model-reuse paper.
Reuse of System-Level Circuit Models in Mixed-Signal Verification — paper ↗
The paper details generated DPI-C reuse, the reported runtime comparison, and the distinct project timelines.
Reuse of System-Level Circuit Models in Mixed-Signal Verification ↗
MathWorks' technical article presents the Cirrus Logic collaboration and summarizes the model-generation and reuse workflow.