Cirrus Logic advertises a Fall co-op for SV-RNM, user-defined types and audio ASIC verification
Cirrus Logic's company account advertised a Fall 2026 Mixed Signal Modeling & Verification Engineer co-op in Austin on May 2. The preserved job description assigns top-down SystemVerilog model development and validation, AMS/UVM verification planning for audio-processing ASICs, behavioral models using SV-RNM, SystemVerilog user-defined types and Verilog-AMS, schematic abstraction, and regression and flow support. The advertised student placement lasts 12–14 weeks. The Event date is the employer's public announcement, not the Fall work term or an inferred first posting date.
Evidence
Cirrus Logic: Fall 2026 Mixed Signal Modeling & Verification co-op announcement ↗
The employer's public announcement identifies the role and Austin location. Its JSON-LD datePublished is May 2, 2026 at 11:24 UTC.
Dice: Cirrus Logic Fall 2026 Co-Op - Mixed Signal Modeling & Verification Engineer
Indexed employer-description copy supplies the audio ASIC, AMS/UVM, SV-RNM/SV-UDT/Verilog-AMS, schematic-abstraction and regression duties. The direct page returns HTTP 410 when checked; this is a historical recruiting record.