Cirrus Logic role links SV-RNM models to analog design, UVM verification, HW/SW validation, and AMS-UVM reuse

As observed on September 14, 2026, Cirrus Logic's official careers site listed an Analog Mixed Signal Modeling & Verification Engineer role for Austin, Chandler, and Greensboro. The posting says the team generates and verifies analog circuit equivalent models for analog design, UVM verification, and HW/SW validation; develops SV-RNM, SV-UDT, and Verilog-AMS models; builds DMS and AMS test plans and platforms; supports chip-level integration and regression debug; and works with UVM verification engineers so verification components are used in an AMS-UVM flow. It also names collaboration spanning pre-silicon verification and post-silicon validation plus automation for design, verification, and modeling. The public page does not expose a reliable creation date, so this Event records the observation date rather than claiming when the role was first posted.