Cirrus Logic role links SV-RNM models to analog design, UVM verification, HW/SW validation, and AMS-UVM reuse
As observed September 14, Cirrus Logic listed an Analog Mixed Signal Modeling & Verification Engineer role for Austin, Chandler and Greensboro. It assigns equivalent models reused across analog design, UVM verification and HW/SW validation; SV-RNM, SV-UDT and Verilog-AMS; DMS/AMS plans and platforms; regression debug; and verification-component reuse in AMS-UVM. The original UL-01 page is now unavailable. Related current UL-02 role, observed October 25, repeats those duties and adds architectural exploration and design-partitioning input. The postings establish a reusable-model methodology hiring mandate, not measured deployment. No reliable first-publication date is exposed, so the September observation date remains.
Evidence
Cirrus Logic Careers: Analog Mixed Signal Modeling & Verification Engineer (UL - 01)
Previously verified September 14 description covers equivalent-model reuse, SV-RNM/SV-UDT/Verilog-AMS, AMS-UVM, chip integration and regression debug. The original UL-01 page returns HTTP 404 on October 25; this is not a fresh full-text review.
Cirrus Logic Careers: current job listing ↗
Current official index lists related UL-02 modeling and GNEG4 mixed-signal modeling/verification roles. The public listing does not provide a reliable creation date.
Cirrus Logic Careers: Analog Mixed Signal Modeling Engineer (UL - 02) ↗
Current official posting and public Lever response repeat equivalent-model reuse across design, UVM and HW/SW validation, SV-RNM/SV-UDT/Verilog-AMS and AMS-UVM component reuse, with architectural exploration and partitioning responsibilities. Observed October 25; first publication is unconfirmed.