Cirrus Logic engineer describes a top-down flow spanning SystemVerilog RNM, DMS, and chip-level AMS verification

A TechWorks presentation by Cirrus Logic engineer Gautham Sathyan describes a top-down mixed-signal verification approach spanning early architectural modeling, analog/digital boundary definition, DMS bring-up, SystemVerilog real-number models for lower-level analog cells, and chip-level AMS simulation. His public event biography identifies him with Cirrus Logic's Newbury Mixed-Signal Modeling and Verification group.