EVAS v0.8.7 publishes an event-driven simulator for Verilog-A behavioral circuit models

The evas-sim v0.8.7 release publishes an open-code, event-driven simulator for voltage-based Verilog-A behavioral models. Its documented scope includes ADC/DAC examples, comparators, clocks, control and calibration logic. It supports a behavioral subset rather than a complete Verilog-AMS implementation, and does not provide a KCL/KVL or MNA circuit solver. July 28 dates this version release, not necessarily the initial publication of the project; no corporate affiliation is inferred.