SV-MSI update links mixed-net interoperability to SystemVerilog-2028, SV-AMS, and UVM-MS

The DVCon Japan 2026 SystemVerilog Mixed-Signal Interface Types BoF describes Accellera work to standardize connections among dissimilar SystemVerilog net types, including seamless logic-to-nettype/RNM connections that tools have historically handled with ad hoc mechanisms. The program says this foundation is expected to be incorporated into IEEE 1800/SystemVerilog-2028 and that the resulting semantics are also intended for use by the Accellera SystemVerilog-AMS and UVM-MS efforts. This records the publicly stated standards direction, not a completed IEEE revision or released SV-MSI standard.