SV-MSI update links mixed-net interoperability to SystemVerilog-2028, SV-AMS, and UVM-MS

The DVCon Japan program lists an SV-MSI update by Abhijit Madhu Kumar, identified as a Cadence Principal Solutions Engineer. It describes proposed interoperability between logic nets and RNM/nettype representations toward IEEE 1800-2028, alongside the SV-AMS and UVM-MS roadmap. These are presented proposals and roadmap directions, not already published standard requirements or released functionality.