Eliyan roles establish AMS verification and schematic-derived RNM for chiplet SerDes PHYs
Eliyan posted verification roles that pair organization-level AMS methodology with hands-on SerDes model ownership. The director role covers RNM, SV-AMS co-simulation, behavioral-model integration, UCIe and Ethernet PHYs, PLLs, CDRs, and SerDes analog front ends; the staff role develops SystemVerilog RNM directly from schematics and verifies those models with UVM tests and assertions. These are public hiring mandates, not evidence that every flow was already deployed.
Evidence
Eliyan Careers API: Director of Design Verification ↗
The official Lever API record exposes a February 16, 2026 creation timestamp and describes AMS flows, RNM, SV-AMS co-simulation, behavioral-model integration, and PHY verification leadership.
Eliyan Careers API: Staff Verification Engineer – AMS modeling ↗
The official Lever API record exposes a May 20, 2026 creation timestamp and describes hands-on SerDes SystemVerilog RNM development from schematics, model ownership, UVM tests, and assertions.