Enphase lists processor-verification roles integrating SV-RNM with analog power-stage closed-loop verification

Enphase listed Staff and Sr. Staff processor-verification roles for a custom RISC-V VLIW processor used in energy-conversion control. The descriptions combine RTL simulation, SystemVerilog Real Number Modeling, analog simulation platforms such as NL5, C/C++ power-conversion and plant models, and Python automation in system-level mixed-signal verification, with validation of closed-loop behavior, deterministic timing, fault handling, and interactions between digital control algorithms and analog power stages.