Hewlett-Packard authors report a digital-centric mixed-signal methodology for SerDes verification
A DVCon 2015 paper by Hewlett-Packard authors describes extending a mature digital UVM testbench to next-generation SerDes mixed-signal verification. The methodology supports model swapping and progressive refinement, allowing early link-training and equalization verification with behavioral models and later integration of schematics without refactoring the testbench.
Evidence
Advanced Digital-Centric Mixed-Signal Methodology ↗
The Hewlett-Packard paper describes reuse of a digital UVM environment, progressive model refinement, and behavioral-to-schematic integration for SerDes verification.