Cadence reports Hitachi used RNM for full-design verification of a mixed-signal backplane signal conditioner
A Cadence press release reports that Hitachi used Virtuoso AMS Designer with real-number modeling to simulate the entire design of a backplane signal-conditioner mixed-signal chip, reducing verification from days to 30 minutes. Cadence says Hitachi presented the design and RNM results at ISSCC 2015 on February 23; this is a vendor-published customer report.
Evidence
日立、ケイデンスのVirtuoso AMS Designerを採用し、ミックスシグナル・チップの検証時間を短縮 ↗
Cadence's vendor-published customer release reports Hitachi's full-design RNM simulation, the days-to-30-minutes reduction, and the February 23 ISSCC presentation.