HMT presents a Polarion-to-SystemVerilog workflow for mixed-signal ASIC verification
At User2User Europe 2026, HMT Microelectronic's Vincent Camus presented a requirement-driven mixed-signal ASIC verification workflow. The public session description connects Siemens Polarion requirements to VIP-based SystemVerilog testbenches, SVA assertions and chip-level mixed-signal validation. It describes automated pass/fail reporting and centralized model hierarchy, simulation configuration and version management. Simulator independence and functional-safety compliance are claims in the presentation description; no third-party certification or quantified verification result was established.
Evidence
Siemens User2User Europe 2026: HMT session description ↗
Official session detail, linked from the Functional Design & Verification catalog, identifies HMT, Vincent Camus and May 12, 2026. Its public description specifies Polarion, SystemVerilog, SVA, mixed-signal validation and traceability.
Verification Academy: Automated requirement-driven, SystemVerilog-based verification workflow for mixed-signal ASICs ↗
Public abstract corroborates the workflow and affiliation. The member-only recording was not reviewed; the Event date comes from the official conference session, not the page update.