Intel authors report a real-valued full-chip mixed-signal validation strategy
Intel authors report a full-chip mixed-signal validation strategy that represents top-level analog ports as real-valued signals, reuses a SystemVerilog real-port testbench from top-down development through bottom-up implementation, and selectively replaces analog blocks with behavioral models. The paper says the tool-independent method was applied to three successive Intel SoC projects with open- and closed-loop mixed-signal networks and includes behavioral-model equivalence checking.
Evidence
Strategy and Environment for SOC Mixed-Signal Validation: A Case Study ↗
The DVCon archive dates the Intel-authored paper to 2010 and identifies it as a full-chip mixed-signal validation case study.
Strategy and Environment for SOC Mixed-Signal Validation: A Case Study — paper ↗
The paper describes the real-valued SystemVerilog port strategy, behavioral-model substitution and equivalence checking, and reported application to three successive Intel SoC projects.