Intel authors report a UVM framework for SerDes mixed-signal behavioral-model verification
Intel of Canada authors report a UVM verification framework for a SerDes physical-media-attachment layer that spans fast, accurate, and AMS-mode behavioral models. The presented framework uses translator blocks between real and logic data, layered adapter sequences, common end-to-end checkers, and configurable NRZ/PAM4 stimulus, with the authors reporting reuse across model modes and improved verification of pre-emphasis and equalization behavior.
Evidence
Translating and Adapting to the 'real' world: SerDes Mixed Signal Verification using UVM ↗
The DVCon archive dates the Intel of Canada paper to 2019 and identifies Akhila Madhu Kumar and Karl Herterich as its authors.
Translating and Adapting to the 'real' world: SerDes Mixed Signal Verification using UVM — paper ↗
The paper details the behavioral-model modes, real-to-logic translators, UVM adapter sequences, NRZ/PAM4 configuration, and reported verification results.