Intel job posting seeks mixed-signal verification leadership for PLL and FLL clock IP

Intel posted a Senior Pre-Silicon Verification Engineer role describing functional verification of PLL and FLL clock-generator IP, SystemVerilog/UVM environments, tests, assertions and coverage, and leadership of mixed-signal validation using AMS simulations to identify and root-cause schematic bugs. This is evidence of a public hiring mandate for clock-IP verification, not proof of the completion or deployment of a particular verification flow.