Marvell Córdoba internship pairs SystemVerilog analog models with SPICE comparison and co-simulation

Marvell posted Analog Modeling & Testing Engineer Intern 2602068 for its Central Engineering team at the Córdoba design center. The training mandate includes modeling analog circuits in SystemVerilog, comparing SV and SPICE simulations, running digital/analog co-simulation and improving analog-IC design flows, alongside Python/firmware-based circuit testing. These are advertised assignments rather than a report of completed work. The named Córdoba modeling program is distinct from the Singapore amplifier-verification internship.