Marvell presents an AI-assisted RTL/spec-to-cycle-true-C bit-match flow for TX DAC calibration verification

The official DVCon Taiwan 2026 program lists a Marvell presentation by Tiger Chen titled 'From RTL+Design Spec to Cycle-True C: An AI-Assisted Bit-Match Verification Flow for TX DAC CAL'. The public program establishes an AI-assisted verification flow whose stated inputs are RTL and a design specification and whose stated reference artifact is a cycle-true C model for TX DAC calibration bit matching. Without retained paper or slides, this Event does not assert a particular generation method, accuracy result, or production-deployment scope.