Marvell AMS IP role spans reusable verification for SerDes, DDR, die-to-die, and PHY interfaces
Marvell posted a Senior Staff Engineer role in its Central Engineering AMS IP team with end-to-end verification ownership for SerDes and other AMS or mixed-signal IP across 5 nm, 3 nm, and 2 nm nodes. The mandate covers calibration, link training, power modes, analog-digital and firmware interactions, coverage, regression, sign-off, and reusable automation using SystemVerilog and UVM. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.
Evidence
Marvell Careers: Senior Staff Engineer — AMS IP Verification (2601686) ↗
The official Marvell Workday record exposes a June 9, 2026 start date and describes the Central Engineering team's interface scope, end-to-end verification ownership, UVM methodology, sign-off, and reusable infrastructure responsibilities.