Maxim and Cadence authors report UVM-MS verification of a complex mixed-signal SoC
A DVCon 2012 paper by Maxim Integrated and Cadence authors reports applying a UVM-MS methodology to a complex noise-cancelling receiver SoC. The case study describes an executable verification plan, wreal behavioral models, constrained-random stimulus, assertions, functional coverage, and verification closure supporting first-pass success.
Evidence
From Spec to Verification Closure: Applying UVM-MS for First-Pass Success to a Complex Mixed-Signal SoC ↗
DVCon's record identifies the Maxim and Cadence case study on UVM-MS verification of a complex mixed-signal receiver SoC.
From Spec to Verification Closure — paper ↗
The paper details the executable plan, wreal models, constrained-random tests, assertions, coverage, and reported first-pass outcome.