Roche Sequencing authors report complex SystemVerilog UDNs for mixed-signal verification
A DVCon 2019 paper by Roche Sequencing Solutions authors presents a structured SystemVerilog user-defined nettype with runtime port resolution and waveform-viewer support. In a SAR ADC case, the authors report 1,183.3 seconds for the referenced SPICE simulation versus 4.7 seconds for the real-number model and say the flow exposed an incorrect MSB capacitor-switch polarity.
Evidence
Novel Mixed-Signal Verification Methodology Using Complex UDNs ↗
DVCon's record identifies the Roche Sequencing Solutions paper on complex SystemVerilog user-defined nettypes.
Novel Mixed-Signal Verification Methodology Using Complex UDNs — paper ↗
The paper details the structured UDN, runtime resolution, GUI support, SAR ADC timing comparison, and reported polarity defect.