Semtech lists cross-site roles for block-to-chip mixed-signal IC verification

Semtech posted related senior verification roles in San Diego and Hyderabad covering verification plans for mixed-signal IP, subsystems, and full ICs; SystemVerilog and UVM testbenches; RTL, gate-level, and AMS simulation; constrained-random stimulus; assertions, functional and code coverage; continuous integration and regression automation; and desired SV-RNM or Verilog behavioral modeling. The San Diego role is tied to low-power sensing ICs with ADCs. These postings evidence a hiring mandate, not completed deployment.