Silicon Labs posts AMS verification role for RNM-based IP and SoC sign-off

Silicon Labs posted a Staff or Senior Staff AMS Verification role whose description covers functional, performance, and power sign-off for next-generation IP and SoCs using RNM models. The role includes Verilog-D, Verilog-A or Verilog-AMS behavioral modeling, block- and chip-level verification, self-checking regressions, model validation, silicon correlation, and SystemVerilog/UVM experience. This is evidence of a public hiring mandate, not proof that every listed method was already deployed.