Synopsys introduces a 2026 R1 photonic Verilog-A model-generation flow

Synopsys announced the Ansys 2026 R1 release with a photonic circuit-design flow connecting OptoCompiler and Lumerical. The release notes describe CML Compiler generating photonic Verilog-A models for PrimeSim HSPICE/SPICE from component data including scattering parameters produced by FDTD, MODE and Multiphysics, enabling electro-optical circuit simulation in OptoCompiler. This records the announced circuit-model flow, rather than a device compact model or a later patch release.