Synopsys posts an AMS verification role describing reusable models and monitors across IP families

Synopsys posted a Hyderabad senior staff role to own AMS verification plans, environments, coverage, and sign-off for mixed-signal IP blocks and subsystems. Its description combines SystemVerilog/UVM with Verilog-A and Verilog-AMS models and mixed-signal simulators, and calls for behavioral models and monitors to be reused across IP families. Requested circuit knowledge includes bias circuits, regulators, PLLs, ADCs, and DACs. A September 28 posting repeats this IP-verification mandate and is grouped with the September 3 listing.