TYLsemi's retained IVR role links Verilog-A/RNM models, co-simulation and power-control checks
An employer-attributed TYLsemi LinkedIn role observed October 25, 2026 describes high-current integrated-voltage-regulator verification. It assigns Verilog-A and SystemVerilog RNM models for power stages, integrated inductors, the power-delivery network and analog blocks; analog/digital co-simulation; and testbenches for load transients, loop stability, ripple, protection and startup/shutdown. Duties also include PVT/Monte Carlo regressions and simulation-to-lab correlation. The first publication date is unconfirmed, so this Event uses the observation date of the retained advertisement, not a claimed October hiring launch.
Evidence
TYLsemi employer LinkedIn: Senior Mixed-Signal Verification Engineer - Power Management ICs ↗
Retained full employer description was checked October 25, 2026. It names high-current IVRs, Verilog-A/SystemVerilog RNM models, simulator combinations, control-loop checks and lab correlation. No reliable original datePosted was exposed; relative ages are not used.
TYLsemi employer LinkedIn: related retained IVR verification listing ↗
Related retained copy repeats the IVR modeling and verification duties and is marked no longer accepting applications. Grouped with the same mandate; this does not establish a separate recruitment event or current vacancy.