Ulkasemi and Designer's Guide authors report a UVM full-chip flow with analog behavioral models
A DVCon U.S. 2024 paper by Ulkasemi and Designer's Guide Consulting authors describes validating analog behavioral models against schematics and then integrating them into a full-chip UVM environment. The paper discusses complementary AMS and digital mixed-signal tradeoffs and presents the method as a reusable verification architecture, not as proof that behavioral abstraction replaces circuit-level verification.
Evidence
Advanced UVM-Based Chip Verification Methodologies with Full Analog Functionality ↗
The official proceedings record identifies Simul Barua with Ulkasemi, Henry Chang with Designer's Guide Consulting, and the March 6, 2024 presentation.
Advanced UVM-Based Chip Verification Methodologies with Full Analog Functionality — paper ↗
The paper describes schematic validation of analog behavioral models and their integration into a full-chip UVM verification environment.