Ayar Labs listed related Bengaluru analog/mixed-signal modeling and verification roles. Their descriptions call for capturing significant first- and second-order circuit effects in SystemVerilog RNM, comparing models with schematics, signing off models, and integrating them into full-chip digital verification. The senior staff role adds model ownership through the product lifecycle. The postings name UVM and Verilog-AMS and include wreal/EEnet and optical simulation tools among preferred experience.