A Google careers posting for a senior verification engineer in Israel lists ownership of verification for 112G and 224G high-speed PHY signal-processing designs. The role calls for RNM or SystemVerilog-AMS flows across analog-front-end and digital-DSP boundaries, with specialized testbenches for adaptive algorithms such as LMS and Zero-Forcing covering stability, convergence time, and tracking across process-voltage-temperature corners. It also calls for link bring-up, auto-negotiation and error-recovery tests and for channel loss, crosstalk, and reflections to be represented in the DV environment. This is evidence of a public hiring requirement, not proof of a deployed internal methodology.