Melexis posted Bevaix internship/master's-thesis project 3932 for automotive sensor IC mixed-signal design verification and system integration. The six-month 2027 project assigns Claude Code workflows, test-case development, and automated classification and root-cause analysis of simulation/verification failures. SystemVerilog/Verilog is essential; UVM is beneficial. Optional work compares Chipstack with Claude. Deployment into real projects and efficiency improvements are expected project results, not demonstrated outcomes. The retained official timestamp is October 5 at 20:00 UTC; 2027 identifies the work cohort.