AMD posts a PMIC verification role linking analog-macro RNM, full-SoC tests, and silicon correlation

AMD posted a Rochester ASIC Design Verification Engineer role to own verification strategy and coverage closure for mixed-signal power-management IP. Responsibilities include full-SoC SystemVerilog/UVM tests, firmware/RTL co-simulation, analog-macro RNM bring-up and correlation with analog behavior, and relating post-silicon behavior to pre-silicon tests. Preferred experience names wreal, nettype real, and Verilog-AMS.