Aug 18, 2026AMD posts a PMIC verification role linking analog-macro RNM, full-SoC tests, and silicon correlationAMD posted a Rochester ASIC Design Verification Engineer role to own verification strategy and coverage closure for mixed-signal power-management IP. Responsibilities include full-SoC SystemVerilog/UVM tests, firmware/RTL co-simulation, analog-macro RNM bring-up and correlation with analog behavior, and relating post-silicon behavior to pre-silicon tests. Preferred experience names wreal, nettype real, and Verilog-AMS.
Jun 30, 2026AMD job posting seeks leadership for complex PLL mixed-signal verificationAMD posted a role for a silicon design engineer that describes leading verification of complex PLLs across RTL, gate-level, and analog/mixed-signal simulation, with UVM, coverage, co-simulation, planning, and technical leadership responsibilities. This is evidence of a public hiring mandate, not proof that every requested flow was already deployed across AMD.
2026AMD job posting seeks an AI-assisted verification strategy for a mixed-signal IP organizationAn Indeed-hosted copy of an AMD Fellow-level pre-silicon verification posting describes a mixed-signal IP organization and asks the role to integrate UVM with real-number modeling and AMS co-simulation, modernize regression, debug, and coverage analytics, and define an AI-assisted strategy spanning intelligent test generation, regression triage, and coverage-gap prediction. This is evidence of a public hiring mandate, not proof that these methods were already deployed across AMD.
2024AMD authors automate analog-boundary delay annotation for mixed-signal gate simulationsAMD authors report a flow that reads a Standard Delay Format file, generates a SystemVerilog specify block for analog-boundary IOPATH delays, and instantiates it in an analog behavioral model for back-annotated mixed-signal gate simulation. In two reported IP cases with about 40 analog-interface signals, the automated approach reduced manual effort and annotated all paths; the paper also reports uncovering a constraint issue in one project after complete delay annotation.
2015Xilinx authors report combining generated real-number models, Octave, and UVM for AMS verificationA DVCon 2015 paper by Xilinx authors describes a mixed-signal verification flow combining automatically generated netlist real-number models, Octave signal processing, and a UVM environment with random stimulus and coverage. In one reported analog-multiplexer case, handwritten model content was limited to 10% of modules and 4% of lines; the paper also reports direct Octave FFT integration running 1.58x faster than its file-based comparison.