AMD job posting seeks leadership for complex PLL mixed-signal verification
AMD posted a role for a silicon design engineer that describes leading verification of complex PLLs across RTL, gate-level, and analog/mixed-signal simulation, with UVM, coverage, co-simulation, planning, and technical leadership responsibilities. This is evidence of a public hiring mandate, not proof that every requested flow was already deployed across AMD.
Evidence
AMD Careers requisition 87581 ↗
Official AMD requisition 87581, posted June 30, 2026, describes the complex-PLL verification leadership scope across RTL, gate-level, AMS, UVM, coverage, and co-simulation.