ams OSRAM authors report a DMS flow for early full-chip power estimation
An ams OSRAM DVCon Europe 2025 paper reports using digital mixed-signal simulation for early full-chip power estimation. Analog-model states map to quiescent-current values inside a central UVM testbench spanning multiple rails and IP blocks. The authors present the method as an early-estimation aid alongside detailed verification, not as a replacement for analog sign-off.
Evidence
Early Power Estimation of Mixed-Signal ICs Using Digital Mixed-Signal Simulation ↗
The full DVCon Europe 2025 paper describes the analog-state-to-quiescent-current model, central UVM testbench, multi-rail application, and its bounded early-estimation role.
DVCon Europe 2025 proceedings program ↗
The official proceedings program dates the ams OSRAM presentation to October 15, 2025.