Analog Port and Siemens report a UVM-based chiplet mixed-signal verification flow
At DAC 2026, Analog Port and Siemens EDA authors described a top-down mixed-signal verification methodology for a 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface. The flow extends a UVM-based digital verification environment into the mixed-signal domain, using SPICE simulation for critical analog blocks and high-performance digital simulation for the broader system. The authors report up to 26x memory savings and more than 3x performance gain for the presented RX and TX simulations; these are case-specific presentation results.
Evidence
Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification ↗
The official DAC 2026 record identifies the Analog Port and Siemens authors, July 29 presentation, UVM-based top-down methodology, selective SPICE/digital partitioning, 32 Gbps 16-TX/16-RX interface, and reported up-to-26x memory and greater-than-3x performance results.
How Siemens Symphony Pro enabled AnalogPort to verify complex chip interfaces ↗
Siemens' vendor-authored white paper separately documents the presented methodology's UVM extension, SPICE treatment of critical analog blocks, digital simulation of the broader system, and the 32 Gbps 16-transmit/16-receive full-duplex interface.