Siemens EDA

Siemens published a technical overview of Symphony Pro's Mixed-Signal Visualizer for AMS verification. It describes linked hierarchy, netlist, source, and variable views; generated schematics for checking connectivity and port mapping; and paired analog/digital signal representations for inspecting A2D/D2A conversion and boundary elements.

Jul 29, 2026

Analog Port and Siemens report a UVM-based chiplet mixed-signal verification flow

At DAC 2026, Analog Port and Siemens EDA authors described a top-down mixed-signal verification methodology for a 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface. The flow extends a UVM-based digital verification environment into the mixed-signal domain, using SPICE simulation for critical analog blocks and high-performance digital simulation for the broader system. The authors report up to 26x memory savings and more than 3x performance gain for the presented RX and TX simulations; these are case-specific presentation results.

Jul 29, 2026

EKEPOWER and Siemens describe variation-aware verification and trimming for mixed-signal printing ICs

A DAC 2026 abstract by EKEPOWER's Irving Hsu and Siemens' Lih-Jen Hou describes a Solido flow combining transient, RF, and mixed-signal analysis for printing ICs with motor/printhead drivers, timing references, and RF sensors. The authors report up to 7.6x speed improvement over their conventional methods and an AI-assisted trimming flow that reduces top-level voltage variation; these are presentation-reported results.

Jul 29, 2026

Microchip and Siemens authors report selective-SPICE digital-top verification with RTL and UPF

A Microchip and Siemens DAC 2026 presentation reports a digital-on-top mixed-signal flow combining selected SPICE blocks with RTL and UPF power intent. The presentation describes AI-accelerated Solido analysis and reports more than 22× acceleration for the presented case. This preserves the customer/vendor presentation modality and does not imply the result applies to every Microchip design.

Jul 28, 2026

Microchip and Siemens report full-chip AMS verification for FPGA I/O PVT calibration

At DAC 2026, Microchip and Siemens authors described full-chip analog mixed-signal verification of FPGA I/O PVT calibration spanning distributed I/O banks. The presented calibration combines a SAR-based digital block with analog circuitry that manages reference currents and voltages. The authors report that Siemens Symphony Pro reduced simulation time by about 3x and memory usage by about 2-3x while supporting regression across multiple I/O standards and extreme PVT conditions; these are presentation-reported results for the described case.

Jun 9, 2026

Siemens publishes a Ubitium PLL case connecting RNM to Veloce Strato emulation

Siemens published a Ubitium case-study abstract describing real-number models of analog blocks integrated into Veloce Strato hardware emulation. Its PLL example operates in a RISC-V system environment, and the abstract reports acceleration while retaining correlation with traditional simulation.

Feb 20, 2026

Siemens publishes an AnalogPort mixed-signal die-to-die verification case study

A Siemens EDA customer story reports that AnalogPort applied UVM to a 32 Gbps full-duplex die-to-die interface with 16 transmitters and 16 receivers. The story describes using Symphony Pro with Questa digital simulation and Solido SPICE simulation, automated boundary insertion, selective data recording, and MS Visualizer; this is a vendor-published customer report.

Nov 7, 2025

Siemens reports Microchip AMS coverage and checkpoint-debug case studies

A Siemens forum recap reports two Microchip posters: mixed-signal code-coverage analysis of a temperature/voltage sensor exposed RTL bugs missed by standalone digital verification; a battery-backed SRAM case used Symphony Get Analog Value and checkpoint save/restore for analog visibility and debug. The date records publication of the vendor recap.

Nov 7, 2025

Siemens reports TOPPAN cut full-chip CMOS image-sensor mixed-signal verification time by more than 50%

A Siemens EDA customer-story recap reports that TOPPAN presented a full-chip mixed-signal verification workflow for a complex CMOS image sensor integrating a microcontroller with analog blocks including LDO, PLL, and temperature sensors. Siemens reports that Symphony reduced TOPPAN's mixed-signal verification time by more than 50% without compromising accuracy; this is a vendor-published customer report.

Sep 12, 2025

Siemens and Ain Shams authors report UVM functional verification of an analog PLL RNM

Mariam Maurice, Rich Edelman, Mohamed Dessouky, and Ashraf Salem published an Integration paper applying constrained-random stimulus, functional coverage, assertions, and a UVM testbench to an analog PLL real-number model. The paper varies loop-filter parameters, charge-pump current, and VCO gain, and compares modeled outputs with a reference model. Its first-online date is September 12, 2025, although the journal volume is dated 2026; the reported DUT is an RNM model.

Feb 4, 2025

Accellera releases UVM-MS 1.0 with participation from seven tracked companies

On February 4, 2025, Accellera released UVM-MS 1.0, defining mixed-signal bridge and proxy components for driving and monitoring mixed-signal nets. The standard's participant list names active contributors from Cadence, Intel, Siemens EDA, Synopsys, NXP, Qualcomm, and Renesas; participation in the standard does not by itself establish deployment at those companies.

Apr 4, 2024

SiTime customer session reports AFS, Symphony, and Solido use for MEMS oscillator SoC verification

At Siemens User2User North America 2024, a customer-presented SiTime session described using Analog FastSPICE, Symphony, and Solido Design Environment to integrate analog and digital components and accelerate verification of high-precision MEMS-based oscillator SoCs.

Mar 6, 2024

Mariam Maurice presents UVM, assertions, and coverage for ADC/DAC real-number models

At DVCon U.S., Siemens EDA's Mariam Maurice presented methods for verifying ADC and DAC real-number models with randomized stimulus, functional coverage, assertions, and UVM. The paper includes constrained variation of reference and supply voltages and coverage of real-valued signal ranges. Its verification targets are modeled analog devices and their specified behavior.

Mar 4, 2024

Accellera releases Verilog-AMS 2023 under working-group chair Peter Grove of Renesas

Accellera approved Verilog-AMS 2023 for release on March 4, 2024. The update enhances analog constructs and adds compiler directives intended to support UVM-MS. Peter Grove of Renesas chaired the working group, and the standard's participant list names contributors affiliated with Analog Devices, Cadence, NXP, Qualcomm, Renesas, Siemens EDA, Synopsys, and Texas Instruments. Participation does not by itself establish company deployment.

Jul 26, 2023

Siemens and Ain Shams authors compare a SystemVerilog PLL model with transistor-level outputs

Mariam Maurice, Mohamed Dessouky, and Ashraf Salem published an IEEE Access paper on analog PLL modeling in an event-driven simulator. It uses piecewise-linear value/slope representations with SystemVerilog user-defined types and nets for higher-order loop filters, models fractional division and phase noise, and represents output loading with resolved nets. The paper compares modeled PLL outputs with transistor-level simulation.

Feb 27, 2023

Siemens EDA presents a digital-centric mixed-signal verification workshop

At DVCon U.S. on February 27, 2023, Siemens EDA presented a workshop describing digital-centric mixed-signal verification methods. Its program covers real-number modeling, constrained-random verification, assertions, functional coverage, formal techniques, low-power verification, and automated debug; the evidence documents vendor methodology advocacy rather than customer adoption.

2022

Siemens author demonstrates capacitance-aware resolved nets and SV-RNM model debugging

A DVCon U.S. 2022 paper by Siemens EDA's Mariam Maurice describes a SystemVerilog resolved-net model carrying voltage, previous voltage, current, capacitance, and resistance. It illustrates loading and filtering effects, real/logic boundary conversion, and interconnect debugging, with ADC, DAC, LDO, and image-sensor examples. The paper identifies UVM, assertions, and functional coverage as future verification work.

2014

Infineon and Mentor authors report UPF-based power-aware mixed-signal verification of a sensor SoC

A DVCon 2014 paper by Infineon and Mentor Graphics authors reports applying UPF with RTL and SPICE content to power-aware mixed-signal verification of a tire-pressure-monitoring sensor SoC. The paper says the flow exposed power blackouts, sequencing errors, missing level shifters, and incorrect isolation polarity before gate-level verification.

2014

STMicroelectronics and Mentor authors report equivalence validation of analog behavioral models

A DVCon 2014 paper by STMicroelectronics and Mentor Graphics authors describes a verification-plan-driven equivalence-validation component that applies common tests to analog implementations and behavioral models, produces pass/fail results and waivers, and can be reused across projects. The paper reports use by ST's high-speed serial-links group across HDMI, USB, and D-PHY work and says it exposed functional, connectivity, and test-mode differences before models were delivered to SoC teams.