Apple lists dedicated Mixed-Signal Model Verification roles
Apple listed Mixed-Signal Model Verification Engineer roles whose description includes self-checking SystemVerilog testbenches that compare behavioral models with source circuits, functional checks against specifications, assertions, formal logical equivalence, lint and timing checks, and flow automation across mixed-signal design teams.
Evidence
Apple Analog and Digital Design search results (historical)
Apple's historical search results dated Cupertino and Austin variants of the role to June 18, 2025; those results are no longer present at the last check.
Mixed-Signal Model Verification Engineer — Jobaaj mirror ↗
Recovery copy of the Apple role describing circuit comparison, functional tests, assertions, formal equivalence, lint, timing checks, and automation.