Astera Labs posts SerDes/PHY verification role covering RNM, AMS co-simulation, and emulation planning
Astera Labs posted a principal SerDes/PHY verification role for PCIe Gen6/7, UCIe, UALink, and Ethernet interfaces. The description calls for UVM environments, RNM and behavioral-model collaboration with analog designers, CDR and training checks, and analog handoff validation. It also assigns methodology decisions across AMS co-simulation, gate-level simulation, and emulation, and prefers emulator familiarity and pre/post-silicon correlation experience.
Evidence
Astera Labs: Principal Design Verification Engineer — SerDes/PHY IP ↗
The official Greenhouse posting describes the SerDes verification scope; its public job-board API gives first publication as August 31, 2026. It lists RNM and emulation responsibilities but does not state that RNM models execute on the emulators.