Astera Labs posted a principal SerDes/PHY verification role for PCIe Gen6/7, UCIe, UALink, and Ethernet interfaces. The description calls for UVM environments, RNM and behavioral-model collaboration with analog designers, CDR and training checks, and analog handoff validation. It also assigns methodology decisions across AMS co-simulation, gate-level simulation, and emulation, and prefers emulator familiarity and pre/post-silicon correlation experience. A related tech-lead listing checked on October 5 repeats this SerDes/PHY verification scope.