Charles Dančak reports a UVM/SystemVerilog testbench for a programmable analog filter
A DVCon U.S. paper by Charles Dančak of Betasoft Consulting extends an object-oriented testbench into UVM for a digitally programmable analog bandpass filter. A fixture encapsulates the DUT and XMODEL stimulus/measurement primitives, while UVM components randomize frequencies and modes, compare transfer gain with HSPICE reference tables and collect functional coverage. SystemVerilog assertions check supply current and bias voltage during power-down. The paper reports agreement within 2% of HSPICE for the illustrated filter example; this is not a general analog-model error bound. The official proceedings archive assigns the work to 2022; conflicting secondary citations to 2021 are not used to backdate the Event.
Evidence
A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example — paper ↗
The paper identifies the Betasoft author, UVM fixture architecture, filter tests and the example-specific HSPICE comparison.
DVCon official proceedings record: analog-filter paper ↗
The official archive identifies the author, title and year 2022. The year differs from some later bibliographies; no unverified 2021 presentation date is asserted.