Betasoft Consulting

Last researched 2026-10-193 indexed events

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Feb 26, 2025

Charles Dančak presents XMODEL-assisted SVA/PSL checks for voltage spikes in an LDO bias line

Charles Dančak of Betasoft Consulting presents an AMS assertion method for the op-amp bias line of the LDO regulator studied in his earlier UVM testbench paper. XMODEL represents the analog signal as piecewise mathematical expressions; meas_max and meas_min compute extrema over measurement intervals, which SVA/PSL properties can check for spikes missed by point sampling. Assertion evaluation remains clocked and detection depends on the model and measurement setup. This is a presented verification technique, not a general guarantee for arbitrary physical waveforms.

Mar 5, 2024

Charles Dančak presents directed and randomly sequenced UVM tests for an LDO regulator

Charles Dančak of Betasoft Consulting presents a UVM testbench for a programmable 45-nm CMOS LDO. MODELZEN extracts a SystemVerilog/XMODEL model from its Virtuoso schematic. Eight directed tests cover regulation, transients, operating modes and supply rejection; a randsequence alternates line and load transients while carrying circuit conditions between tests. A UVM event pool coordinates stimulus and measurements. One Xcelium run with seed 3947 reports four failing transient tests out of ten, including a 279-mV overshoot. These are modeled testbench results, not measured silicon or a universal coverage guarantee. This is the regulator-testbench work referenced by the later voltage-spike assertion paper.

2022

Charles Dančak reports a UVM/SystemVerilog testbench for a programmable analog filter

A DVCon U.S. paper by Charles Dančak of Betasoft Consulting extends an object-oriented testbench into UVM for a digitally programmable analog bandpass filter. A fixture encapsulates the DUT and XMODEL stimulus/measurement primitives, while UVM components randomize frequencies and modes, compare transfer gain with HSPICE reference tables and collect functional coverage. SystemVerilog assertions check supply current and bias voltage during power-down. The paper reports agreement within 2% of HSPICE for the illustrated filter example; this is not a general analog-model error bound. The official proceedings archive assigns the work to 2022; conflicting secondary citations to 2021 are not used to backdate the Event.