Charles Dančak presents directed and randomly sequenced UVM tests for an LDO regulator

Charles Dančak of Betasoft Consulting presents a UVM testbench for a programmable 45-nm CMOS LDO. MODELZEN extracts a SystemVerilog/XMODEL model from its Virtuoso schematic. Eight directed tests cover regulation, transients, operating modes and supply rejection; a randsequence alternates line and load transients while carrying circuit conditions between tests. A UVM event pool coordinates stimulus and measurements. One Xcelium run with seed 3947 reports four failing transient tests out of ten, including a 279-mV overshoot. These are modeled testbench results, not measured silicon or a universal coverage guarantee. This is the regulator-testbench work referenced by the later voltage-spike assertion paper.